JPH10275904A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transistor which can operate at a high speed and can operate even in a high-frequency domain. SOLUTION: An IGFET(insulated gate field effect transistor) 11 is constituted of source-drain areas 12, agate electrode 13, a gate insulating film 14, and channel areas 15. Each source-drain area 12 is formed in a single-crystal silicon substrate 16, and the gate electrode 13 is formed on the substrate 16 between the source-drain areas 12 through the gate insulating film 14. The channel areas 15 are formed in the substrate 16 below the gate electrode 13. Namely, thin sections 16a and thick sections 16b are alternately formed in the substrate 16 between the source-drain areas 12. In addition, the source-drain areas 12 are connected to each other through the thin and thick sections 16a and 16b, and the thin sections 16a are constituted to function and the channel areas 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device having a function of a silicon quantum wire, a method of manufacturing the same, and an IGFET using the silicon quantum wire as a channel region. And a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as the size of an LSI approaches the nanometer scale, the improvement of the operation speed of the LSI in the conventional device structure has started to be limited. In order to improve the operation speed of the LSI, it is sufficient to increase the carrier mobility. One-dimensional quantum devices have attracted attention as a technology for realizing high carrier mobility.

[0003] In a one-dimensional quantum device, high carrier mobility can be obtained by causing carriers to travel on a silicon ultrafine wire called a silicon quantum wire, which is formed as thin as a quantum effect. When a one-dimensional quantum device with high carrier mobility is used, a transistor that can operate in a high-frequency region can be realized.

FIG. 4 shows an IGFET (Insulated Ga) using a conventional silicon quantum wire and a one-dimensional quantum device.
te Field Effect Transistor). Step 1 (see FIG. 4A); forming a silicon oxide film 52 on a single crystal silicon substrate 51 and forming a single crystal silicon layer 53 on the silicon oxide film 52 SOI (Silicon On Insulato)
r) Form the substrate 54. Next, the single-crystal silicon layer 53
A silicon oxide film 55 having a constant line width is formed thereon.

Step 2 (see FIG. 4B): The single-crystal silicon layer 53 is patterned by a wet etching method using an ethylenediamine-based etchant with the silicon oxide film 55 as an etching mask. At this time, overetching occurs in which the etchant erodes the single crystal silicon layer 53 from the periphery of the silicon oxide film 55,
The line width of the fine silicon wire 56 composed of the patterned single crystal silicon layer 53 is smaller than the line width of the silicon oxide film 55. In addition, both ends (not shown) of the silicon thin wire 56
Is a single-crystal silicon layer 53 that has not been patterned
(Not shown).

Step 3 (see FIG. 4C): The silicon oxide film 55 and the silicon oxide film 52 below the silicon fine wire 56 are removed by a wet etching method using a hydrofluoric acid solution as an etchant. In addition, the silicon fine wire 56
(Not shown) are held by an unpatterned single-crystal silicon layer 53 (not shown).

Step 4 (see FIG. 4D): A silicon oxide film 57 is formed on the outer peripheral surface of the silicon fine wire 56 by using a thermal oxidation method.
To form Next, CVD (Phisical Vapor Depositio
A doped polysilicon film 58 is formed on the entire surface of the device including the thin silicon wires 56 by using the n) method.

Thereafter, source / drain regions (not shown) are formed by implanting impurity ions into a single-crystal silicon layer 53 (not shown) connected to both ends of the fine silicon wires 56. As a result, the IGFET using the doped polysilicon film 58 as a gate electrode and the silicon thin wire 56 as a channel region
59 is completed.

Here, by reducing the line width and the line height of the silicon fine line 56 to a level at which the quantum effect appears,
The silicon wire 56 can function as a silicon quantum wire. Then, in the IGFET 59, a high carrier mobility can be obtained by causing the carriers to travel along the thin silicon wires 56 forming the channel region. As a result, the operating speed of the IGFET 59 is increased, and in addition, the IGFET 59 can operate in a high frequency range.

[0010]

In the IGFET 59, the outer periphery of the thin silicon wire 56 is surrounded by the silicon oxide film 57. Therefore, the traveling of the carriers in the silicon thin wire 56 is easily affected by the state of the interface between the silicon thin wire 56 and the silicon oxide film 57 and the stress applied from the silicon oxide film 57 to the silicon thin wire 56.

That is, if an interface state between the silicon fine wire 56 and the silicon oxide film 57 is generated more than necessary or the stress applied to the silicon fine wire 56 from the silicon oxide film 57 becomes large, the quantum effect does not appear and the silicon fine wire 56 It no longer functions as a silicon quantum wire. As a result, IG
The FET 59 cannot obtain a high carrier mobility, and its operation speed is reduced, and furthermore, it becomes inoperable in a high frequency region.

The present invention has been made to solve the above problems, and has the following objects. 1] To provide a semiconductor device having the function of a silicon quantum wire and a method of manufacturing the same.

2] Provided is a semiconductor device having an IGFET having a high operating speed and capable of operating even in a high frequency range, and a method of manufacturing the same.

[0014]

The gist of the present invention is that a thin portion is formed linearly in a silicon layer.

The gist of the present invention is that a thin portion is formed in a linear shape in a silicon layer in an SOI substrate. The third aspect of the present invention provides the SOI
The gist is that thin portions and thick portions are alternately formed in a stripe shape in a silicon layer on a substrate.

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the IG uses a thin portion of the silicon layer as a channel region.
The gist is to provide an FET.

According to a fifth aspect of the present invention, a step of forming a groove in the first silicon substrate, a step of forming an insulating film on the first silicon substrate including the inside of the groove, A step of forming a silicon film, a step of bonding a second silicon substrate on the silicon film, and a step of uniformly polishing and flattening a surface of the first silicon substrate opposite to a surface on which a groove is formed. Forming an SOI substrate composed of the first silicon substrate and the insulating film, and forming a thin portion linearly at the bottom of the groove of the first silicon substrate. And

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifth aspect, a step of forming a gate insulating film on a thin portion of the first silicon substrate; The gist of the present invention is that a step of forming a gate electrode on an insulating film and a step of forming a source / drain region by doping an impurity in a portion of the first silicon substrate sandwiching a thin film portion are provided. .

In the embodiments of the invention described below, the “silicon layer” described in the claims or the means for solving the problems corresponds to the single-crystal silicon substrate 16, and the “insulating film” similarly Corresponding to the silicon oxide film 17,
Similarly, the “first silicon substrate” is a single-crystal silicon substrate 1
6, and the “second silicon substrate” also corresponds to the single crystal silicon substrate 19.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1A shows a plan view of the IGFET 11 of the present embodiment. FIG. 1B is a sectional view taken along line XX of FIG.

The IGFET 11 includes a source / drain region 12, a gate electrode 13, a gate insulating film 14, and a channel region 15. Each source / drain region 1
2 is formed in a single crystal silicon substrate 21.

The gate electrode 13 is formed on the single-crystal silicon substrate 16 between the source / drain regions 12 via the gate insulating film 14. Channel region 15 is formed in single-crystal silicon substrate 16 below gate electrode 13. That is, the single-crystal silicon substrate 16 between each source / drain region 12 has a thin portion 16 a and a thick portion 1 a along the channel direction of the IGFET 11.
6b are alternately formed in a stripe shape. That is, the source / drain regions 12 are connected by the linear portions 16a and 16b. The thin portion 16a functions as the channel region 15.

In the single crystal silicon substrate 16, a groove 33 is formed on a surface opposite to a surface on which the gate electrode 13 and the gate insulating film 14 are formed. That is, in the single-crystal silicon substrate 16, a portion corresponding to the bottom of the groove 33 becomes a thin portion 16a, and a portion without the groove 33 becomes a thick portion 16b.

The single crystal silicon substrate 16 is bonded on a single crystal silicon substrate 19 via a silicon oxide film 17 and a polysilicon film 18. That is, the polysilicon film 18 having the ridge 18a is formed on the single crystal silicon substrate 19. The protrusions 18 a of the polysilicon film 18 are formed so as to fit inside the grooves 33 of the single crystal silicon substrate 16. Polysilicon film 18
A silicon oxide film 17 is formed thereon. That is,
A portion 16a of the single-crystal silicon substrate 16 having a small thickness is formed on the protrusion 18a of the polysilicon film 18.

Next, a method of manufacturing the IGFET 11 will be sequentially described with reference to FIGS. Step 1 (see FIG. 2A): CVD method or PVD (Ph
a silicon oxide film 31 (thickness: 100 nm) on the single crystal silicon substrate 16 by using the ysical vapor deposition method.
To form

Step 2 (see FIG. 2B): A resist pattern 32 made of a photoresist film is formed on the silicon oxide film 31. Step 3 (see FIG. 2C): The silicon oxide film 31 is patterned by an anisotropic etching method using the resist pattern 32 as an etching mask. Next, the single crystal silicon substrate 16 is etched by an anisotropic etching method using the patterned silicon oxide film 31 as an etching mask to form a groove 33 (width: 0.2 μm).
, Depth: 0.2 μm).

Step 4 (see FIG. 2D): The resist pattern 32 and the silicon oxide film 31 are removed. Step 5 (see FIG. 3A): The grooves 33 are formed by using a thermal oxidation method.
A silicon oxide film 17 (thickness: 10 nm) is formed on the surface of the single crystal silicon substrate 16 including the inside of the substrate. Next, CVD
The polysilicon film 18 (thickness: 200 n) is formed on the silicon oxide film 17 including the inside of the trench 33 by using the PVD method or the PVD method.
m). At this time, the ridge 18a is formed by the polysilicon film 18 buried inside the groove 33.

Step 6 (see FIG. 3B): The surface of the polysilicon film 18 is uniformly polished and flattened. Next, a single crystal silicon substrate 19 is bonded on the polysilicon film 18.

Step 7 (see FIG. 3C): The surface of the single-crystal silicon substrate 16 opposite to the surface where the grooves 33 are formed is polished and flattened. Then, ridge 18a
The thickness of the single-crystal silicon substrate 16 on the top of
It becomes thinner than that of the part without. As a result, a thin portion 16a and a thick portion 16b are formed on the single crystal silicon substrate 16. In addition, each member (16 to 19)
Is formed.

Step 8 (see FIG. 1): A gate insulating film 14 is formed on the single crystal silicon substrate 16. Next, a conductive film is formed on the gate insulating film 14 by using the CVD method or the PVD method, and the conductive film is patterned to form the gate electrode 13.
To form Subsequently, source / drain regions 12 are formed by implanting impurity ions into the single crystal silicon substrate 16 using the gate electrode 13 as an ion implantation mask.

As described above, according to the present embodiment, the following operations and effects can be obtained. (1) When operating the IGFET 11 in a fully depleted type,
The threshold voltage of each portion 16 of the single crystal silicon substrate 16 is
a and 16b. That is, in the single-crystal silicon substrate 16, no inversion layer is formed because no carrier is generated in the thick portion 16b, and carriers are generated only in the thin portion 16a to form an inversion layer.
Therefore, by controlling the voltage of the source / drain region 12, a large amount of carriers travels only in the thin portion 16a, while almost no carriers travel in the thick portion 16b of the single crystal silicon substrate 16. Can be done.

(2) According to the above (1), the width and height (film thickness) of the thin film portion 16a in the single-crystal silicon substrate 16 are reduced to a level at which the quantum effect appears, whereby the film thickness is reduced. The thin portion 16a can function as a silicon quantum wire.

(3) The width of the thin portion 16 a of the single crystal silicon substrate 16 is equal to the width of the groove 33.
That is, by adjusting the width of the groove 33 of the single-crystal silicon substrate 16, the width of the thin portion 16a can be freely adjusted.

The height (film thickness) of the thin portion 16 a of the single crystal silicon substrate 16 can be freely adjusted by polishing the single crystal silicon substrate 16 in step 7.

Accordingly, the width and height of the portion 16a having a small thickness in the single crystal silicon substrate 16 can be freely set, and the operation and effect (2) can be easily obtained.

(4) The thin portion 16 a of the single crystal silicon substrate 16 functions as the channel region 15 of the IGFET 11. Therefore, in the IGFET 11, the channel region 1 functioning as a silicon quantum wire is
By moving the carrier 5, high carrier mobility can be obtained. As a result, the operation speed of the IGFET 11 increases, and in addition, the IGFET 11 can operate even in a high frequency range.

(5) The silicon oxide film 17 is arranged under the thin portion 16a (channel region 15) of the single crystal silicon substrate 16. Therefore, the carrier travels in the channel region 15 between the silicon oxide film 17 disposed thereunder and the single crystal silicon substrate 1.
6 and the stress applied from the silicon oxide film 17 to the single crystal silicon substrate 16.

However, the thin portion 16a of the single crystal silicon substrate 16 has no silicon oxide film disposed on both sides thereof. Therefore, there is no possibility that an interface level between the channel region 15 and the silicon oxide film 17 is generated more than necessary, and no excessive stress is applied to the channel region 15 from the silicon oxide film 17.

Therefore, the quantum effect appears stably in the thin portion 16a (channel region 15) of the single crystal silicon substrate 16, and the portion 16a reliably functions as a silicon quantum wire. As a result, the IGFET 11 can stably obtain a high carrier mobility.

(6) The technique of forming the groove 33 in the single-crystal silicon substrate 16, the technique of polishing the single-crystal silicon substrate 16, and the technique of bonding the single-crystal silicon substrates 16 and 19 are all widely used conventionally. ing. The technology for forming the gate insulating film 14, the gate electrode 13, and the source / drain region 12 is the same as the general technology for manufacturing an IGFET. That is, the IGFET 11 does not require any special technology, and can be easily and easily manufactured.

Incidentally, the width of the groove 33 in the single-crystal silicon substrate 16 is suitably set in the range of 0.1 to 0.5 μm, preferably 0.1 to 0.2 μm. . If it is larger than this range, the quantum effect tends not to appear, and if it is thinner, the groove 33 tends not to be formed.

The depth of the groove 33 in the single-crystal silicon substrate 16 is suitably set in the range of 0.2 to 1 μm, preferably 0.2 to 0.5 μm. If it is larger than this range, etching tends to be difficult, and if it is shallower, the quantum effect tends not to appear.

The height (thickness) of the portion 16a having a small thickness in the single crystal silicon substrate 16 is in the range of 0.1 to 0.1.
It is appropriate to set it in the range of 5 nm, and preferably, it is set to 0.1 nm.
It is preferable to set the range of 1 to 0.2 nm. If it is larger than this range, the IGFET 11 tends to be partially depleted, and the quantum effect does not appear. If it is smaller, the IGFET 11 tends to be easily affected by the interface between the silicon fine wire 56 and the silicon oxide film 57.

The above embodiment may be modified as follows, and the same operation and effect can be obtained in such a case. (1) The single crystal silicon substrate 16 is replaced with a polysilicon layer or an amorphous silicon layer.

(2) The silicon oxide film 17 is replaced with another insulating film such as a silicon nitride film. (3) The polysilicon film 18 is replaced with an amorphous silicon film or a silicon oxide film.

(4) When the width of the groove 33 of the single crystal silicon substrate 16 is small, the inside of the groove 33 is covered with the silicon oxide film 17.
And the protrusion 18a of the polysilicon film 18 may be omitted.

[0047]

According to the invention described in any one of claims 1 to 3, it is possible to provide a semiconductor device having the function of a silicon quantum wire. That is, the thin portion of the silicon layer functions as a silicon quantum wire.

According to the fourth aspect of the present invention, it is possible to provide a semiconductor device having an IGFET which operates at a high speed and can operate even in a high frequency range. That is, since a thin portion of the silicon layer functioning as a silicon quantum wire is used as a channel region, an IGFET that operates at a high speed and can operate even in a high-frequency region can be obtained.

According to the fifth aspect of the present invention, it is possible to provide a method of manufacturing a semiconductor device having the function of a silicon quantum wire. According to the sixth aspect of the present invention, it is possible to provide a method of manufacturing a semiconductor device having an IGFET which operates at a high speed and can operate even in a high frequency range.

[Brief description of the drawings]

FIG. 1A is a plan view of one embodiment. FIG. 1 (b)
2 is a sectional view taken along line XX of FIG.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of the embodiment.

FIG. 3 is a sectional view for explaining a manufacturing process of the embodiment.

FIG. 4 is a cross-sectional view for explaining a conventional manufacturing process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... IGFET 12 ... Source / drain region 13 ... Gate electrode 14 ... Gate insulating film 15 ... Channel region 16 ... Single-crystal silicon substrate as a silicon layer or a first silicon substrate 17 ... Silicon oxide film as an insulating film 18 ... Poly Silicon film 19 ... Single-crystal silicon substrate as second silicon substrate 33 ... Groove

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 622 626C

Claims (6)

[Claims] 1. A semiconductor device in which a thin portion is formed linearly in a silicon layer. 2. A semiconductor device in which a thin portion is formed linearly in a silicon layer of an SOI substrate. 3. A semiconductor device in which thin portions and thick portions are alternately formed in a silicon layer on an SOI substrate in a stripe shape. 4. The semiconductor device according to claim 1, further comprising an IGFET using a thin portion of said silicon layer as a channel region. 5. A step of forming a groove in the first silicon substrate, a step of forming an insulating film on the first silicon substrate including the inside of the groove, and a step of forming a silicon film on the insulating film Bonding a second silicon substrate on the silicon film, and uniformly polishing and flattening a surface of the first silicon substrate opposite to a surface on which the groove is formed, thereby forming a first silicon substrate. Forming an SOI substrate comprising a substrate and an insulating film,
Forming a thin portion in a linear shape at the bottom of the groove of the first silicon substrate in a linear manner. 6. The method for manufacturing a semiconductor device according to claim 5, wherein a step of forming a gate insulating film on the thin portion of the first silicon substrate; and forming a gate electrode on the gate insulating film. A method of manufacturing a semiconductor device, comprising: a step of forming; and a step of forming a source / drain region by doping an impurity into a portion of a first silicon substrate which sandwiches a thin film portion.