JPH10275812A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a semiconductor device in switching speed by a method, wherein a first single crystal silicon layer is formed on a semiconductor substrate, and polycrystalline silicon layers which are sporadically laid into a prescribed pattern and a second single crystal silicon layer where the polycrystalline silicon layers are embedded are formed on the first single crystal silicon layer. SOLUTION: A first-single crystal silicon layer 2 is formed on a semiconductor substrate 3, and a second single-crystal silicon layer of multilayered structure where polycrystalline silicon regions 1 sporadically arranged in a prescribed pattern in a plan view from above the semiconductor substrate 3 are embedded is formed on the first single crystal silicon layer 2. That is, the polycrystalline silicon region 1 is formed 9 μm in length a and 1 μm in width b, a space c between the first and second polycrystalline regions 1 and another space c between the second and third polycrystalline regions 1 are set at 0.1 to 10 μm or so. By this setup, a semiconductor device of this constitution can be enhanced in switching speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a thyristor, an IGBT (Insu).
lated Gate Bipolar Transi
Stor), CMOSFET and the like.

[0002]

2. Description of the Related Art Semiconductor devices include thyristors and IGBTs used as power devices.

[0003] Such thyristors and IGBTs are widely used in switching power supplies, motor control, ultrasonic application equipment and the like. However, diversification of electronic devices is expected to further improve the switching speed of thyristors and IGBTs.

[0004] As a measure for improving the switching speed of the thyristor and the IGBT, the following is shown in order to shorten the lifetime of a part or all of the carriers existing inside the semiconductor substrate.
The following three methods can be applied.

A method of diffusing a heavy metal such as gold or platinum into a semiconductor device A heavy metal such as gold or platinum serves as a carrier recombination center in a semiconductor substrate, so that the carrier lifetime can be shortened.

A method of irradiating a semiconductor device with radiation Since a semiconductor substrate is damaged by irradiating the semiconductor device with radiation, recombination centers are generated in the semiconductor substrate, and the lifetime of carriers can be shortened. it can.

A method of injecting a light mass substance such as an electron beam, hydrogen, or helium into a semiconductor substrate The semiconductor substrate is damaged by the injection of a light mass substance such as an electron beam, hydrogen, or helium. Occurs and shortens the lifetime of the carrier.

[0008] However, the above conventional methods have the following problems.

In the method described above, heavy metals such as gold and platinum cannot be partially diffused in the semiconductor substrate but diffuse throughout the semiconductor substrate. Moreover,
Since the diffusion speed of the heavy metal is high, it is relatively difficult to suppress the diffusion. In addition, heavy metals such as gold and platinum damage pn junctions and the like in devices formed on the semiconductor substrate, that is, devices formed on the surface of the substrate, and thus have a bad influence on gate characteristics or junction characteristics.

Therefore, by diffusing a heavy metal such as gold or platinum into the semiconductor substrate, the purpose of shortening the lifetime of the carrier can be achieved, although the heavy metal becomes the recombination center of the carrier. , IGBTs, the deterioration of device characteristics such as an increase in leakage current and an increase in ON voltage is inevitable.

In addition, this method also damages the entire semiconductor wafer similarly to the above-mentioned method. However,
In the method (2), the gate characteristics and the junction characteristics can be improved by performing annealing at a temperature of 300 ° C. to 400 ° C. in, for example, an inert gas after the irradiation of radiation, so that the on-voltage and the like can be improved. Recovery can be performed and deterioration of device characteristics can be avoided.

However, the recombination center inside the semiconductor substrate disappears at the same time by this annealing treatment. Therefore, there is a trade-off relationship between the recovery of the device characteristics and the shortening of the carrier lifetime, and the ON voltage is completely recovered. There is a problem that it cannot be done.

According to the method (1), the controllability is better than those of the methods (1) and (2), so that damage can be partially caused in a cross-sectional direction in the semiconductor substrate, that is, in a depth direction. At the same time, a large area inside the semiconductor substrate is damaged. Therefore, the semiconductor element region formed on the surface of the semiconductor substrate is also damaged.
The ON voltage of the thyristor and the IGBT deteriorates.

In this case, as in the above method, the gate voltage and the junction characteristic are generally improved by annealing to recover the on-state voltage. Since the internal recombination center also disappears, there is a problem that the on-state voltage cannot be completely recovered.

On the other hand, in CMOSFET, gettering technology is widely used as a countermeasure against metal contamination in a process of manufacturing a semiconductor device.

This method is a technique for collecting metal contaminants in a region where an element is not formed on a semiconductor substrate, that is, in an inactive region. This is a technology to collect contaminants. As typical gettering methods, there are two methods described below.

Intrinsic gettering technology in which a crystal defect layer is automatically formed in an annealing step in a semiconductor manufacturing process inside a semiconductor substrate, and the formed crystal defect layer is used as a gettering layer.

A crystal defect is generated by roughening the back surface of the semiconductor substrate by a sand blast method, or an crystal in which a polycrystalline silicon layer is formed on the back surface of the semiconductor substrate and the formed polycrystalline silicon layer is used as a metal contamination absorbing layer. Thick gettering technology.

In the technique described above, a crystal defect layer is formed when oxygen mixed into a semiconductor substrate becomes a gettering center in an annealing step. However, in this case, in order to prevent the device characteristics from deteriorating, it is necessary to form a crystal defect layer only inside the semiconductor substrate without generating crystal defects near the surface of the semiconductor substrate.

However, since the occurrence of the crystal defects is highly dependent on the semiconductor fabrication process, it is necessary to optimize the annealing temperature and the like in the annealing step for each type of semiconductor device. For example, in a manufacturing process of a CMOSFET, it is necessary to optimize annealing conditions such as an annealing temperature in a well diffusion step and an annealing step in a field oxide film forming step.

For example, the well diffusion step is typically 110
This step is performed at a high temperature of 0 ° C. or more, and in this step, oxygen existing in the semiconductor substrate near the surface of the semiconductor substrate escapes to the outside. Then, after this, at a temperature of 900 ° C. or more,
By growing a thick silicon oxide film, a crystal defect layer caused by oxygen precipitation can be formed inside the semiconductor substrate.

However, if the outward diffusion of oxygen is insufficient during the annealing at a high temperature of 1100 ° C. or higher, crystal defects are formed even on the semiconductor substrate surface, which is the semiconductor element formation region, and the device characteristics are reduced. Is significantly worsened.

Conversely, if oxygen in the semiconductor substrate escapes too much in the annealing step, a crystal defect layer cannot be formed in the semiconductor substrate, and a gettering effect cannot be expected.

Also, in the field oxide film forming step, as in the well diffusion step, unless an appropriate annealing temperature is selected, no crystal defects occur due to the dependence on the amount of oxygen in the semiconductor substrate. As a result, the formation of crystal defects extends to the surface of the semiconductor substrate.

In a semiconductor device of a type in which a current flows from the front surface of the semiconductor substrate to the back surface, the resistance increases inside the semiconductor substrate. This increase in resistance inside the semiconductor substrate has an adverse effect on all the semiconductor elements on all the semiconductor chips formed on the same substrate, that is, on the wafer. In this manner, device characteristics such as an increase in the ON voltage of the thyristor and the IGBT are deteriorated, so that it is difficult to use the above method.

That is, the method cannot be used for a thyristor or an IGBT of a type in which a current flows in the cross-sectional direction of a substrate, and is highly dependent on a manufacturing process. Was necessary.

The technique has a feature that the gettering layer can be surely formed without depending on the process. On the other hand, since the gettering layer is formed on the back surface of the semiconductor substrate, The distance from the active region where the device is formed, that is, the surface of the semiconductor substrate to the gettering layer is increased.

Here, in the semiconductor device manufacturing process, generally, the higher the temperature, the faster the diffusion rate of impurities and metals in the semiconductor substrate. Further, since the crystal defect layer for gettering, that is, the gettering layer, is formed at a position of several tens of μm from the surface of the semiconductor substrate, the distance between the surface of the semiconductor substrate and the gettering layer becomes long.
Therefore, the effect of gettering cannot be expected unless the temperature at which the metal is sufficiently diffused is applied as the annealing process.

However, with the miniaturization of elements, lowering the temperature in the semiconductor device manufacturing process has been applied, and with the permeation of this lowering technology, a gettering layer has become necessary in a region closer to the surface of the semiconductor substrate. With it,
With the progress of miniaturization of devices, a reduction in processing temperature particularly in a process after formation of a gate oxide film is being studied.

For example, in a semiconductor device having a pattern rule of about 4 μm, when the annealing temperature of 1000 ° C. becomes 0.5 μm or less, the temperature becomes 900 ° C. or less. Due to the lowering of the annealing temperature of 100 ° C., the above-mentioned metal diffusion distance is shortened by about one digit. For this reason, for example, as the temperature of the semiconductor device manufacturing process decreases, the effect of the gettering technique is reduced.

In other words, according to the method (1), the distance between the gettering layer and the device formation region is long. The effect of preventing metal contamination by the extrinsic gettering technology is reduced.

As described above, thyristor, IGBT
In the application of the intrinsic gettering technology or the extrinsic gettering technology as a countermeasure for metal contamination in the above, there is a problem that various secondary problems occur.

Therefore, it has been difficult to realize both a countermeasure against speed and prevention of metal contamination in a semiconductor device, particularly in a vertical power device.

[0034]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and improves the switching speed of a semiconductor device by forming a carrier annihilation region inside a semiconductor substrate. The purpose is to be.

Another object of the present invention is to provide a structure in which the carrier annihilation region is not accompanied by deterioration of the on-voltage.

Another object of the present invention is to form a gettering layer of a polycrystalline silicon region in the semiconductor substrate in the vicinity of a substrate surface on which elements are formed, thereby achieving a stable gettering effect independent of a process. To get.

Another object of the present invention is to reduce the on-voltage of a vertical power device in which a current flows from the front surface to the back surface of a semiconductor substrate, which is impossible with the conventional intrinsic gettering technology. It is to propose a gettering method that can be applied without any problem.

[0038]

According to the present invention, there is provided a semiconductor device comprising:
A polycrystalline silicon layer partially present in a predetermined pattern and a second monocrystalline silicon layer formed by embedding the polycrystalline silicon layer are formed on a first monocrystalline silicon layer formed on a semiconductor substrate. It is characterized by including.

Therefore, according to the semiconductor device of the present invention, since the plurality of polycrystalline silicon layers can be used as recombination centers of carriers, respectively, the semiconductor wafer is not damaged and device characteristics are deteriorated. The switching speed can be improved without any problem. Further, since the solid-phase epitaxial growth method is applied as a process for forming the second single-crystal silicon layer, a gettering region is formed near the surface of the second single-crystal silicon layer where an element is formed on the semiconductor substrate. Can be formed, a stable gettering effect independent of the manufacturing process can be obtained, the manufacturing process can be reduced in temperature, and it is possible to cope with miniaturization of elements.

In this semiconductor device, a plurality of the polycrystalline silicon layers are formed in a semiconductor chip in a linear shape with a constant width and at a constant interval, and the polycrystalline silicon layers are formed in a linear shape with the plural lines. The polycrystalline silicon layer is formed in a lattice-like or island-like pattern by forming a plurality of the polycrystalline silicon layers at regular intervals on a straight line having a constant width so as to intersect with the polycrystalline silicon layer. It is desirable that

According to this semiconductor device, since the area occupied by the polycrystalline silicon layer in the semiconductor device can be increased, the effect can be significantly improved.

This semiconductor device can be applied to an insulated gate semiconductor device that controls formation / non-formation of a channel in a channel formation region by a voltage applied to a gate electrode.

According to this semiconductor device, even when the present invention is applied to a vertical power device in which a current flows from the front surface to the back surface of the semiconductor substrate, the above effect can be obtained without deterioration of the on-voltage.

Further, in this semiconductor device, the gate electrode may have a trench structure.

According to this semiconductor device, since the element can be further miniaturized, it is possible to greatly reduce the size of the semiconductor device.

Further, in this semiconductor device, the polycrystalline silicon layer of the present invention is formed in substantially the same volume, and is formed in plural at the same depth in the depth direction of the semiconductor substrate. Is desirable.

According to this semiconductor device, by using the polycrystalline silicon layer as the carrier annihilation region, the carrier annihilation effect can be exerted on the entire surface of the semiconductor chip and the semiconductor wafer.

In this semiconductor device, it is preferable that the polycrystalline silicon layers are formed at a predetermined interval.

According to this semiconductor device, in addition to the above-mentioned points, the effect of increasing the on-voltage when the device is turned on can be reduced to a negligible level.

In this semiconductor device, it is preferable that the polycrystalline silicon layer is divided into a plurality of layers in a depth direction of the semiconductor substrate.

According to this semiconductor device, more polycrystalline silicon layers can be formed in the semiconductor chip. Therefore, by using the polycrystalline silicon layer as the carrier annihilation region, the semiconductor chip and the entire surface of the semiconductor wafer can be formed. A carrier extinction effect can be achieved.

This semiconductor device comprises a thyristor and an IG
BT (Insulated Gate Bipolar)
The present invention can be applied to a vertical semiconductor device such as a transistor, and the same effects as those described above can be obtained.

The semiconductor device of the present invention can be applied to a CMOSFET.

According to this semiconductor device, by applying the solid phase epitaxial growth method as a manufacturing process, the gettering layer can be formed without increasing the process and without depending on the process. The yield can be improved, a low-temperature process can be applied, and the device can be miniaturized.

The semiconductor device of the present invention is obtained by the following manufacturing method.

In this method of manufacturing a semiconductor device, the semiconductor substrate is formed of single-crystal silicon, and a polycrystalline silicon layer is formed on the surface of the semiconductor substrate.
A second step of forming a silicon oxide film so as to cover the surface of the polycrystalline silicon layer, and forming a polycrystalline silicon layer on the surface of the silicon oxide film and the semiconductor substrate, and then performing a heat treatment. A third step of forming a single-crystal silicon layer by a solid phase epitaxial growth method starting from a seed region consisting of the exposed surface of the semiconductor substrate.

According to the semiconductor device obtained by this manufacturing method, the semiconductor device can be easily formed by the solid phase epitaxial growth method.
An element is formed on the semiconductor substrate, and a gettering region can be formed in the vicinity of the surface of the single crystal silicon layer. Therefore, a stable gettering effect independent of a manufacturing process can be obtained, and a manufacturing process can be performed. The temperature can be reduced, and the device can be miniaturized.

[0058]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG.
2 (a) and 2 (b) are drawings showing a planar layout pattern of a polycrystalline silicon region, and FIGS. 2 (a) and 2 (b) are cross-sectional views of main parts of a device including the polycrystalline silicon region.

FIGS. 2A and 2B are schematic cross-sectional views of a main part of the device where the polycrystalline silicon region 1 is formed. In FIG. 2, the description of the semiconductor element region such as the impurity diffusion layer is omitted.

In FIG. 2A, a plurality of polycrystalline silicon regions 1 are formed on a silicon substrate 3 at a constant interval.
Further, they are formed of the same layer. The plurality of polycrystalline silicon regions 1 are formed by covering the surface of the polycrystalline silicon layer with a silicon oxide film. On this polycrystalline silicon region 1, a single crystal silicon region 2 is formed by solid phase epitaxial growth (SPE; Soli).
d Phase Epitaxy). The process for fabricating the device and the specific description of the SPE method will be described later.

FIG. 2B shows the state shown in FIG.
A plurality of, for example, 3
A cross-sectional view of a main part of a device formed by layers is shown. Each of the plurality of polycrystalline silicon regions 1 is formed so as to be covered by the single crystal silicon region 2.

The semiconductor device of FIG. 2B is different from the semiconductor device of FIG. 2A in that the process of forming the polycrystalline silicon region 1 and the process of forming the single crystal silicon region 2 must be performed three times each. No. Therefore, although the fabrication process as a semiconductor device is complicated, the number of polycrystalline silicon regions is increased several times in the same region when viewed two-dimensionally, so that the effect of preventing metal contamination and improving the switching speed is very large. growing.

FIGS. 1 (a) and 1 (b) are plan layout patterns of the polycrystalline silicon region shown in FIG. 2 (a).
2 shows a pattern on a plane along the line A, and shows a plane layout pattern of a plurality of polycrystalline silicon regions 1 and a plurality of single crystal silicon regions 2 formed on the semiconductor substrate 3 (see FIG. 2).

In the semiconductor device shown in FIG. 1A, the polycrystalline silicon regions 1 are formed with substantially the same volume, and a plurality of the polycrystalline silicon regions 1 are arranged at regular intervals vertically and horizontally. It is formed by being arranged. Here, in this specification,
The polycrystalline silicon region 1 refers to the entire region composed of a polycrystalline silicon layer whose surface is covered with a silicon oxide film, as described later.

In the semiconductor device shown in FIG. 1B, the polycrystalline silicon region 1 shown in FIG.
The polycrystalline silicon region of (b) is laid out continuously. That is, the polycrystalline silicon region 1 is formed in a lattice on the semiconductor substrate 3, and inside the polycrystalline silicon region 1 formed in the lattice, that is, in a portion where the polycrystalline silicon region 1 is not formed. The single crystal silicon region 2 is formed.

The planar layout pattern of the polycrystalline silicon region / single crystal silicon region as shown in FIGS. 1A and 1B is applied to all the semiconductor chips formed on the semiconductor substrate 3. Also has the same pattern. That is, a large number of polycrystalline silicon regions are formed on the entire surface of the semiconductor substrate so as to be buried under the semiconductor element region. Then, as shown in FIGS. 1 (a) and 1 (b), when the semiconductor substrate is viewed in a plan view from above, the polycrystalline silicon region 1 is formed by being partially buried with a predetermined pattern. I have.

Next, the semiconductor device of the present embodiment (FIG. 2)
The process of (a) for forming the polycrystalline silicon region and the single crystal silicon region will be described with reference to FIG.

FIGS. 3A to 3E show a process of forming a polycrystalline silicon region and a single crystal silicon region in the semiconductor device of the present embodiment.

A polycrystalline silicon layer 40 is formed on the silicon substrate 3.
The, for example, by low pressure CVD, about 630 ° C., at monosilane S _i H _4, is formed to a thickness of about 0.05 to 1.0 [mu] m. The thickness of this polycrystalline silicon layer 40 can be controlled to a desired thickness by process control.
(FIG. 3A) Next, the polycrystalline silicon layer 40 is processed into a predetermined pattern by photolithography and etching such as RIE to form a plurality of polycrystalline silicon layers 4. (FIG. 3 (b)) Thereafter, the semiconductor wafer is placed in an oxidation treatment apparatus such as a diffusion furnace, and the surface of the semiconductor wafer is oxidized in an atmosphere of about 600 ° C. so that the surface of each polycrystalline silicon layer 4 is In addition, a silicon oxide film 50 is formed on the entire surface of the semiconductor substrate 3. (FIG. 3C) Then, the silicon oxide film 50 is patterned again by etching such as photolithography and RIE, and the silicon oxide film 5 is formed in a pattern covering the surface of each polycrystalline silicon layer 40. Thereby, polycrystalline silicon region 1 is formed. In the manufacturing process of the semiconductor device, the thickness of the polycrystalline silicon region 1 can be set to, for example, about 0.05 to 1.0 μm (FIG. 3D).

Next, the natural oxide film formed on the semiconductor substrate 3 is removed, for example, by immersing it in a dilute hydrogen fluoride solution. Next, after a polycrystalline silicon layer is formed on the entire surface of the semiconductor substrate 3 by, for example, a low pressure CVD method, about 6
The semiconductor substrate 3 is annealed at a predetermined time of about 00 ° C.
Starting from a seed part (seed crystal part) consisting of an exposed part of
PE is generated, and the polycrystalline silicon layer is monocrystallized to form a monocrystalline silicon layer 2. This allows
Each of the polycrystalline silicon regions 1 is filled with a single crystal silicon region 2 formed by the SPE method (FIG. 3).
(E)).

For the SPE method, a method previously proposed by the present applicant (the technique disclosed in Japanese Patent Application No. 6-193604) can be used.

In this manner, the polycrystalline silicon region 1 is formed by the processes shown in FIGS.
A single crystal silicon region 2 is formed on the entire surface of semiconductor substrate 3 so as to be buried.

For forming the single-crystal silicon epitaxial layer 2 (step of FIG. 3E), a method other than the method described above can be applied. That is, the SPE method can be used for embedding the polycrystalline silicon layer 1, and in the subsequent single crystal silicon region forming process, an epitaxial growth method using a normal pressure CVD method with a high film forming rate can be used.

As described above, the semiconductor device of the present invention can be manufactured by the semiconductor device manufacturing process utilizing the SPE method. In this semiconductor device, switching speed can be improved without deterioration of on-resistance.

That is, in the semiconductor device of the present invention, in the polycrystalline silicon region 1, the carrier lifetime is extremely short, and itself functions as a carrier annihilation region. Therefore, it is used as a power device, for example, a thyristor, an IGBT (Insulated Ga
When applied to te Bipolar Transistor, etc., the switching speed can be improved.

The effect of the carrier annihilation region depends on the impurity concentration of the single crystal silicon region.
The impurity concentration of the single crystal silicon region is 1 × 10 ¹³ to
A further effect can be obtained by setting it to about 1 × 10 ¹⁶ cm ⁻³ .

Since the carrier lifetime can be eliminated within a range of about 10 μm around the polycrystalline silicon region 1, the distance between the polycrystalline silicon regions 1 formed in the same layer is reduced by one. The above-described effect can be obtained by forming the thickness as 10 μm to 10 μm.

That is, for example, in the planar layout pattern of the polycrystalline silicon region shown in FIG.
The width a shown in (a) is set to 9 μm and the width b is set to 1 μm, and the polysilicon region 1 is laid out. That is,
The layout is performed so that a rectangular polycrystalline silicon region 1 having an interval of 9 μm between the polycrystalline silicon regions 1 can be formed in a 1 μm square. According to this layout, the polycrystalline silicon region 1 is used as the above-described carrier annihilation region, so that the carrier annihilation effect can be exerted on the entire surface of the semiconductor chip and the semiconductor wafer.

On the other hand, the ratio of the area occupied by the polycrystalline silicon region 1 to the entire semiconductor wafer is as shown in FIG. 1 (a), where the 1 μm ² polycrystalline silicon region is present in a 100 μm ² square. Therefore, the area occupies 1% of the whole area. Therefore, according to the present invention, the effect of increasing the on-voltage when the device is on can be reduced to a negligible extent.

Further, in the planar layout pattern of FIG. 1B, the width a in FIG.
Is set to 1 μm, and the layout pattern of the polycrystalline silicon region 1 is set to a lattice shape having a width of 1 μm and one side of 9 μm. At this time, the occupied area of the polycrystalline silicon region 1 in FIG. 1B is larger than the occupied area of the polycrystalline silicon region 1 in FIG. Accordingly, the carrier annihilation effect can be exerted on the entire surface of the semiconductor chip and the semiconductor wafer.

Further, in the polycrystalline silicon region 1 having a multilayer structure as shown in FIG. 2B, the first and second layers and the second and third layers are formed for the same reason as described above. The distance between the polycrystalline silicon regions 1 of the layer,
For example, the polycrystalline silicon region 1 in FIG.
The distance c between a, 1b and 1b, 1c is about 0.1 to
It can be set to 10 μm. Therefore, by using the polycrystalline silicon region 1 as a carrier annihilation region, the switching speed can be improved over the entire surface of the semiconductor chip and the semiconductor wafer.

That is, FIGS. 1A, 1B and 2
In the planar or cross-sectional layout pattern of the semiconductor device as shown in (a) and (b), the larger the area occupied by the chip in the polycrystalline silicon region 1, the greater the effect as a gettering layer and a carrier annihilation layer. However, if the area occupied by the polycrystalline silicon region 1 becomes too large, the on-voltage of the device will increase, so that it is necessary to optimize the layout of the polycrystalline silicon region 1.

As gettering, an intricate gettering method shown in FIG. 4 is generally known. The gettering method called this intrinsic gettering is a method of forming a crystal defect region 6 inside a semiconductor wafer, that is, on a semiconductor substrate 3 and in an amorphous defect region 7, and using the crystal defect region 6 as a gettering region. It is.

Conventionally, in a power device of a type in which a current flows in the vertical direction, as shown in FIG. 4, when a crystal defect region 6 exists, the resistance of this portion increases, and deterioration of the ON voltage of the device is reduced. For this reason, an intrinsic gettering method cannot be applied as a gettering method.

However, as shown in FIGS. 1 (a), 1 (b), 2 (a) and 2 (b), the polycrystalline silicon region is partially formed as in the semiconductor device of the present embodiment. By embedding in a single-crystal silicon region and using this as a gettering region, formation of a gettering region without deterioration of on-voltage can be realized as described above.

The number of the gettering regions is 10 ⁶ / cm ^{2 in} the layout of FIG. 1A with respect to the direction viewed from above the semiconductor wafer. Therefore, it is generally considered sufficient if the number of crystal defects in the gettering region of the intrinsic gettering is 10 ⁵ to 10 ⁶ / cm ^2. Therefore, the method according to the present embodiment provides sufficient gettering. The effect can be obtained. further,
In the layout of FIG. 1B, since the area occupied by the gettering region with respect to the entire semiconductor chip can be increased by selecting the width of the lattice pattern of the polycrystalline silicon region, a further gettering effect can be expected.

Also, in FIGS. 2A and 2B, the gettering effect increases as the number of the polycrystalline silicon regions 1 increases from the above-described point. Therefore, from FIG. FIG. 2B is more effective than FIG. On the other hand, as described above, since the process of forming the polycrystalline silicon region 1 is complicated, the process is also complicated as a whole as a semiconductor device, and the getter is also designed in consideration of the above-mentioned increase in on-voltage. It is necessary to optimize the layout of the ring region. That is,
In the three-dimensional layout of the gettering area,
The planar patterns shown in FIGS. 1A and 1B and FIG.
By combining the cross-sectional patterns shown in (a) and (b), the layout of the polycrystalline silicon region can be easily optimized.

On the other hand, an LSI represented by a CMOSFET
In FIG. 4, the intrinsic gettering shown in FIG. 4 is widely used. As described above, this intrinsic gettering causes a small crystal defect such as the crystal defect region 6 shown in FIG. 4 to occupy a large area in the amorphous defect region 7 in the silicon substrate. In this method, the silicon substrate itself has gettering ability.

That is, in the semiconductor wafer manufacturing process, the oxygen dissolved in the semiconductor wafer generates microcrystal defects such as oxygen precipitates and dislocations by annealing, and becomes a gettering center. Since the occurrence of microcrystal defects strongly depends on the oxygen concentration in the crystal, the distribution of precipitate nuclei such as carbon, and the thermal history, it is important to design and optimize the semiconductor wafer from the crystal growth to the element formation process.

In the process of forming a semiconductor element, the precipitation of oxygen proceeds by annealing. Therefore, by using the semiconductor wafer optimized as described above, the gettering ability can be reduced only by performing the element forming process. Can last up to.

That is, according to the intrinsic gettering technique, a small crystal defect is generated inside the silicon crystal and gettering is performed in the small defect crystal region. Therefore, the element active region must be kept free from defects. No.

However, as described above, as the miniaturization of the semiconductor device progresses, the temperature of the semiconductor device manufacturing process decreases, and a gettering region is required in a region closer to the element formation region, that is, in the active region. . However, in the intrinsic gettering method for forming a crystal defect inside a silicon substrate, it is impossible to accurately control the position of the crystal defect at, for example, about ± 1 μm or less.

As a countermeasure, a method in which a semiconductor wafer having a polycrystalline silicon region formed over the entire surface is bonded and polished to reduce the thickness is conceivable. In addition, there is a problem that this method cannot be applied to a power device in which a current flows vertically.

However, in the method of the present invention for improving the gettering method in a micro LSI, the distance between the semiconductor element formation region and the gettering region is S
The thickness can be controlled by the thickness of the single crystal silicon region formed by the PE method or the epitaxial growth. Therefore, according to the semiconductor device of the present invention, it is easy to control the distance between the semiconductor element formation region and the gettering region to this extent, and the gettering region is formed in a very close region that does not cause the characteristic deterioration of the device region. be able to.

As described above, according to the semiconductor device of the present invention, the switching speed of the semiconductor device can be improved by forming the carrier annihilation region having a structure without deterioration of the ON voltage inside the semiconductor substrate. it can. In addition, since a gettering region can be formed in the semiconductor substrate in the vicinity of the substrate surface (single-crystal silicon epitaxial layer surface) on which elements are formed, a stable gettering effect independent of a process can be obtained. The manufacturing process can be cooled,
It is possible to cope with miniaturization of elements.

Further, the present invention can be applied to a vertical power device of a type in which a current flows from the front surface to the back surface of a semiconductor substrate, and can implement intrinsic gettering without deterioration of on-voltage. .

(Embodiment 2) In Embodiment 1, a method for forming a polycrystalline silicon region common to each device, in other words, a method for forming a carrier annihilation region and a gettering region has been described. As described above, the polycrystalline silicon region can be applied to various semiconductor devices.

Embodiment 2 shows an example in which the present invention is applied to a thyristor.

FIG. 5B is a sectional view of a main part of a thyristor device according to the second embodiment. In the thyristor of the second embodiment, p ⁺
Polycrystalline silicon region 1 is embedded in n-type single-crystal silicon epitaxial layer 12 formed by the SPE method shown in FIG. 3 using n-type single-crystal silicon epitaxial layer 11 formed on type silicon substrate 3 as a seed portion. It is formed by. Also, this polycrystalline silicon region 1
Since the thyristor also functions as a gettering layer, the yield of the thyristor can be improved.

In the thyristor of the second embodiment, p
^A plurality of polycrystalline silicon regions 1 are formed on n-type single-crystal silicon epitaxial layer 11 formed on ⁺ -type silicon substrate 3. An n-type single-crystal silicon layer epitaxial layer 12a is formed so as to bury the plurality of polycrystalline silicon regions 1, and an n ⁺ -type diffusion layer is formed in the n-type single-crystal silicon layer epitaxial layer 12a. A cathode region 26 is formed.

A gate region 27 formed of a p ⁺ -type diffusion layer is formed with a cathode region 26 formed of the n ⁺ -type diffusion layer interposed therebetween.

A cathode electrode 14 formed of a single crystal silicon layer is provided on the cathode region 26, and a gate electrode 13 is provided on the gate region 27. A silicon electrode is provided between the cathode electrode 14 and the gate electrode 13. It is insulated by the oxide film 54. Further, an anode electrode 15 made of a single crystal silicon layer is formed on the back surface of the p ⁺ type silicon substrate 3 so as to face the cathode electrode 13.

FIG. 5A is a circuit diagram of the thyristor according to the second embodiment, and the operation of the thyristor according to the second embodiment will be described.

This thyristor can be described as a structure in which an electrostatic induction bipolar transistor Q1 and a pnp transistor Q2 are combined.

Here, the regions that operate as bipolar transistors are gate region 27, cathode region 26, and p ⁺ type silicon substrate 3.

Normally, when no bias is applied between the gate G and the cathode C, even if a voltage is applied to the anode A, the thyristor is turned off because both the bipolar transistor Q1 and the pnp transistor Q2 are off. In state.

Next, when a positive voltage is applied to the gate electrode G (13), holes are generated from the gate region 27 to the cathode region 2 (13).
From 6, electrons are injected into the channel region, and the hole and electron currents flow as gate currents. The holes and electrons are
It fills the channel region and flows into the cathode region 26, a state of so-called conductivity modulation. This state is a state where the cathode region 26 is filled with carriers, that is, equivalent to the ON state of the bipolar transistor Q1.

Next, a pnp transistor Q2 is turned on by applying a positive voltage to the anode A (15) side. By applying a positive voltage to the anode electrode A side, holes are injected from the gate region 27 and the p ⁺ type silicon substrate 3, and electrons are injected from the cathode region 26. This is because the electrons injected from the cathode electrode C (14) and the anode electrode A (1)
5 shows that the holes injected from 5) flow as an anode current.

In order to speed up turn-on in such a thyristor, the point is how many electrons are injected from the cathode by applying a voltage to the gate electrode G.

Next, a manufacturing process of the thyristor according to the second embodiment will be described with reference to FIGS. Also,
In the second embodiment, the polycrystalline silicon region is formed in one layer, and the same members as those in the first embodiment are denoted by the same reference numerals, and the same parts as those in the first embodiment are omitted. explain.

[0111] First, on the p ⁺ -type silicon substrate 3, about 10
00-1,150 ° C., using monosilane S _i H ₄ or a silicon chloride gas S _i2 Cl _2, the atmospheric pressure CVD method, growing single crystal silicon epitaxial layer at a thickness of 5 to 100 [mu] m. Then, for example, by implanting phosphorus P into the single crystal silicon epitaxial layer,
An n-type single crystal silicon epitaxial layer 11 is formed.
The thickness of the n-type single crystal silicon epitaxial layer 11 is
It can be set to match the desired pressure resistance.

Next, a polycrystalline silicon region 1 is formed on the n-type single-crystal silicon epitaxial layer 11 according to the first embodiment.
Are formed by the method described above. The planar layout pattern of this polycrystalline silicon region 1 is, for example, as shown in FIG.
Any of the patterns illustrated in FIGS. 6A and 6B can be applied (FIG. 6A).

Next, for example, at about 1000 to 1150 ° C.
A polycrystalline silicon layer is formed by a normal pressure CVD method using monosilane, disilane, silane chloride, or the like. Next, a single crystal silicon epitaxial layer is formed by an SPE method using the exposed surface of the n-type single crystal silicon epitaxial layer 11 as a seed portion, and, for example, phosphorus P is implanted to form n on the silicon oxide film 5. A single-crystal silicon epitaxial layer 12a is formed.

At this time, as shown in FIG. 6 (b), the n-type single-crystal silicon epitaxial layer 12a is formed thin, and the n-type single-crystal silicon epitaxial layer 12a is formed thereon by atmospheric pressure CVD. There is a method of forming the layer 12b and a method of forming the n-type single-crystal silicon epitaxial layer 12a by the SPE method as shown in FIG. 6 (c). Either method can be used. FIG. 6 in Embodiment 2 shows an example in which the latter method is applied.

Then, for example, by diffusing boron B into the n-type single crystal silicon epitaxial layer 12b, a p ⁺ -type diffusion layer is formed to form the gate region 27. By diffusing into the silicon epitaxial layer 12b, an n ⁺ -type diffusion layer is formed to form the cathode region 26. Further, by forming a single crystal silicon epitaxial layer by a general electrode forming method, the gate electrode 13 and the cathode electrode 1 are formed.
4. An anode electrode 15 is formed to form a basic thyristor structure (FIG. 6D).

As described above, in the thyristor manufacturing process of the present invention, a carrier annihilation region is easily formed in a semiconductor substrate in a structure without deterioration of on-voltage by utilizing the characteristics of the SPE method. Thus, the switching speed of the thyristor can be improved.

According to the method of the second embodiment, the gettering layer can be formed in the vicinity of the surface of the semiconductor substrate (the surface of the n-type single-crystal silicon epitaxial layer). A thyristor that can obtain an effect can be realized. Therefore, according to the thyristor of the present invention, a low-temperature process can be adopted, and it is possible to cope with miniaturization of elements.

(Embodiment 3) Next, the present invention will be described with reference to an IGBT.
(Insulated Gate BipolarTr
An example applied to an ansistor will be described in a third embodiment.

FIG. 7A is a circuit diagram of an IGBT of the present invention.

The IGBT has an M as shown in FIG.
The OS transistor M1 is an input transistor, and pn
This is a complementary-connection Darlington (inverted Darlington) bipolar / MOS composite transistor using the p-type bipolar transistor Q1 as an output transistor.

FIG. 7B is a sectional view of a main part of an IGBT device according to the third embodiment. In the IGBT of the third embodiment, similarly to the thyristor of the second embodiment, in order to improve the switching speed, the SPE is formed by using the n-type single-crystal silicon epitaxial layer 11 formed on the p ⁺ -type silicon substrate 3 as a seed portion. It is formed by burying a polycrystalline silicon region 1 in an n-type single crystal silicon epitaxial layer 12a formed by a method. Further, since the polycrystalline silicon region 1 also functions as a gettering layer, the yield of IGBT can be improved.

In the IGBT according to the third embodiment, a plurality of polycrystalline silicon regions 1 are formed on n-type single-crystal silicon epitaxial layer 11 formed on p ⁺ -type silicon substrate 3 (collector). I have. Then, the plurality of polycrystalline silicon regions 1 are embedded so that n
Formed single-crystal silicon epitaxial layer 12a is formed. A p-type body layer 29 (emitter) is provided near the surface of the n-type single crystal silicon epitaxial layer 12a.
Is formed, and an n ⁺ -type diffusion layer is formed therein as the source region 22.

Then, a silicon oxide film 55 is formed on the source region 22, and the silicon oxide film 5
A polycrystalline silicon gate electrode 21 is provided on 5, and an anode electrode 15 is formed on the back surface of the p ⁺ -type silicon substrate 3 so as to face the polycrystalline silicon gate electrode 21.

Next, the manufacturing process of the IGBT according to the third embodiment will be described with reference to FIGS. 8 (a) to 8 (c) and FIGS.
This will be described with reference to FIG. In the third embodiment, the polycrystalline silicon region 1 is formed in one layer, and the same members as those in the first and second embodiments are denoted by the same reference numerals, and are the same as those in the first and second embodiments. The parts that are not described will be omitted.

First, on a p ⁺ type silicon substrate 3, 100
0-1,150 ° C., using monosilane S _i H ₄ or a silicon chloride gas S _i2 Cl _2, the atmospheric pressure CVD method, a single crystal silicon epitaxial layer is grown at a thickness of 5 to 100 [mu] m. By implanting, for example, phosphorus P into the single crystal silicon epitaxial layer, n
A single-crystal silicon epitaxial layer 11 is formed. The thickness of the n-type single crystal silicon epitaxial layer 11 is
It can be set to match the desired pressure resistance.

Next, a plurality of polycrystalline silicon regions 1 are formed on the n-type single crystal silicon epitaxial layer 11 by the method described in the first embodiment. The planar layout pattern of this polycrystalline silicon region 1 is shown in FIG.
Any of the patterns illustrated in (b) can be applied. (FIG. 8A) Next, for example, at about 1000 to 1150 ° C., monosilane,
Atmospheric pressure CVD using disilane or chloride silane
A polycrystalline silicon layer is formed by a method. Then, SPE
The n-type single crystal silicon epitaxial layer 1
A single crystal silicon epitaxial layer is formed using the exposed surface of 1 as a seed portion, and, for example, phosphorus P is implanted to form an n-type single crystal silicon epitaxial layer 12a on the silicon oxide film 5.

At this time, as shown in FIG. 8B, the n-type single-crystal silicon epitaxial layer 12a is formed thin, and the n-type single-crystal silicon epitaxial layer 12a is formed thereon by the atmospheric pressure CVD method. There is a method of forming the layer 12b and a method of forming the n-type single-crystal silicon epitaxial layer 12a by the SPE method as shown in FIG. 8C, and any of these methods can be used. 8 and 9 in the third embodiment show examples in which the latter method is applied.

Next, for example, boron B is diffused on the surface of the n-type single crystal silicon epitaxial layer 12a to form a p-type body layer 29, and phosphorus P is diffused to form an n ⁺ -type diffusion layer. The layer forms the source region 22. Then, a gate oxide film 55 is formed on the surface of the n-type single crystal silicon epitaxial layer 12a.
(FIG. 9 (d)) Then, a polycrystalline silicon layer serving as a gate electrode is formed, and the polycrystalline silicon layer is processed by photolithography and RIE etching.
A polycrystalline silicon gate electrode 21 is formed and a basic IG
A BT structure is formed (FIG. 9E).

As described above, the manufacturing process of the IGBT of the present invention can be easily performed by utilizing the characteristics of the SPE method.
In the semiconductor substrate, a carrier annihilation region is formed in a structure that does not involve deterioration of the on-voltage, so that the switching speed of the IGBT can be improved.

Also, in particular, the distance between the semiconductor element formation region and the gettering region can be controlled by the thickness of the single crystal silicon epitaxial layer by the SPE method. I to apply current to
In the GBT, a large gettering effect can be obtained. That is, since the gettering layer can be formed near the surface of the semiconductor substrate (the surface of the n-type single crystal silicon epitaxial layer), an IGBT which can obtain a stable gettering effect independent of the process can be realized. . Therefore, according to the IGBT of the present invention, a low-temperature process can be adopted, and it is possible to cope with miniaturization of elements.

(Embodiment 4) An example in which the present invention is applied to an IGBT is described in Embodiment 3. However, as described above, in a semiconductor device, the element size of a semiconductor device has been advanced, and therefore, In addition, there has been an increasing need to miniaturize elements by applying a trench gate.

An example in which the present invention is applied to a trench gate type IGBT will be described in a fourth embodiment.

FIG. 10 shows a trench gate type IGB of the present invention.
1 shows a cross-sectional view of a main part of a device T. FIG.

In the trench IGBT of the present invention,
As with the thyristors and IGBTs of the second and third embodiments,
In order to improve the switching speed, the n-type single crystal silicon epitaxial layer 12a formed by the SPE method
It is formed by embedding the polycrystalline silicon region 1. Further, in the IGBT of the present invention, since the polycrystalline silicon region 1 can also function as a gettering layer, the yield of the trench gate IGBT can be improved.

In the trench gate type IGBT of the fourth embodiment, the n-type single crystal silicon epitaxial layer 11 formed on the p ⁺ type silicon substrate 3 is
A plurality of polycrystalline silicon regions 1 are formed. And
An n-type single crystal silicon epitaxial layer 12a is formed so as to bury the plurality of polycrystalline silicon regions 1.

A p-type body layer 29 is formed near the surface of the n-type single crystal silicon epitaxial layer 12a, and a trench 30 is formed therein. Then, a silicon oxide film 56 is formed on the entire surface of the trench 30, and polycrystalline silicon is buried and formed on the silicon oxide film 56, so that the polycrystalline silicon gate electrode 21 is formed. .
An n ⁺ -type diffusion layer is formed so as to surround the polycrystalline silicon region 21, and functions as a source region 22. Further, an anode electrode 15 is formed on the back surface of the p ⁺ type silicon substrate 3 so as to face the polycrystalline silicon gate electrode 21.

The manufacturing process of the trench gate type IGBT will be described below. In the fourth embodiment,
It is assumed that the polycrystalline silicon region 1 is formed in one layer.

N-type single crystal silicon epitaxial layer 12
Steps up to the process of forming a are the same as those of the third embodiment
Since it is the same as the GBT, detailed description is omitted, but after the formation process of the polysilicon region 1 (FIG. 8A), an n-type single-crystal silicon epitaxial layer 12a is formed on the polysilicon region 1 by the SPE method. Formed and grown to a predetermined thickness. At this time, the n-type single crystal silicon epitaxial layer 12a is formed thin by the SPE method,
It is also possible to form the n-type single-crystal silicon epitaxial layer 12b with a thickness by the VD method. (FIGS. 8B and 8C) And, although not particularly shown, for example, on the surface of the n-type single crystal silicon epitaxial layer 12a,
By diffusing boron B, a p-type body layer 29 is formed. The trenches 3 are formed in the p-type body layer 29 by photolithography and etching such as RIE.
0 is formed.

Next, 950 is applied to the trench 30.
By performing oxidation in an atmosphere of ~ 1150 ° C,
A silicon oxide film 56 is formed on the trench 30.
Then, phosphorus P is diffused on the p-type body layer 29 to form an n ⁺ -type diffusion layer, and the source region 22 is formed.

Then, polycrystalline silicon is formed on the silicon oxide film 56 in the trench 30 by normal pressure CVD or the like so as to fill the trench 30, and the polycrystalline silicon is formed by photolithography and etching such as RIE. By processing, the polycrystalline silicon gate electrode 21 can be formed, and a basic trench gate type IGBT structure is formed.

Also in this example, the polycrystalline silicon region 1 of the present invention functions as a carrier annihilation layer, and can achieve an improvement in switching speed without an increase in on-voltage.
Further, the carrier annihilation layer also functions as a gettering region, and the yield of the trench gate type IGBT can be expected to be improved.

In the manufacturing process of the trench type IGBT of the present invention, the characteristic of the SPE method is used to easily form a carrier annihilation region in the semiconductor substrate in a structure without deterioration of on-voltage, The switching speed of the IGBT can be improved.

In particular, the distance between the semiconductor element formation region and the gettering region can be controlled by the thickness of the single crystal silicon epitaxial layer by the SPE method. I to apply current to
In the GBT, a large gettering effect can be obtained. That is, a gettering layer is formed near the surface of the semiconductor substrate (near the surface of the p-type body layer), and a stable gettering effect independent of a process can be obtained. Therefore, according to the trench gate type IGBT of the present invention, a low temperature process can be adopted, and it is possible to cope with miniaturization of elements. Further, in the fourth embodiment, by adopting the trench gate structure, a device which can cope with further miniaturization of elements can be realized, which can greatly contribute to miniaturization of a semiconductor device.

(Embodiment 5) Next, the present invention relates to a CMOS.
A fifth embodiment applied to an FET will be described.

FIG. 11A shows an inverter circuit using the CMOSFET of the present invention.

The inverter circuit of the present invention has a pMOSFE
It has a TQ10 and an nMOSFET Q11. And
The pMOSFET Q10 and the nMOSFET Q11
Are connected to form a common input gate. The pMOSFET Q10 and the nMOS
The drains of the FET Q11 are connected to each other, and the drain serves as a common output gate. And the p
The power supply voltage Vdd is applied to the source of the MOSFET Q10, and the ground voltage is applied to the source of the nMOSFET Q11.

FIG. 11B shows a CMOSFET of the present invention.
2 shows a cross-sectional view of a main part of the device of FIG. CMO of Embodiment 5
In the SFET, the surface of the p ⁺ -type silicon substrate 3, that is, the p-type single-crystal silicon epitaxial layer 33a formed by the SPE method shown in FIG. It is formed by burying the crystalline silicon region 1. Then, similarly to the second to fourth embodiments, since the polycrystalline silicon region 1 can also function as a gettering region, the yield of the CMOSFET can be improved.

The CMOSFET of the fifth embodiment
In the above, the surface of the p ⁺ type silicon substrate 3, that is,
A plurality of polycrystalline silicon regions 1 are formed on p-type single crystal silicon epitaxial layer 28. Then, a p-type single crystal silicon epitaxial layer 33a is formed so as to bury the plurality of polycrystalline silicon regions 1.

Further, an N well 23 and a P well 20 are formed in the p type single crystal silicon epitaxial layer 33a, and a p ⁺ type diffusion layer 34a functioning as a source region or a drain region is formed in the N well 23. , 34
b is formed in the P well 20, and n ⁺ type diffusion layers 34c, 34c functioning as a source region or a drain region.
4d is formed.

Then, the P well 20 and the N well 2
Since the LOCOS oxide film 35 is entirely formed on the surface of the LOCOS oxide film 35, the thin silicon, which is a part of the LOCOS oxide film 35, is formed on the p ⁺ -type diffusion layers 34a and 34b and the n ⁺ -type Oxide films are formed respectively, and gate electrodes 13n and 13p are formed on the silicon oxide films on the P well 20 side and the N well 23 side, respectively.

Each of these gate electrodes has an nMO
Gate electrode 13n in SFET and pMOSFET
13p is the gate electrode. Then, an interlayer insulating film 24 is formed on the gate electrodes 13n and 13p, and the metal wiring 25 and the gate electrodes 13n and 13b are formed.
Are insulated from each other. The metal wiring 25
Is formed partially through the interlayer insulating film 24, and the metal wiring 25 is formed in the n ⁺ -type diffusion layer 13.
a, 13b and p ⁺ type diffusion layers 13c, 13d. As a result, the source electrode and the drain electrode of the MOSFET can be drawn out, and the pMOS
The current flowing through the FET and the nMOSFET can be taken out on the metal wiring 25.

Next, a manufacturing process of the CMOSFET of the fifth embodiment will be described with reference to FIGS. In the fifth embodiment, the polycrystalline silicon region 1, that is, the gettering layer is formed as one layer, and the same members as those in the first to fourth embodiments are denoted by the same reference numerals. The description of the same parts as those in Nos. 1 to 4 will be omitted.

First, a plurality of polycrystalline silicon regions 1 are formed on p-type silicon substrate 3 (p-type single crystal silicon epitaxial layer 28) by the method described in the first embodiment. As the planar layout pattern of the polycrystalline silicon region 1, any of the patterns exemplified in FIGS. 1A and 1B can be applied (FIG. 12A).

Next, for example, at about 1000 to 1150 ° C.
A polycrystalline silicon layer is formed by atmospheric pressure CVD using monosilane, disilane, silane chloride, or the like. Next, a single-crystal silicon epitaxial layer is formed by SPE using the exposed portion of the p-type single-crystal silicon epitaxial layer 28 on the surface of the p-type silicon substrate 3 as a seed portion. On the silicon oxide film 5, a p-type single crystal silicon epitaxial layer 33a is formed.

At this time, as shown in FIG. 12B, the p-type single-crystal silicon epitaxial layer 28 is formed thin, and a p-type single-crystal silicon epitaxial layer having a film thickness is formed thereon by a normal pressure CVD method. There is a method of forming the layer 33b and a method of forming the p-type single-crystal silicon epitaxial layer 33a by the SPE method as shown in FIG. 12 (c). Either method can be used. FIG. 12 in Embodiment 5 shows an example in which the latter method is applied.

Next, an LOCOS oxide film 35 is formed on the surface of the p-type single-crystal silicon epitaxial layer 33a in a pattern as shown in the figure, and, for example, phosphorus P is diffused to form an N well 23. Then, a P well 20 is formed by diffusing boron B. Then, the nMOSFET and the pMOSFE are formed by a general method.
Gate electrodes 13n and 13p and source / drain regions 34a to 34d at T are formed in the n-well 23 and the p-well 20. Further, the gate electrode 13n,
By forming the interlayer insulating film 24 and the metal wiring 25 on the 13p by a general method, the nMOSFET, the pMO
By forming SFET, basic CMOSFET
A structure is formed. (FIG. 12D) As described above, the manufacturing process of the CMOSFET of the present invention can be performed by using the characteristics of the SPE method and performing the SPE method using the semiconductor substrate itself as a seed portion. Can be easily implemented without an increase. Further, in the CMOSFET of the present invention, a gettering layer can be formed in the vicinity of the surface of the semiconductor substrate without depending on a process, so that a stable gettering effect can be obtained. Therefore, according to the CMOSFET of the present invention, a low-temperature process can be adopted, and it is possible to cope with miniaturization of elements. Further, by adopting a trench gate structure as a gate electrode, a device which can further cope with miniaturization of elements can be realized, which can greatly contribute to miniaturization of a semiconductor device.

Further, in this example, the polycrystalline silicon region functions as a gettering region, and an improvement in the yield of the CMOSFET can be expected.

Although the first to fifth embodiments have been described above, an example of a device having one polycrystalline silicon region has been described as a layout pattern of the polycrystalline silicon region. Layering is also possible as described above. In this case, the processes (a) to (d) shown in FIG. 3 may be repeated as many times as the number of the polycrystalline silicon regions.

[0159]

[Brief description of the drawings]

FIG. 1 is a diagram showing a planar layout pattern of a semiconductor device of the present invention.

FIG. 2 is a schematic diagram of a main part showing a cross-sectional structure of a semiconductor device of the present invention.

FIG. 3 is a view illustrating a process of forming a polycrystalline silicon region in the semiconductor device of the present invention.

FIG. 4 is a diagram for explaining intrinsic gettering;

FIG. 5A is a circuit diagram of a thyristor according to a second embodiment;
It is a principal part schematic diagram (b) which shows the cross-section of a thyristor.

FIG. 6 is a diagram illustrating a manufacturing process of the thyristor according to the second embodiment.

FIG. 7 is a circuit diagram (b) of the IGBT according to the third embodiment, and FIG.
It is a principal part schematic diagram (b) which shows the cross-section of GBT.

FIG. 8 is a first diagram showing a manufacturing process of the IGBT of the third embodiment.

FIG. 9 is a second diagram showing a manufacturing process of the IGBT of the third embodiment.

FIG. 10 is a main part schematic diagram showing a cross-sectional structure of a trench gate IGBT according to a fourth embodiment.

FIG. 11A is a circuit diagram of an inverter circuit to which a CMOSFET according to a fifth embodiment is applied, and FIG.
FIG. 3B is a schematic diagram (b) of a main part showing a cross-sectional structure of the SFET.

FIG. 12 is a diagram illustrating a manufacturing process of the CMOSFET according to the fifth embodiment;

[Explanation of symbols]

Reference Signs List 1 polycrystalline silicon region 2 single crystal silicon region 3 p ⁺ type silicon substrate 4, 40 polycrystalline silicon layer 5, 50, 54, 55, 56 silicon oxide film 6 crystal defect region 7 crystal defect-free region 11 n-type single crystal silicon Epitaxial layer 12a N-type single crystal silicon epitaxial layer formed by SPE method 12b N-type single crystal silicon epitaxial formed by normal pressure CVD method 13 Gate electrode 14 Cathode electrode 15 Anode electrode 20 PWELL 21 Polycrystalline silicon gate electrode 22 Source region 23 NWELL 24 interlayer insulating film 25 a metal interconnection 26 cathode region 27 gate region 28 p ⁺ -type single crystal silicon epitaxial layer 29 p-type body layer (emitter) 30 trench 31a, b seed crystal part (seed portion) 32 amorphous silicon 33 n-type is formed by p-type single crystal silicon epitaxial layer 33b atmospheric pressure CVD method was formed by SPE method single crystal silicon epitaxial layer 34a, b source, drain layer 35 LOCOS oxide film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 H01L 29/78 658H 21/336

Claims (1)

[Claims] 1. A polycrystalline silicon layer partially present in a predetermined pattern on a first monocrystalline silicon layer formed on a semiconductor substrate and a second polycrystalline silicon layer formed by embedding the polycrystalline silicon layer. A semiconductor device including a single crystal silicon layer.