JPH1027107A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To start an interruption without increasing the load on software when one specific event reaches a specific frequency by providing hardware which can automatically count the frequency of interruption occurrence in the information processor. SOLUTION: An interruption detecting circuit monitors signals inputted to and outputted from an I/O port part and signals on an internal bus to detect abnormality and generates interruption request signals IRQ1-1RQn corresponding to the abnormality. A counter counts the interruption request signals corresponding to interruptions set by an interruption setting register 72 and a comparator 76 compares its counted value with a value set in a frequency register 75. When it is decided that interruption requests reach the specific frequency, the comparator 76 outputs an interruption request signal IRQc to a priority decision and vector generating circuit 71. Consequently, even if the same interruption is continuouslly generated, a memory can be prevented from overflowing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control technique in an information processing apparatus, and more particularly to a technique effective for use in a single-chip microcomputer (hereinafter, referred to as a single-chip microcomputer) integrated into a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, single-chip microcomputers include:
An interrupt function is provided for interrupting the program being executed when a specific event occurs during the execution of the program.
By the way, the interrupt function in the conventional single-chip microcomputer interrupts the execution of the program immediately when a certain specific event occurs.

[0003]

In a system using a microcomputer, the execution of a program is not interrupted immediately when a certain event occurs, but the program is executed when a certain event occurs a predetermined number of times. You may want to interrupt the execution of. More specifically, for example, there is a case where it is desired to automatically perform protection for a case where interrupts due to system runaway occur consecutively and prevent overflow of a memory (RAM) used as a stack area or the like in interrupt processing.

However, conventional single-chip microcomputers do not have hardware for automatically counting the number of times an interrupt has occurred. Therefore, if it is desired to generate an interrupt when a certain event occurs a predetermined number of times,
I had to deal with software. That is, a specific general-purpose register in the single-chip microcomputer is used as a counter, and when a specific interrupt occurs, the register is counted up, and when the counter reaches a predetermined value, the execution of the main program is interrupted. A program that branches to a subroutine or executes an interrupt processing routine prepared in advance has been required.

An object of the present invention is to provide an interrupt control technique capable of interrupting when a specific event occurs a predetermined number of times without increasing the load on software. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The outline of a typical invention among the inventions disclosed in the present application is as follows. In other words, by providing hardware capable of automatically counting the number of interrupt occurrences inside the information processing apparatus, an interrupt can be generated when a specific event occurs a predetermined number of times without increasing the load on software. It is like that.

More specifically, an interrupt designating means for designating an interrupt request signal whose number of occurrences is to be monitored, and an interrupt counting means for counting the interrupt request signal designated by the interrupt designating means are provided inside the single-chip microcomputer. Interrupt number setting means for designating how many times an interrupt request signal is to be generated, and determining whether or not the count value of the interrupt counting means has reached the value set in the interrupt number setting means And a code that can specify the type of interrupt whose occurrence is to be monitored or the priority order and other interrupt requests can be specified in the interrupt designating means in advance in the main program. By setting the number of occurrences, an interruption can be made when a specific event occurs a predetermined number of times.

[0008]

FIG. 1 shows an embodiment of a single-chip microcomputer to which the present invention is applied. In FIG. 1, reference numeral 1 denotes a CPU (central processing unit) that executes processing according to a program and controls the entire chip, and 2 denotes a ROM (read-only) that stores an operation program of the CPU 1 and fixed data.
3) RAM for providing a work area for CPU 1
(Random access memory), 4 an I / O port for inputting and outputting signals to and from an external device, 5 a timer circuit for counting time and generating a timer interrupt,
6 is a serial communication interface circuit for converting data to be transmitted into serial data or converting received data into parallel data, and 7 is an interrupt control circuit for notifying the CPU 1 of the occurrence of an interrupt based on an interrupt request signal. is there. CPU1, ROM2, RAM3, I
The / O port unit 4, timer circuit 5, serial communication interface circuit 6, and interrupt control circuit 7 are connected to an internal bus 8
Are connected to each other so that data can be transmitted and received.

The single-chip microcomputer of this embodiment monitors a signal input and output from the I / O port unit 4 and a signal on the internal bus 8 to detect an abnormality and to execute an interrupt corresponding to the abnormality. An interrupt detection circuit 9 for generating request signals IRQ1 to IRQn is provided. Interrupt request signals IRQ1 to IRQn formed by the interrupt detection circuit 9
Is supplied to the interrupt control circuit 7, the interrupt control circuit 7 determines the order of the interrupts, notifies the CPU 1 of the occurrence of the interrupt, and generates and outputs a vector address VAD corresponding to the interrupt. Although not particularly limited, the single-chip microcomputer of this embodiment is provided with interrupt input terminals IR1 and IR2 for receiving an interrupt request signal from an external device. Interrupt input terminal IR
One of IR1 and IR2 is used to input an interrupt request signal NMI that cannot be masked.

When CPU 1 receives a signal notifying the occurrence of an interrupt from interrupt control circuit 7, CPU 1 interrupts the program being executed and branches to a subroutine based on vector address VAD, or enters an interrupt processing routine corresponding to the interrupt. Jump and execute the routine. In the interrupt processing, the program that has been executed is interrupted, and the data held in the general-purpose register is saved to an external storage device via the internal RAM 3 or the I / O port unit 4 at that time. Execute the process. After the end of the interrupt processing, the saved data is returned to the original register, and the execution of the original program is resumed from the interrupted instruction.

FIG. 2 shows an embodiment of the interrupt control circuit 7. The interrupt control circuit 7 of this embodiment is
Interrupt request signals IRQ1 to IRQ1 from the interrupt detection circuit 9
In response to the interrupt request signals IRQ0 and NMI from the interrupt input terminals IR1 and IR2 and the interrupt request signals IRQ0 and NMI, the priority is determined, and a signal RQ for notifying the CPU 1 of the occurrence of an interrupt is output from the highest priority and an interrupt is generated. , C
Masking of an interrupt is performed in accordance with the state of a mask bit or the like of a control register in the PU1, and a vector address VAD corresponding to the type or priority of an interrupt request signal is provided.
And an interrupt setting register 72 for setting a code or the like for designating an interrupt request signal whose number of occurrences is to be monitored, and an interrupt set by the interrupt setting register 72. A counter 73 for counting an interrupt request signal, and an interrupt request signal corresponding to, for example, a "1" bit of the interrupt setting register 72 among the interrupt request signals NMI and IRQ0 to IRQn are selectively sent to the counter 73. A selector 74 to be supplied, an interrupt count register 75 for specifying how many times the interrupt request signal is generated, and an interrupt count register 75 for comparing the count value of the counter 73 with the value set in the interrupt count register 75 And a comparator 76 for determining whether or not the number of interrupt requests has reached a predetermined number.

When the comparator 76 determines that the number of interrupt requests has reached a predetermined number, the comparator 76 outputs an interrupt request signal IRQc to the priority determination & vector generation circuit 71. Further, although not particularly limited, the interrupt request signal N
MI, IRQ0 to IRQn;
Interrupt request signals IRQ1 to IRQn from
Gate circuits G1 to Gn are provided to prevent the interrupt request signal set in the interrupt setting register 72 from being transmitted to the priority determination & vector generation circuit 71. The interrupt setting register 72 and the interrupt count register 75 are configured so that the CPU 1 can set a code specifying an interrupt request signal and the interrupt count via the internal bus 8 respectively.

In the above embodiment, the internal interrupt request signal is interrupted only when it is generated a predetermined number of times. As a result, even if the same interrupt occurs continuously, it is possible to prevent the memory used in the interrupt processing from overflowing. On the other hand, the external interrupt request signals NMI and IRQ0 are input to the priority determination & vector generation circuit 71 without passing through the gate circuit. An interrupt will also occur when it occurs. Therefore, when the same interrupt occurs a predetermined number of times, it is possible to execute another interrupt process different from the one before. Thus, for example, when the interrupt request signal NMI is continuously input from the outside due to runaway of the system, the system can be protected by executing processing such as forcibly stopping the system when the predetermined number of times is reached.

In the above embodiment, only the interrupt request signals IRQ1 to IRQn detected by the interrupt detection circuit 9 are set when the number of interrupt occurrences reaches a predetermined number.
Although an interrupt can be issued to U1, the interrupt request signals IRQ0 and NMI from the interrupt input terminals IR1 and IR2 are also interrupted to the CPU 1 when the number of interrupt occurrences reaches a predetermined number. Can be configured to be applied. Further, a gate circuit for transmitting or interrupting the interrupt request signal to the priority determination & vector generation circuit 71 is connected to the interrupt request signals IRQ1 to IRQ.
n, or the gate circuits G1 to G1.
A separate Gn control register may be provided so that it is possible to arbitrarily set whether an interrupt is generated when a predetermined number of occurrences occur, or whether an interruption is performed each time and an interruption occurs when a predetermined number of occurrences occur. Good.

As described above, in the above-described embodiment, the interrupt designating means (register 72 and selector 74) for designating the interrupt request signal whose number of occurrences is to be monitored is specified in the single-chip microcomputer. Interrupt counting means (counter 73) for counting the number of interrupt request signals generated, interrupt number setting means (register 75) for specifying how many times the interrupt request signal is generated, and a total of the interrupt counting means. A comparison means (comparator 76) for determining whether or not the numerical value has reached the value set in the interrupt number setting means is provided, and an interrupt request signal whose occurrence number should be monitored by the interrupt designating means can be specified in advance by the main program. Code and the number of occurrences to be interrupted are set in the interrupt count setting means. Without increasing the wear of the load, there is an effect that a particular event will be able to interrupt when a predetermined number of occurrences.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say. For example, in the above embodiment, the selector 74 and the gate circuit G are directly controlled by the code set in the interrupt setting register 72.
1 to Gn are controlled, but a decoder may be provided in the interrupt setting register 72 so that the selector 74 and the gate circuits G1 to Gn are controlled by a signal obtained by decoding a set value. . Instead of providing the gate circuits G1 to Gn, a circuit having an equivalent function may be provided in the priority determination & vector generation circuit 71.

In the above description, the case where the invention made by the present inventor is mainly applied to interrupt control in a single-chip microcomputer, which is the background of application, has been described. However, the present invention is not limited to this. It can be widely used in microcomputer systems generally having an interrupt function.

[0018]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in an information processing apparatus having an interrupt function, an interrupt can be generated when a specific event occurs a predetermined number of times without increasing the load on software.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a single-chip microcomputer to which the present invention is applied;

FIG. 2 is a block diagram showing one embodiment of an interrupt control circuit.

[Explanation of symbols]

 Reference Signs List 1 CPU (central processing unit) 2 ROM (read only memory) 3 RAM (random access memory) 4 I / O port section 5 timer circuit 6 serial communication interface circuit 7 interrupt control circuit 8 internal bus 9 interrupt detection Circuit 71 Priority judgment & vector generation circuit 72 Interrupt setting register 73 Counter 74 Selector 75 Interrupt count register 76 Comparator IRQ Interrupt request signal VAD Vector address

Claims (4)

[Claims] An interrupt designating means for designating an interrupt request signal to be monitored, an interrupt counting means for counting the interrupt request signal designated by the interrupt designating means, and an interrupt request signal when the interrupt request signal is generated. Interrupt number setting means for specifying whether to apply or not, and comparing means for determining whether or not the count value of the interrupt counting means has reached the value set in the interrupt number setting means, wherein the comparing means An information processing apparatus configured to execute a process corresponding to the interrupt request when the determination is made. 2. The method according to claim 1, wherein the interrupt specifying means sets an interrupt setting register for setting a code capable of specifying an interrupt request signal whose occurrence count is to be monitored, and an interrupt request signal corresponding to the interrupt setting signal based on the set value of the interrupt setting register. 2. The information processing apparatus according to claim 1, further comprising a selector for selectively supplying the interrupt counting means. 3. The information processing apparatus according to claim 1, further comprising gate means capable of transmitting / interrupting an interrupt request signal specified by said interrupt specifying means. 4. A central processing unit for executing processing according to a program, an internal memory storing a program and the like, and an interrupt control circuit for notifying the central processing unit of the occurrence of an interrupt based on an interrupt request signal. And 1
A single-chip microcomputer formed on one semiconductor chip, wherein the interrupt control circuit counts an interrupt request signal specified by the interrupt specifying means for specifying an interrupt request signal to be monitored; Interrupt counting means;
Interrupt count setting means for designating how many times an interrupt request signal is to be generated when an interrupt is requested, and determining whether the count value of the interrupt counting means has reached the value set in the interrupt count setting means A single-chip microcomputer comprising: comparing means; and, when the comparing means determines a match, notifying the central processing unit of the occurrence of an interrupt.