JPH10270858A - Multilayered wiring board and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method to manufacture a multilayered wiring board with high connection reliability and solder heat resistance. SOLUTION: This multilayered wiring board is provided with a through hole 4 connected electrically with a conductor circuit and a cavity 5 for housing a semiconductor chip 6. The multilayered wiring board having an insulation adhesive layer whose storage elastic modulas 15 within a range of 1000-5000 MPa at 30 deg.C in stage B and is 30 MPa or higher at 300 deg.C in C stage and whose glass transition temperature is 180 deg.C or higher, a circuit board which is hollowed in advance to form a cavity for housing a semiconductor chip and where a conductor circuit is formed on an insulation layer, the insulation adhesive layer 1, and the circuit board are piled up, and heated and pressurized for forming a multilayer, and further a hole is made to form the through hole 4 and a conductor is formed on the inner wall of the hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board, and more particularly to a multilayer wiring board used for a semiconductor chip package and a method of manufacturing the same.

[0002]

2. Description of the Related Art A multilayer wiring board generally includes an insulating adhesive layer, a power supply layer, a ground layer, a circuit conductor formed on the surface thereof, an inner circuit formed therein, and an electric circuit of each layer. It consists of a through hole or a non-through hole for connection, and a solder resist for insulating the circuit on the surface.

There are many methods of manufacturing such multilayer wiring boards. For example, an internal circuit board serving as an internal circuit, a power supply layer and a ground layer is manufactured by removing unnecessary portions of copper foil of a copper-clad laminate. After that, prepreg and copper foil are layered on top of each other, and heated and pressed for lamination and integration, holes are drilled in the necessary places for connection, and the inner wall is metallized by electroless plating etc. In general, a method is known in which an unnecessary portion is removed by etching, and a solder resist is applied and dried.

In addition, the inner circuit boards of the respective layers are separately prepared, aligned using guide pins, and integrally laminated and formed, and then formed with through holes, surface circuits, and solder resists. Is also generally known.

As for a package for a semiconductor chip, a leadless chip carrier in which a terminal portion connected to a semiconductor chip is formed on an outer part of the package so as to extend from the inside is disclosed in Japanese Patent Application Laid-Open No. 59-158579.
No., published in Japanese Unexamined Patent Publication No. Japanese Patent Publication No. 58-11100 discloses a pin grid array having a plurality of terminal pins for mounting a package and connecting to through holes of another wiring board and a method of manufacturing the same. Further, instead of the pins of the pin grid array, a ball grid array in which solder balls are fused to the lands and electrical connection is made by soldering is disclosed in
No. 11100 discloses this. Japanese Patent Publication No. 58-28828 discloses a method of forming a terminal automation part and forming a tape automation carrier insulated with a tape-shaped insulating film.

[0006] Such semiconductor chip packages (hereinafter referred to as chip carriers) often use ceramics as an insulating material, and these chip carriers are electrically connected to the terminals of the semiconductor chip by wire bonding. The organic insulating material has been used as a sealing material for protecting the semiconductor chip and the connection portion from the environment after mounting the semiconductor chip on these chip carriers.

Further, in recent years, ceramic chip carriers are not economical due to the increased number of steps for firing, so that a chip carrier is manufactured by a so-called multilayer wiring board technique using an organic insulating material. Is being developed. For example, a method of manufacturing a package of a pin grid array using an organic insulating material is disclosed in
-25023.

[0008]

In recent years, with respect to multilayer wiring boards as well, downsizing and multifunctionality of electronic devices have been demanded, and higher density and thinner wiring have been required. Therefore, the thickness of the insulating material used for the insulating adhesive layer between the inner layer circuits has also been required to be reduced.In the case of a prepreg using a conventional glass woven fabric or non-woven fabric, the thickness of the glass woven fabric or non-woven fabric is not sufficient. I can no longer do it. Therefore, an insulating resin is applied or the insulating resin is formed into a film.

However, if such an insulating adhesive layer is made of a material that does not contain a reinforcing material such as a glass woven fabric or a nonwoven fabric,
The occurrence of voids and peeling in the insulating adhesive layer has been observed, and there has been a problem that connection reliability and solder heat resistance are reduced.

An object of the present invention is to provide a multilayer wiring board having high connection reliability and solder heat resistance, particularly a multilayer wiring board used for a semiconductor chip package, and a method for manufacturing such a multilayer wiring board. .

[0011]

According to the present invention, there is provided a multilayer wiring board comprising:
For example, as shown in FIG.
A plurality of conductor circuit layers consisting of conductor circuits 3 supported on
An insulating adhesive layer for bonding the insulating layer to the conductive circuit layer or the insulating layer; a through hole having a conductor electrically connected to the conductive circuit on an inner wall thereof; and a cavity for accommodating the semiconductor chip. 5, the storage elastic modulus of the insulating adhesive layer 1 at the B stage is 30 ° C.
And the storage elastic modulus at the C stage of the insulating adhesive layer 1 is 30 MPa at 300 ° C.
And the glass transition temperature of the insulating adhesive layer 1 is 1
It is characterized by being at least 80 ° C.

Such a multilayer wiring board has a circuit board in which a conductor circuit 3 is formed on an insulating layer 2 by previously hollowing out a cavity 5 for accommodating a semiconductor chip 6, an insulating adhesive layer 1, and an insulating adhesive layer 1. Conductive circuit 3 on layer 2 or insulating layer 2
Is laminated and integrated by heating and pressurizing, a hole is formed as a through hole 4, and a conductor electrically connected to the conductor circuit 3 is formed on the inner wall of the hole. In the production method, the storage elastic modulus at the B stage is 3
It is characterized by using an insulating adhesive layer 1 having a storage elastic modulus at 300 ° C. of 30 MPa or more at 300 ° C. and a glass transition temperature of 180 ° C. or more at 0 ° C. in the range of 1000 to 5000 MPa.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The insulating adhesive layer used in the present invention is B
Storage elastic modulus on stage is 1000-5000 at 30 ° C
And the storage elastic modulus at the C stage is 30.
30 MPa or more at 0 ° C. and a glass transition temperature of 180
° C or higher, but the viscoelasticity at the B stage is 3
If the pressure is less than 1000 MPa at 0 ° C., the flow of the resin is large, so that the exudation into the cavity becomes large,
When it exceeds 5,000 MPa, the filling property of the inner layer conductor circuit becomes low or the handleability decreases, and the storage elastic modulus at the C stage is less than 30 MPa at 300 ° C., or the glass transition temperature is less than 180 ° C. If there is, the connection reliability and the solder heat resistance decrease due to the flow of the resin and the difference in the glass transition temperature with the insulating layer 2.

In the present invention, the insulating adhesive layer 1 is preferably an adhesive film composed of a polyamideimide resin and a thermosetting resin component. The polyamideimide resin includes a diamine having three or more aromatic rings. An aromatic polyamideimide resin obtained by reacting an aromatic diimide dicarboxylic acid represented by the general formula (1) obtained by reacting with trimetic anhydride and an aromatic diisocyanate represented by the general formula (2), or 2,2-bis [4- {4- (5-hydroxycarbonyl-1,3-dione-isoindolino) phenoxy} phenyl] propane as an aromatic diimide dicarboxylic acid and 4,4'-diphenylmethane as an aromatic diisocyanate It is preferable to use an aromatic polyamide-imide resin obtained by reacting with a diisocyanate. New

[0015]

Embedded image

[0016]

Embedded image

The diamine having three or more aromatic rings includes
2,2-bis [4- (4-aminophenoxy) phenyl] propane, bis [4- (3-aminophenoxy) phenyl] sulfone, bis [4- (4-aminophenoxy) phenyl] sulfone, 2,2- Bis [4- (4-aminophenoxy) phenyl] hexafluoropropane,
Bis [4- (4-aminophenoxy) phenyl] methane, 4,4-bis (4-aminophenoxy) biphenyl, bis [4- (4-aminophenoxy) phenyl] ether, bis [4- (4-aminophenoxy) )] Phenyl] ketone, 1,3-bis (4-aminophenoxy) benzene, 1,4-bis (4-aminophenoxy) benzene and the like can be used alone or in combination.

The aromatic diisocyanate includes 4,4
4′-diphenylmethane diisocyanate, 2,4-tolylene diisocyanate, 2,6-tolylene diisocyanate, naphthalene-1,5-diisocyanate, 2,
4-Tolylene dimer or the like can be used alone or in combination.

The thermosetting resin component includes an epoxy resin having two or more glycidyl groups and a curing agent for the epoxy resin.
It is preferable to use an epoxy resin having two or more glycidyl groups and its curing accelerator. Also, the more glycidyl groups, the better, and more preferably three or more. The amount of the glycidyl group varies depending on the number of the glycidyl groups, and the greater the amount of the glycidyl group, the smaller the amount of the glycidyl group. It is more preferable to use a curing agent for epoxy resin and a curing accelerator together. The curing agent or curing accelerator for the epoxy resin may be any of those that react with the epoxy resin or those that promote curing, such as amines, imidazoles, polyfunctional phenols, and acid anhydrides. Objects and the like can be used.

As the amines, dicyandiamide, diaminodiphenylmethane, guanylurea and the like can be used.
As the imidazoles, alkyl group-substituted imidazoles, benzimidazoles and the like can be used, and as the polyfunctional phenols, hydroquinone, resorcinol, bisphenol A and their halogen compounds, and novolaks which are condensates with aldehydes, resol resins, etc. And phthalic anhydride, hexahydrophthalic anhydride, benzophenonetetracarboxylic acid and the like can be used as acid anhydrides. Among them, it is preferable to use polyfunctional phenols as the curing agent and to use imidazoles as the curing accelerator.

In the case of amines, the necessary amount of these curing agents or curing accelerators is the equivalent of the active hydrogen equivalent of the amine,
An amount in which the epoxy equivalents of the epoxy groups of the epoxy resin are substantially equal is preferred. Next, in the case of imidazoles, the equivalent ratio to active hydrogen is not simply obtained, and empirically, epoxy 1
1 to 10 parts by weight is required for 00 parts by weight. In the case of polyfunctional phenols and acid anhydrides, 0.8 to 1.2 equivalents are required for 1 equivalent of the epoxy resin. If the amount of these curing agents or curing accelerators is small, uncured epoxy resin remains, the storage elastic modulus at 300 ° C. at the C stage is small, and if too large, unreacted curing agent and curing accelerator remain. , And the insulation is reduced.

In addition, if necessary, a catalyst for electroless plating can be added in order to increase the plating adhesion of the inner wall of the through hole and the like and to manufacture a wiring board by an additive method.

In the present invention, these compositions are mixed in an organic solvent to obtain a heat-resistant resin composition. As such an organic solvent, any organic solvent may be used as long as solubility can be obtained. Examples thereof include dimethylacetamide, dimethylformamide, dimethylsulfoxide, and N-methyl-2-.
Pyrrolidone, γ-butyrolactone, sulfolane, cyclohexanone and the like can be used. This heat resistant resin composition,
It can be applied to release PET to make an adhesive sheet, or it can be applied to one side of a metal foil to form an adhesive sheet with a metal foil. can do.

The compounding ratio of the heat-resistant resin composition is preferably from 10 to 150 parts by weight of the thermosetting resin component to 100 parts by weight of the polyamideimide resin, and less than 10 parts by weight of the thermosetting resin component. If there is, 30 at C stage
If the storage elastic modulus at 0 ° C. is low and exceeds 150 parts by weight, the compatibility is reduced and gelation occurs during stirring, and the flexibility of the film is reduced.

As the circuit board of the present invention, a circuit board obtained by etching and removing unnecessary copper foil of a copper-clad laminate used for a normal wiring board can be used. The insulating layer 2 of this copper-clad laminate is made by impregnating a thermosetting resin such as an epoxy resin, a phenol resin, a polyimide resin, or a polyamide resin, or a reinforcing fiber such as a glass cloth, glass paper, or aramid paper with these resins. Or a resin obtained by mixing the above-mentioned fibers, glass chopped strands, short fibers of resin, ceramic fibers, whiskers, or other reinforcing fibers with these resins. As the copper foil of the copper-clad laminate, in addition to a normal rolled copper foil or an electrolytic copper foil, a composite metal foil composed of a thin copper foil and a carrier metal supporting the same can be used. As a metal foil, a metal layer that can be subjected to an etching treatment different from copper, such as a product in which aluminum foil is subjected to a mold release treatment and bonded to a copper foil or a thin copper layer / nickel layer / thick copper layer, is removed by etching. For example, there is one used as a stopper when performing the operation.

As described above, a circuit board obtained by removing unnecessary portions of copper foil by etching can be used as described above, but a via hole can be formed first. That is, for example, using a double-sided copper-clad laminate for the copper-clad laminate, in the manner of producing a normal double-sided wiring board, drilling a hole that becomes a via hole, forming a conductor by plating at least on the inner wall of the hole, unnecessary unnecessary It is to produce a circuit board having wiring conductors on both sides by removing copper by etching. In addition, a copper-clad laminate with a hole to be a via hole is laminated on the circuit board on which the conductor circuit is formed via an insulating adhesive layer,
It can also be manufactured by heating and pressurizing to laminate and integrate, performing copper plating, metalizing the inner wall of the via hole, and removing unnecessary copper by etching. Furthermore, a copper-clad laminate with a hole to be a via hole is layered on it via an insulating adhesive layer, and the laminate is integrated by heating and pressing, copper plating is performed, and the inner wall of the via hole is metallized. This can be repeated by etching off the unnecessary copper, and all the conductor circuits can have the required number of layers.

The cavity according to the present invention forms a space for mounting the semiconductor chip 6 as shown in FIG.
In order to connect the wirings, a conductor circuit 3 serving as an internal terminal must be provided on the multilayer wiring board. If the number of the internal terminals is large, only one layer of wiring may be insufficient. As shown in FIG. 3, a conductor circuit 3 serving as an internal terminal can be provided in a plurality of layers. In this case, the shapes of the cavities are the same or larger in order from the insulating layer 2 closest to the place where the semiconductor chip 6 is bonded and fixed, and the conductive circuit 3 formed on each insulating layer 2 and exposed is A conductor circuit 3 serving as an internal terminal for making an electrical connection with the semiconductor chip 6 can be provided.

Further, the cavity of the present invention may be a through hole, and a heat sink 8 may be provided so as to cover one opening of the through hole as shown in FIG. it can. As shown in FIG.
As shown in FIG. 6, a support portion 81 on which the semiconductor chip 6 is mounted and a flange portion 82 thinner than the support portion 81 provided around the support portion 81 are used, and the outermost insulating layer 2 has substantially the same size as the support portion 81. A hole may be provided so that the support portion 81 of the heat sink 8 can be fitted into the hole. On the surface of the flange portion 82 of the heat sink 8 that is bonded to the insulating layer 2,
Irregularities can also be formed, and the adhesive strength between the heat sink 8 and the multilayer wiring board can be increased, which is preferable.

As a method of laminating such a multilayer wiring board, the insulating adhesive layer 1 and the circuit board formed as described above are combined with the mirror board 101 / product surface as shown in FIG. Protective film 105 for protection / Construction of multilayer wiring board in which insulating layer 2 and insulating adhesive layer 1 and insulating layer 2 or circuit board are stacked 104 / Cushion material 103 / Molded product 102 having perforated cavity shape / End plate 101 , And heating and pressing to laminate and integrate.

Further, when the heat sinks 8 are simultaneously bonded, as shown in FIG. 6B, the configuration at the time of lamination is changed to a flow rate at the lamination heating temperature like the end plate 101 / cushion material 103 / (for example, polyethylene film). A film 111 having a large melting point and a film 110 having a high melting point for protecting the surface of a product / a multi-layer wiring board structure 104 in which the insulating layer 2, the insulating adhesive layer 1, and the insulating layer 2 or a circuit board are stacked 104 / cushion material 103 / cavity Can be manufactured by stacking in order of the molded article 102 / end plate 101 having a hole in the shape of.

Such a multilayer wiring board can be provided with external terminals 11 for making an electrical connection with another wiring board. For example, as shown in FIG.
Is used, a pin grid array can be formed. Alternatively, as shown in FIG. 7B, a ball grid array can be formed by forming lands for making electrical connection by the solder balls 10. . Furthermore, FIG.
(C) As shown in FIG.
It can be an on-chip wiring board or a multi-chip module.

[0032]

【Example】

(Synthesis of Aromatic Polyamideimide) As a diamine having three or more aromatic rings in a 1-liter separable flask equipped with a cock and connected to a reflux condenser and having a 25-ml water content receiver, a thermometer, and a stirrer. 2-bis- [4-
(4-aminophenoxy) phenyl] propane 123.
2 g (0.3 mol), trimellitic anhydride 115.3
g (0.6 mol) was charged with 716 g of NMP (N-methyl-2-pyrrolidone) as a solvent, and the mixture was stirred at 80 ° C. for 30 minutes. Then, 143 g of toluene is charged as an aromatic hydrocarbon azeotropic with water, and then the temperature is raised to about 160
Reflux at 2 ° C. for 2 hours. About 10.8 of water
Make sure that no more than 1 ml of water has been collected and that no distilling of water can be seen.While removing the distillate remaining in the water content determination receiver, raise the temperature to about 190 ° C to remove toluene. did. Thereafter, the solution was returned to room temperature, and 75.1 g (0.3 mol) of 4,4'-diphenylmethane diisocyanate was charged as an aromatic diisocyanate, and 1
The reaction was performed at 90 ° C. for 2 hours. After completion of the reaction, an NMP solution resin of an aromatic polyamideimide resin (hereinafter abbreviated as PAI) was obtained.

Embodiment 1 This embodiment will be described with reference to FIGS. (1) As the insulating layer 2, a BT resin-based single-sided copper-clad laminate having a thickness of 0.4 mm as shown in FIG.
A H-HL830 (trade name, manufactured by Mitsubishi Gas Chemical Co., Ltd.) from which the copper foil has been removed, a counterbore processing is performed on one surface at a depth of 0.2 mm to form a recess 11 serving as a cavity; 2) As the insulating adhesive layer 1, the storage elastic modulus at the B stage as shown in FIG.
Storage elastic modulus at Pa, C stage is 100M at 300 ° C
EOCN1020 which is an aromatic polyamideimide resin / epoxy resin having a Pa and a glass transition temperature of 217 ° C.
The weight ratio of KA1160 (trade name, manufactured by Nippon Kayaku Co., Ltd.) / Polyfunctional phenols (trade name, manufactured by Dainippon Ink and Chemicals, Inc.) is 100/21/11 and has a thickness of 0.05 mm. An adhesive film 1b in which an opening 12b which is a cavity larger than the counterbored portion 11 of the substrate 2a is provided in the adhesive film; and (3) a BT resin having a thickness of 0.4 mm as shown in FIG. A CCH-HL830 (trade name, manufactured by Mitsubishi Gas Chemical Co., Ltd.), which is a single-sided copper-clad laminate, is provided with an opening 12c serving as a cavity having the same size as the opening 12b serving as a cavity of the adhesive film 1b. A substrate 2c on which a conductor circuit 3 serving as an internal terminal for connecting to the semiconductor chip 6 by wire bonding 13 is formed on a portion exposed when the semiconductor chip 6 is overlapped;
As shown in FIG. 8 (d), the same material as in (2) and a thickness of 0.
An adhesive film 1d having an opening 12d larger than the opening 12c serving as a cavity of the substrate 2c in an adhesive film of 075 mm, and (5) a BT resin having a thickness of 0.4 mm as shown in FIG. Is a single-sided copper-clad laminate
The substrate 2 on which the copper foil of H-HL830 (trade name, manufactured by Mitsubishi Gas Chemical Co., Ltd.) is removed and an opening 12e having the same size as the opening 12d serving as a cavity of the adhesive film 1d is provided.
e, (6) an adhesive film having the same material as (2) and a thickness of 0.1 mm as shown in FIG.
An adhesive film 1f provided with an opening 12f serving as a cavity having the same size as the opening 12e serving as a cavity of the substrate 2e, and (7) having a thickness of 0.2 as shown in FIG.
mm BT resin-based single-sided copper-clad laminate CCH-HL
830 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) was prepared as a substrate 2g from which the copper foil had been removed. (8) As shown in FIG.
(7) Configuration of multilayer wiring board 104 / cushion material 103
/ Molded product 102 with perforations in cavity shape / End plate 1
01 and 150 kg at 180 ° C. and 30 kgf / cm ²
The heating and pressurizing were carried out under the conditions of minutes, and the layers were integrated. (9) FIG.
As shown in FIG. 10 (a), a hole serving as a through hole 4 was formed in the laminated structure, and electroless plating 14 was performed on the inner wall and surface of the hole as shown in FIG.
As shown in FIG. 10 (c), unnecessary copper is removed by etching to form an outer layer conductive circuit 3, and further, a cavity is formed as shown in FIG. 10 (d). An opening 15 of the same size is provided in the same place as the part 12e by a router process in a corresponding place of the substrate 2g, and a plurality of pins 9 are fixed to the through hole 4,
A pin grid array having a cavity was prepared.

Example 2 (1) As the insulating layer 2, a BT resin-based single-sided copper-clad laminate having a thickness of 0.2 mm as shown in FIG.
CH-HL830 (Mitsubishi Gas Chemical Co., Ltd., trade name)
(2) Insulating adhesive layer 1
As shown in FIG. 11B, (2) of the first embodiment
Adhesive film 1 having an opening 12i for forming a cavity in an adhesive film of the same material having a thickness of 0.05 mm
i, and (3) a thickness of 0.4 as shown in FIG.
mm BT resin-based single-sided copper-clad laminate CCH-HL
830 (trade name, manufactured by Mitsubishi Gas Chemical Co., Ltd.), an opening 12j having the same size as the opening 12i serving as the cavity of the adhesive film 1i is provided. And bonding wire 13
And (4) an adhesive film of the same material as (2) and having a thickness of 0.05 mm as shown in FIG. An adhesive film 1k provided with an opening 12k larger than an opening 12j serving as a cavity of the substrate 2j, and (5) a BT resin-based single-sided copper-clad laminate having a thickness of 0.4 mm as shown in FIG. CCH-HL830 (trade name, manufactured by Mitsubishi Gas Chemical Co., Ltd.) having an opening 12 having the same size as the opening 12k serving as a cavity of the adhesive film 1k.
and a substrate 2l on which a conductor circuit 3 serving as an internal terminal for connecting to the semiconductor chip 6 and the bonding wire 13 is formed on a portion exposed when the substrate 2n is superimposed on the substrate 2n.
(6) As shown in FIG. 11 (f), an adhesive film provided with an opening 12m larger than the opening 12l serving as a cavity of the substrate 2l in an adhesive film of the same material as the above (2) and having a thickness of 0.05 mm 1m and (7) Copper foil of CCH-HL830 (trade name, manufactured by Mitsubishi Gas Chemical Co., Ltd.), which is a BT resin-based single-sided copper-clad laminate having a thickness of 0.4 mm as shown in FIG. Is removed, and an opening 12n having the same size as the opening 12m serving as a cavity of the adhesive film 1m is removed.
And (8) an adhesive film of the same material as in (2) having a thickness of 0.05 mm, as shown in FIG. 11 (h), having the same size as the opening 12n serving as a cavity of the substrate 1n. Film 1o provided with an opening 12o
And (9) a thickness of 0.4 m as shown in FIG.
m BT resin-based single-sided copper-clad laminate CCH-HL8
30 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) was prepared as a substrate 2p from which the copper foil had been removed. (10) As shown in FIG. 9, end plate 101 / protective film 105 / (1) to (1) above
(9) Configuration of multilayer wiring board 104 / cushion material 103
/ Molded product 102 with perforations in cavity shape / End plate 1
01, and the layers were integrated by heating and pressing at 180 ° C. and 30 kgf / cm ² for 150 minutes. (11) FIG.
As shown in FIG. 12A, a hole to be a through hole 4 is formed in the laminated product, and the inner wall and the surface of the hole are subjected to electroless plating 14 as shown in FIG.
As shown in FIG. 12C, a conductor circuit 3 including a land for fusing the solder ball 10 is formed. Further, in order to form a cavity, as shown in FIG.
The opening 15 having the same size in the same place as the opening 12o
Was provided in a corresponding portion of the substrate 1p by router processing, and a solder resist was applied and dried to produce a ball grid array.

Example 3 In Example 1, a heat sink 8 having a flange portion as shown in FIG. 5 was prepared by providing a through hole instead of counterboring the substrate 2a, and shown in FIG. 6 (b). As described above, the lamination structure is as follows: the end plate 101 / the cushion material 103 / the film 111 having a low melting point / the film 110 having a high melting point / the insulating layer 2
The same conditions, except that a multi-layer wiring board structure 104 in which the insulating adhesive layer 1 and the insulating layer 2 or a circuit board are stacked, a cushioning material 103, a molded product 102 having a hole in the cavity shape, and a mirror plate 101 are stacked in this order. Produced a pin grid array.

Examples 4 to 6 CCH-HL830 (trade name, manufactured by Mitsubishi Gas Chemical Co., Ltd.), which is a BT resin-based single-sided copper-clad laminate used in Examples 1 to 3, was coated with an epoxy resin-impregnated glass cloth copper-clad laminate. M which is a board
A pin grid array or a ball grid array was produced under the same conditions except that CL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was used.

Example 7 (1) As the insulating layer 2, an MCL-E-67 (Hitachi Chemical Co., Ltd.) which is a 0.2 mm thick epoxy resin impregnated glass cloth copper clad laminate as shown in FIG. A substrate 2q in which a concave portion 11 serving as a cavity is formed on one surface of a substrate obtained by removing a copper foil (trade name, manufactured by Kogyo Co., Ltd.) at a depth of 0.1 mm, and (2) an insulating adhesive layer 1 , FIG. 13 (b)
As shown in FIG.
Counterbore processing part 1 of substrate 2q on 05mm adhesive film
An adhesive film 1r provided with an opening 12r serving as a cavity larger than 1, and (3) as shown in FIG.
Two MCL-E-67 (manufactured by Hitachi Chemical Co., Ltd., trade name), which are epoxy resin impregnated glass cloth copper-clad laminates having a thickness of 0.1 mm, were previously provided with conductor circuits 3 and via holes, respectively. The one with the hole that becomes 7
Adhesive film 21 of the same material as in (2) and having a thickness of 0.1 mm
Through 1, 180 ° C., in a laminate of the adhesive under the conditions of 30 kgf / cm ^2, as shown in FIG. 13 (d), an opening 12s of the same size as the opening 12r of the cavity of the adhesive film 1r The substrate 2 on which a conductor circuit 3 serving as an internal terminal for connecting to the semiconductor chip 6 by wire bonding 13 is formed in a portion exposed when the substrate 2u is overlaid.
(4) An opening 12t larger than the opening 12s serving as a cavity of the substrate 2s is formed on an adhesive film of the same material as in (2) having a thickness of 0.05 mm as shown in FIG. And (5) MCL-E- which is an epoxy resin-impregnated glass cloth copper-clad laminate having a thickness of 0.1 mm in advance as shown in FIG.
67 (manufactured by Hitachi Chemical Co., Ltd., trade name) 2 sheets 203,
204, each having a conductor circuit 3 and a hole to be a via hole 7 were formed by using the same material as in (2) and having a thickness of 0.1.
180 ° C., 30 kg through an adhesive film 212 mm
As shown in FIG. 13 (g), an opening 12u having the same size as the opening 12t serving as a cavity of the adhesive film 1t is provided on the substrate laminated and bonded under the condition of f / cm ² and the substrate 2w is superposed. A substrate 2u on which a conductor circuit 3 serving as an internal terminal for connecting the semiconductor chip 6 to the semiconductor chip 6 with the bonding wire 13 is formed, and (6) the above-mentioned (2) as shown in FIG. An opening 1 serving as a cavity of the substrate 2u is formed on a 0.05 mm thick adhesive film of the same material.
Adhesive film 1v provided with opening 12v larger than 2u
And (7) a thickness of 0.4 m as shown in FIG.
MCL is an epoxy resin impregnated glass cloth copper-clad laminate
Except for the copper foil of -E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.), the opening 1 serving as a cavity of the adhesive film 1v.
A substrate 2w provided with an opening 12w of the same size as 2v,
(8) As shown in FIG. 13 (j), the substrate 2w is placed on an adhesive film of the same material as in (2) having a thickness of 0.05 mm.
An adhesive film 1x provided with an opening 12x having the same size as the opening 12w to be the cavity of (9) FIG.
Substrate 2y excluding the copper foil of MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a 0.4 mm-thick epoxy resin-impregnated glass cloth copper-clad laminate as shown in (k).
(10) As shown in FIG.
/ Protective film 105 / Construction of multilayer wiring board 104 of (1) to (9) above / Cushion material 103 / Molded product 102 with perforations in cavity shape / End plate 101: 180 ° C., 30 kgf / cm integrated heating and pressing laminate under conditions of ² in 150 minutes. (11) A hole to be a through hole 4 is formed in the laminated product, electroless plating 14 is performed on the inner wall and surface of the hole, and electroplating is further performed to form the outer conductor circuit 3 and further a cavity is formed. In order to achieve this, an opening 15 having the same size as that of the opening 12w serving as a cavity of the substrate 2w is provided in a corresponding portion of the substrate 2y by router processing, and wiring for a multilayer chip carrier as shown in FIG. A plate was made.

Examples 8 to 11 In Examples 1 to 3, CCH-HL830 (trade name, manufactured by Mitsubishi Gas Chemical Co., Ltd.), which is a BT resin-based copper-clad laminate, and in Example 7, epoxy resin impregnated glass In place of MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.), a cloth-clad laminate, MCL-I-671 (polyamide-impregnated glass cloth copper-clad laminate, manufactured by Hitachi Chemical Co., Ltd.) Examples 1 to 3 except that
A pin grid array, a ball grid array, or a wiring board for a multi-layer chip carrier was manufactured under the same conditions as in the above-mentioned embodiments.

Examples 12 to 22 In place of the insulating adhesive layer used in Examples 1 to 11, the elastic modulus at the B stage was 3500 MPa at 30 ° C., the elastic modulus at the C stage was 170 MPa at 300 ° C., and the glass transition. Aromatic polyamide-imide resin having a temperature of 223 ° C./EOC
N1020 (Epoxy resin, manufactured by Nippon Kayaku Co., Ltd.) / K
A1160 (polyfunctional phenols, manufactured by Dainippon Ink and Chemicals, Inc.) was used under the same conditions as in each example except that an adhesive film having a weight ratio of 100/43/23 was used.
A pin grid array, a ball grid array, or a wiring board for a multilayer chip carrier was manufactured.

Comparative Examples 1 to 8 In place of the insulating adhesive layer used in Examples 1 to 8, the elastic modulus at the B stage was 2500 MPa at 30 ° C., and the elastic modulus at the C stage was 5.2 MPa at 300 ° C. A pin grid array, a ball grid array, or a wiring board for a multi-layer chip carrier was produced under the same conditions as in the respective examples except that an adhesive film composed of only a polyamideimide resin having a glass transition temperature of 229 ° C. was used.

Comparative Examples 9 to 16 In place of the insulating adhesive layer used in Examples 1 to 8, aromatic polyamideimide resin / EOCN1020 (epoxy resin, manufactured by Nippon Kayaku Co., Ltd.) / KA1160 (polyfunctional phenols, Weight ratio of Dai Nippon Ink Industry Co., Ltd.) is 1
A pin grid array, a ball grid array, or a wiring board for a multi-layer chip carrier was manufactured under the same conditions as in each example except that an adhesive film consisting of 00/98/58 was used.

In the initial state, the multilayer wiring board thus manufactured was good without any peeling or voids.
However, when the solder float test was performed at 260 ° C. for 2 minutes, no peeling or voids occurred in the insulating adhesive layer in the example, but the storage elastic modulus in the C stage was obtained in the comparative examples 1 to 8. , A large number of peelings and voids occurred in the insulating adhesive layer. In the case of Comparative Examples 9 to 16, the amount of the thermosetting resin component was large, and gelling at the time of stirring or formation of a film was impossible, and a multilayer wiring board could not be produced.

[0043]

As described above, according to the present invention,
The insulating adhesive layer used for the multilayer wiring board has a storage elastic modulus at the B stage in the range of 1000 to 5000 MPa at 30 ° C., a storage elastic modulus at the C stage of 300 MPa or more at 30 ° C., and a glass transition temperature. Is 180
By adjusting the temperature to not less than ° C., it is possible to provide a multilayer wiring board having good handleability of the B stage, excellent connection reliability and heat resistance, and a method for manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an example of use of the present invention.

FIG. 2 is a sectional view showing a first embodiment of the present invention.

FIG. 3 is a sectional view showing a second embodiment of the present invention.

FIG. 4 is a sectional view showing a third embodiment of the present invention.

FIG. 5 is a sectional view showing a fourth embodiment of the present invention.

FIGS. 6A and 6B are schematic cross-sectional views for explaining an example of the present invention.

FIGS. 7A to 7C are cross-sectional views showing another embodiment of the present invention.

FIGS. 8A to 8G are cross-sectional views each showing a configuration of an example of the present invention.

FIG. 9 is a cross-sectional view for explaining a method according to one embodiment of the present invention.

FIGS. 10A to 10E are cross-sectional views illustrating a method according to the first embodiment of the present invention.

FIGS. 11A to 11E are cross-sectional views each showing a configuration of another embodiment of the present invention.

FIGS. 12A to 12D are cross-sectional views illustrating a method according to another embodiment of the present invention.

13 (a) to 13 (k) are cross-sectional views each showing a configuration of still another embodiment of the present invention.

FIG. 14 is a cross-sectional view illustrating a structure according to still another embodiment of the present invention.

[Explanation of symbols]

1. 1. Insulating adhesive layer 2. Insulating layer 3. Conductor circuit serving as internal terminal Through hole 5. Cavity 6. Semiconductor chip 7. Via hole 8. Heat sink 81. Supporting part 82. Tsuba 9. Pin 10. Solder ball 11. Recesses 12b, 12c, 12d, 12e, 12f, 12i, 1
2j, 12k, 12l, 12m, 12n, 12o, 12
r, 12s, 12t, 12u, 12v, 12w, 12
x. Opening serving as cavity 13. Bonding wire 14. Plating 15. Opening 101. End plate 102. Molded product 103. Cushioning material 104. Configuration of multilayer wiring board 105. Protective film 110. High melting point film 111. Low melting point film 1b, 1d, 1f, 1i, 1k, 1m, 1o, 1r, 1
t, 1v, 1x, 211, 212. Adhesive film 2a, 2c, 2e, 2g, 2h, 2j, 2, 1n, 2n
p, 2q, 2s, 2u, 2w, 2y, 201, 202
0, 203, 204. substrate

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuichi Shimayama 1500 Ogawa, Oaza, Shimodate City, Ibaraki Prefecture Inside Shimodate Research Laboratory, Hitachi Chemical Co., Ltd.

Claims (22)

[Claims] A plurality of insulating layers; a plurality of conductive circuit layers comprising circuit conductors supported by the insulating layers; an insulating adhesive layer for bonding the insulating layers to the conductive circuit layers or the insulating layers; In a multilayer wiring board having a through hole having an electrically connected conductor on the inner wall thereof and a cavity for receiving a semiconductor chip, the storage elastic modulus of the insulating adhesive layer at the B stage in the range of 1000 to 5000 MPa at 30 ° C. And the storage elastic modulus at the C stage of the insulating adhesive layer is 300 ° C.
, And the glass transition temperature of the insulating adhesive layer is 180 ° C or more. 2. The multilayer wiring board according to claim 1, wherein the insulating adhesive layer is an adhesive film comprising a polyamideimide resin and a thermosetting resin component. 3. The multilayer wiring board according to claim 2, wherein the thermosetting resin component comprises an epoxy resin having two or more glycidyl groups and a curing agent or a curing accelerator thereof. 4. The polyamideimide resin and the thermosetting resin component have a weight ratio of 10 to 150 parts by weight of the thermosetting resin component to 100 parts by weight of the polyamideimide resin. 4. The multilayer wiring board according to 2 or 3. 5. The multilayer wiring board according to claim 1, wherein said multilayer wiring board has a via hole for making an electrical connection between adjacent conductive circuit board layers. 6. The semiconductor device according to claim 6, wherein the cavities have the same or larger sizes in order from an insulating layer closest to a portion where the semiconductor chip is bonded and fixed. The multilayer wiring board according to any one of claims 1 to 5, further comprising an internal terminal portion for making an electrical connection. 7. The method according to claim 1, wherein the cavity is a through hole, and a heat sink is provided at one opening of the through hole so as to cover the opening. 2. The multilayer wiring board according to item 1. 8. The multilayer according to claim 1, wherein an external terminal for making an electrical connection with another wiring board is provided on the outermost insulating layer. Wiring board. 9. The multilayer wiring board according to claim 8, wherein the external terminals are a plurality of pins. 10. The multilayer wiring board according to claim 8, wherein the external terminals are lands for making electrical connection by solder balls. 11. A circuit board having a conductive circuit formed on an insulating layer, a circuit board having a conductive circuit formed on an insulating layer, an insulating adhesive layer, and a conductive circuit formed on the insulating layer or the insulating layer. In a method of manufacturing a multilayer wiring board in which a circuit board is superimposed, laminated by heating and pressurizing to form a through hole, and a conductor electrically connected to a conductor circuit is formed on an inner wall of the hole. The storage elastic modulus at the B stage is in the range of 1000 to 5000 MPa at 30 ° C., and the storage elastic modulus at the C stage is 30 MPa at 300 ° C.
A method for producing a multilayer wiring board, comprising using an insulating adhesive layer having a glass transition temperature of 180 ° C. or higher. 12. The method according to claim 11, wherein the insulating adhesive layer is an adhesive film comprising a polyamideimide resin and a thermosetting resin component. 13. The method according to claim 12, wherein the thermosetting resin component is an epoxy resin having two or more glycidyl groups and a curing agent or a curing accelerator thereof. 14. The polyamideimide resin and the thermosetting resin component in a weight ratio of 10 to 100 parts by weight of the thermosetting resin component to 100 parts by weight of the polyamideimide resin. 14. The method for producing a multilayer wiring board according to 12 or 13. 15. A circuit board in which a conductive circuit is formed on an insulating layer, a circuit board in which a conductive circuit is formed on an insulating layer, an insulating adhesive layer, and a circuit in which a conductive circuit is formed on the insulating layer. 15. The method according to claim 11, wherein the step of stacking the plates and heating and pressurizing to laminate and integrate includes at least a step of forming a via hole for making electrical connection between adjacent conductor circuit layers. The method for producing a multilayer wiring board according to any one of the above. 16. A copper-clad laminate having a hole to be a via hole is superimposed on a conductor circuit of a circuit board via an insulating adhesive layer, and the laminate is integrated by heating and pressing, and copper plating is performed. Metallizing the inner wall of the substrate, removing unnecessary copper by etching, and further laminating a copper-clad laminate having a hole to be a via hole through an insulating adhesive layer, and repeating this process. Item 16. The method for producing a multilayer wiring board according to Item 15. 17. The method for manufacturing a multilayer wiring board according to claim 15, wherein a circuit board in which an inner wall of a hole serving as a via hole is metallized is used. 18. A cavity for receiving a semiconductor chip, which is provided by hollowing out an insulating adhesive layer and a plurality of circuit boards, has a size in order from an insulating layer closest to a position where the semiconductor chip is bonded and fixed. The method for manufacturing a multilayer wiring board according to any one of claims 11 to 17, wherein the same or larger one is used. 19. An insulating adhesive layer, an insulating layer, and a circuit board,
The cavity for housing the semiconductor chip is hollowed out in advance, and the circuit board, the insulating adhesive layer, and the insulating layer or the circuit board are stacked, laminated under heat and pressure, and a hole is formed as a through hole. 12. A heat sink is provided at one opening of the through hole after forming a conductor electrically connected to the conductor circuit of the circuit board on the inner wall of the hole. 19. The method for producing a multilayer wiring board according to any one of items 18 to 18. 20. A heat sink having a support portion on which a semiconductor chip is mounted, and a flange portion thinner than the support portion provided around the support portion, wherein a hole having substantially the same size as the support portion is formed in the outermost insulating layer. Is provided, and the support of the heat sink is fitted into the hole.
The method for manufacturing a multilayer wiring board according to claim 19, wherein the bonding is performed. 21. The method for manufacturing a multilayer wiring board according to claim 19, wherein the flange of the heat sink is formed with irregularities. 22. A circuit board in which a cavity for receiving a semiconductor chip is previously cut out, an insulating adhesive layer,
When laminating and integrating the insulating layer or circuit board, and applying heat and pressure to laminate and integrate, the configuration at the time of lamination is made by laminating a press head plate / a film-like material that protects the surface of the product / insulating adhesive layer and a plurality of circuit boards. 22. A laminated product in which layers are formed in that order: a molded product having a hole in the shape of a cushion / cavity / cavity / a press head plate, and laminated by heating and pressing.
The method for producing a multilayer wiring board according to any one of the above.