JPH10270664A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique, by which the deterioration of the charge holding characteristics of a capacitive element is eliminated while the quantity of charges stored in the capacitive element is increased. SOLUTION: In the method, the semiconductor integrated circuit device with capacitive elements 20 formed by successively laminating lower electrodes 16, dielectric films 17 and upper electrodes 18 respectively is manufactured. Silicon nitride films 17A containing chlorine atom concentration of 2×10<13> [atoms/cm<2> ] or more are formed, oxidation is executed, and silicon oxide films 17B are formed onto the surfaces of the silicon nitride films 17A and the dielectric films 17 are shaped at that time. The silicon nitride films 17A are formed by a chemical vapor growth method using dichlorosilane and ammonia.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a capacitance element formed by sequentially laminating a lower electrode, a dielectric film, and an upper electrode. It is about technology.

[0002]

As a semiconductor integrated circuit device DRAM (D y
namic R andum A ccess M emory) there is. This DRAM
Is of the memory cell, MISFET (M etal I nsulator S e
formed of a series circuit of the miconductor F eild E ffect T ransistor) and capacitive element to store one bit of information ( "0" or "1"). The MISFET is mainly composed of a semiconductor region which is a channel forming region, a gate insulating film, a gate electrode, a pair of semiconductor regions which are a source region and a drain region. Capacitive element includes a lower electrode, a dielectric film, formed by sequentially stacking the respective upper electrode STC (St ACKE
It is composed of a d C apacitor) structure. Each of the lower electrode and the upper electrode is formed of a silicon film into which an impurity for reducing a resistance value is introduced.

The dielectric film of the capacitor has a single-layer structure, a two-layer structure, or a three-layer structure, as described in, for example, Japanese Patent Application Laid-Open No. 3-16153.
The single-layer dielectric film is formed by oxidizing the surface of the lower electrode to form a silicon oxide film. The two-layer dielectric film is formed on the lower electrode by chemical vapor deposition (CVD).
Law: C hemical V apor D eposition) in forming a silicon nitride film, then, it is formed by forming a silicon oxide film by oxidizing the surface of the silicon nitride film. The two-layer structure is referred to as a NO (N itride / O xide) film. The dielectric film having a three-layer structure forms a silicon oxide film by oxidizing the surface of the lower electrode, and then forms a silicon nitride film on the silicon oxide film by a chemical vapor deposition method. It is formed by oxidizing the surface of the silicon film to form a silicon oxide film. The three-layer structure ONO (O xide / N itride / O xi
de) It is called a membrane.

[0004]

In the capacitive element of the memory cell described above, in the silicon oxide film formed by oxidizing the surface of the silicon nitride film, there is a defect that the atomic group surrounding the lattice defect (vacancy point) has. Saturated bond, that is, dangling bond
There are many. Similarly, there are many dangling bonds in the silicon nitride film. The electrons accumulated in one electrode are easily trapped in these dangling bonds. For this reason, there has been a problem that electrons accumulated in one electrode leak to the other electrode, and the charge retention characteristics of the capacitor deteriorate.

Further, the growth rate of the silicon oxide film formed by oxidizing the surface of the silicon nitride film is high, and it is difficult to form a thin silicon oxide film. The amount of charge stored in the capacitor is proportional to the area of the dielectric film between one electrode and the other electrode and inversely proportional to the film thickness of the dielectric film. Want to be thin.

An object of the present invention is to provide a technique capable of suppressing the deterioration of the charge retention characteristic of the capacitive element.

Another object of the present invention is to provide a technique capable of reducing the film thickness of a silicon oxide film formed on a silicon nitride film and increasing the amount of charge stored in a capacitive element.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A method of manufacturing a semiconductor integrated circuit device having a capacitance element in which a lower electrode, a dielectric film, and an upper electrode are sequentially laminated, wherein a chlorine atom concentration is 2 × 10 ¹³ [atoms]
/ Cm ² ] or more, a step of performing an oxidation treatment, forming a silicon oxide film on the surface of the silicon nitride film to form a dielectric film. The silicon nitride film is formed by a chemical vapor deposition method using dichlorosilane and ammonia.

According to the above-described means, when the surface of the silicon nitride film is oxidized to form a silicon oxide film, dangling bonds are terminated with nitrogen atoms and unbonded bonds are formed in the silicon oxide film. Hands almost disappear. Further, dangling bonds in the silicon nitride film are also terminated by chlorine atoms, and dangling bonds hardly exist in the silicon nitride film. Therefore, the electrons accumulated in one electrode do not leak to the other electrode, so that the deterioration of the charge retention characteristic of the capacitor can be suppressed.

When the silicon nitride film is oxidized to form a silicon oxide film, the number of silicon atoms existing on the surface of the silicon nitride film is reduced, so that the reaction between silicon atoms and oxygen atoms is suppressed. . Therefore, the growth rate of the silicon oxide film is reduced, so that a thin silicon oxide film can be formed on the silicon nitride film. As a result, it is possible to increase the charge storage amount of the capacitive element.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments of the invention, components having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

FIG. 1 shows a DRA which is an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of an M memory cell, and FIG. 2 is a cross-sectional view showing a schematic configuration of the memory cell.

As shown in FIG. 1, a memory cell M of a DRAM is constituted by a series circuit of a MISFET 19 and a capacitance element 20 and stores 1-bit information ("0" or "1"). This memory cell M is arranged at the intersection of a word line WL extending in the row direction (Y direction) and a data line DL extending in the column direction (X direction).

The plurality of memory cells M are arranged in the direction in which the word lines WL extend and the direction in which the data lines DL extend in the memory cell array portion of the DRAM.
The memory cell array section is surrounded by a peripheral circuit section in which peripheral circuits such as a word driver circuit, an X decoder circuit, and a Y decoder circuit are arranged.

One semiconductor region of the MISFET 19 is electrically connected to the data line DL, and the other semiconductor region is electrically connected to one electrode of the capacitive element 20,
The gate electrode is electrically connected to the word line WL.

When the memory cell M is selected, the word line WL is fixed at a potential of, for example, 5 [V]. When the memory cell M is not selected, the word line WL is fixed at a potential of, for example, 0 [V]. The potential of the data line DL is fixed to, for example, 3.3 [V] when the charge is accumulated in the capacitor 20, and is fixed to 0 [V] when the charge is not accumulated in the capacitor 20. Is done.

Next, a specific structure of the memory cell M will be described with reference to FIG.

As shown in FIG. 2, the DRAM is mainly composed of the semiconductor substrate 1. The semiconductor substrate 1 is formed of a p-type semiconductor substrate made of, for example, single crystal silicon.

The MISFET 19 of the memory cell M is
It is formed on the surface of the p-type well region 2 formed in the element formation region of the semiconductor substrate 1. The element forming region of the semiconductor substrate 1 has its periphery defined by a field insulating film 3 formed in the element isolating region, and is isolated from other element isolating regions.

The MISFET 19 mainly includes a p-type well region 2 as a channel forming region, a gate insulating film 4, a gate electrode 5, a pair of n-type semiconductor regions 7 as source and drain regions, and a pair of n-type semiconductors. The region 9 is configured. That is, the MIS of the memory cell M of the present embodiment
The FET 19 has an n-channel conductivity type. The gate insulating film 4 is formed on the surface of the p-type well region 2,
For example, it is formed of a silicon oxide film. The gate electrode 5 is
It is formed on the surface of the gate insulating film 4 and is formed of, for example, a silicon film into which an impurity (for example, phosphorus (P)) that reduces the resistance value is introduced. Each of the pair of n-type semiconductor regions 7, which is a source region and a drain region, is formed on the surface of the n-type well region 2 and introduced in self-alignment with the gate electrode 5 (for example, phosphorus (P (P )). Each of the pair of n-type semiconductor regions 9 serving as the source region and the drain region is an n-type impurity (for example, introduced in self-alignment with the sidewall spacers 8 formed on both sides of the gate electrode 5 in the gate length direction). It is formed of arsenic (As). Each of the pair of n-type semiconductor regions 9 is formed with a higher impurity concentration than the pair of n-type semiconductor regions 7. That is, the MISFET of the memory cell M of the present embodiment
19 is composed of LDD (L ightly D oped D rain ) structure.

The gate electrode 5 of the MISFET 19 is
The gate electrode 5 of the MISFET 19 of another memory cell M integrated with the word WL extending on the field insulating film 3 and arranged along the direction in which the word line WL extends.
Is electrically connected to. Gate electrode 5, word line W
The upper surface of each L is covered with an insulating film 6, and the side wall surfaces of the gate electrode 5 and the word line WL are covered with a side wall spacer 8. Each of the insulating film 6 and the sidewall spacer 8 is formed of, for example, a silicon oxide film.

A data line DL is electrically connected to one n-type semiconductor region 9 of the MISFET 19 through a connection hole 12 formed in an interlayer insulating film 10. The data line DL is, for example, an impurity (for example, phosphorus) that reduces the resistance value.
(P))-introduced silicon film 11A and this silicon film 11A
Of tungsten (W) film 11B formed on the surface of the.

The capacitive element 20 of the memory cell M is formed on the surface of the interlayer insulating film 13. This capacitive element 20
Has an STC structure in which a lower electrode 16, a dielectric film 17, and an upper electrode 18 are sequentially laminated. Each of the lower electrode 16 and the upper electrode 18 is an impurity that reduces the resistance value.
It is formed of a silicon film into which (for example, phosphorus (P)) is introduced.
The dielectric film 17 is formed of, for example, a silicon nitride film 17A and a silicon oxide film 17B. The silicon nitride film 17A is formed on the surface of the lower electrode 16 by chemical vapor deposition. The silicon oxide film 17B is formed by oxidizing the surface of the silicon nitride film 17A.

The lower electrode 16 of the capacitor 20 is electrically connected to the other n-type semiconductor region 9 of the MISFET 19 via the conductive film 15. The conductive film 15 is formed by connecting holes 1 formed in the interlayer insulating film 13 and the interlayer insulating film 10, respectively.
4 embedded. The conductive film 15 is formed of, for example, a silicon film into which an impurity (for example, phosphorus (P)) for reducing a resistance value is introduced.

Although not shown, the upper electrode 16 of the capacitive element 20 is covered with an interlayer insulating film. A multilayer wiring layer is formed on the surface of this interlayer insulating film, and the uppermost wiring layer is covered with a final protective film.

Next, a method of manufacturing the memory cell M will be briefly described with reference to FIGS.

First, a semiconductor substrate 1 is prepared.

Next, a p-type well region 2 is formed on the surface of the semiconductor substrate 1, and then a field insulating film 3 is formed on an element isolation region of the semiconductor substrate 1. The field insulating film 3 is formed of, for example, a silicon oxide film formed by using a known selective oxidation method.

Next, a gate insulating film 4 is formed on the surface of the element forming region of the semiconductor substrate 1 whose periphery is defined by the field insulating film 3. The gate insulating film 4 is formed of, for example, a silicon oxide film formed by oxidizing the element formation region of the semiconductor substrate 1.

Next, on the entire surface of the semiconductor substrate 1 including the field insulating film 3 and the gate insulating film 4, insulating films made of an impurity-doped silicon film and a silicon oxide film are sequentially formed. I do. Then, the insulating film and the silicon film are sequentially patterned to form the gate electrode 5 having the upper surface covered with the insulating film 6 and the word line WL having the upper surface covered with the insulating film 6.

Next, in the element formation region of the semiconductor substrate 1, an n-type impurity is introduced into the surface of the p-type well region 2 in a self-aligned manner with respect to the gate electrode 5 to form a pair of source and drain regions. The n-type semiconductor region 7 is formed.

Next, sidewall spacers 8 are provided on both sides of the gate electrode 5 and the word line WL in the gate length direction.
To form The sidewall spacers 8 are formed by forming a silicon oxide film on the entire surface of the semiconductor substrate 1 including the insulating film 6 and then performing anisotropic etching on the silicon oxide film.

Next, in the element formation region of the semiconductor substrate 1, an n-type impurity is introduced into the surface of the p-type well region 2 in a self-aligned manner with respect to the side wall spacer 8, and a pair of a source region and a drain region is formed. N-type semiconductor region 9
To form In this process, the MIS of the memory cell M
The FET 19 is formed.

Next, an interlayer insulating film 10 made of a silicon oxide film is formed on the entire surface of the semiconductor substrate 1. Thereafter, a connection hole 12 exposing the surface of one n-type semiconductor region 9 of the MISFET 19 is formed.
A data line DL electrically connected to one n-type semiconductor region 9 of the ET 19 is formed.

Next, an interlayer insulating film 1 made of a silicon oxide film is formed over the entire surface of the semiconductor substrate 1 including the data line DL.
3 is formed, and then the interlayer insulating film 13 and the interlayer insulating film 1 are formed.
At 0, a connection hole 14 exposing the surface of the other n-type semiconductor region 9 of the MISFET 19 is formed.

Next, a conductive film 15 is embedded in the connection hole 14. The conductive film 15 is formed of, for example, a silicon film into which impurities are introduced.

Next, a silicon film doped with impurities (for example, phosphorus (P) is formed on the entire surface of the semiconductor substrate 1 including the conductive film 15 by, for example, the CVD method. After that, the silicon film is patterned. 3, a lower electrode 16 connected to the conductive film 15 is formed, as shown in Fig. 3. In this step, although not shown,
A natural oxide film is formed. The natural oxide film is formed by a small amount of oxygen (O ₂ ) or water (H ₂ O) caught in the furnace from the furnace opening when the silicon film is formed by the CVD method. This natural oxide film forms a weak spot, and the capacitive element 2
This causes deterioration of the charge retention characteristic of 0.

Next, the natural oxide film is removed using, for example, a hydrofluoric acid aqueous solution.

Next, as shown in FIG. 4, a silicon nitride film having a chlorine atom concentration of 2 × 10 ¹³ [atoms / cm ² ] or more is formed on the entire surface of the semiconductor substrate 1 including the gate electrode 16. 17A is formed with a thickness of, for example, about 2 [nm]. The silicon nitride film 17A is formed by chemical vapor deposition (CVD) using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ).
Method). The chlorine atom concentration of the silicon nitride film 17A can be controlled by adjusting the ambient temperature at the time of formation. The dangling bonds in the silicon nitride film 17A are terminated with chlorine atoms, and almost no dangling bonds are present in the silicon nitride film 17A.

Next, the surface of the silicon nitride film 17A is oxidized to form a silicon oxide film 17B on the surface of the silicon nitride film 17A as shown in FIG. In this step, the silicon oxide film 17B is formed while terminating dangling bonds with chlorine atoms of the silicon nitride film 17A, so that dangling bonds hardly remain in the silicon oxide film 17B. Moreover, since the number of silicon atoms existing on the surface of the silicon nitride film 17A is reduced, the reaction between silicon atoms and oxygen atoms is suppressed. Therefore, the growth rate of the silicon oxide film 17B slows down, so that the thin silicon oxide film 17B can be formed on the silicon nitride film 17A. By this step, the dielectric film 16 having a two-layer structure including the silicon nitride film 17A and the silicon oxide film 17B is formed.

Next, a silicon film having impurities (for example, phosphorus (P)) introduced therein is formed on the surface of the silicon oxide film 17B by, for example, a chemical vapor deposition method. Thereafter, the silicon film, the silicon oxide film 17B, and the silicon nitride film 17A are sequentially patterned to form the upper electrode 18, thereby forming the capacitive element 20 as shown in FIG. A memory cell M that stores bit information is formed.

With respect to the characteristics of the memory cell M formed as described above, a sample prepared by changing the concentration of chlorine atoms in the silicon nitride film 17A was measured. The results are shown in FIG. 7) and FIG. 7 (correlation diagram between chlorine atom concentration in the silicon nitride film and the defect rate). In FIG. 6, the vertical axis represents the chlorine atom concentration [atoms / cm ² ] in the silicon nitride film, and the horizontal axis represents the leak current [A / cm ² ].

In FIG. 7, the vertical axis represents the concentration of chlorine atoms in the silicon nitride film [atoms / cm ² ], and the horizontal axis represents the refresh time defect rate [%]. As shown in FIG. 6, the leak current decreases as the concentration of chlorine atoms in the silicon nitride film increases. As shown in FIG. 7, the refresh time failure rate sharply increases from around 2 × 10 ¹³ [atoms / cm ² ]. From these results, the present inventor considers that the chlorine atom concentration of the silicon nitride film is preferably set to 2 × 10 ¹³ [atoms / cm ² ] or more.

As described above, the lower electrode 16 and the dielectric film 1
7. Capacitance element 2 in which upper electrode 18 is sequentially laminated
A method for manufacturing a DRAM (semiconductor integrated circuit device) having a zero concentration, comprising forming a silicon nitride film 17A having a chlorine atom concentration of 2 × 10 ¹³ [atoms / cm ² ] or more, performing an oxidation process, A step of forming a silicon oxide film 17B on the surface of the silicon film 17A to form a dielectric film 17 is provided. Thus, when the surface of silicon nitride film 17A is oxidized to form silicon oxide film 17B, dangling bonds are terminated with nitrogen atoms, and almost all dangling bonds are present in silicon oxide film 17B. No longer. In addition, the silicon nitride film 17
The dangling bonds in A are also terminated by chlorine atoms, and the silicon nitride film 17
There is almost no dangling bond in A. Therefore,
Since the electrons accumulated in the upper electrode 16 do not leak to the other electrode, it is possible to suppress the deterioration of the charge retention characteristic of the capacitive element 20.

When the silicon nitride film 17A is oxidized to form the silicon oxide film 17B, the number of silicon atoms present on the surface of the silicon nitride film 17A is reduced, so that the reaction between the silicon atoms and the oxygen atoms is reduced. Is suppressed. Therefore, the growth rate of silicon oxide film 17B is reduced, so that silicon nitride film 17A
A thin silicon oxide film 17B can be formed on top. As a result, the charge storage amount of the capacitor 20 can be increased.

The inventions made by the present inventors are as follows.
Although specifically described based on the above embodiment, the present invention is
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

For example, the present invention can be applied to a semiconductor integrated circuit device having a capacitor in which a dielectric film is formed by an ONO film.

Further, the present invention can be applied to a flash memory (semiconductor integrated circuit device) having a memory cell which is a nonvolatile memory element formed by sequentially stacking a floating gate electrode, an interlayer insulating film, and a control gate electrode. In this case, the floating gate electrode, the interlayer insulating film, and the control gate electrode of the nonvolatile memory element correspond to the lower electrode, the dielectric film, and the upper electrode of the capacitive element, respectively.

[0052]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

Deterioration of the charge retention characteristics of the capacitor can be suppressed.

Further, the amount of charge stored in the capacitor can be increased.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a memory cell of a DRAM according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a schematic configuration of the memory cell.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing the memory cell.

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the memory cell.

FIG. 5 is a cross-sectional view for explaining the method for manufacturing the memory cell.

FIG. 6 is a correlation diagram between a chlorine atom concentration of a silicon nitride film and a leak current.

FIG. 7 is a correlation diagram between the chlorine atom concentration of the silicon nitride film and the refresh time defective rate.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... P-type well region, 3 ... Field insulating film, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... Insulating film, 7 ... N-type semiconductor region, 8 ... Sidewall spacer, 9 ... N Type semiconductor region, 10 ... interlayer insulating film, 12 ... connecting hole, 13 ... interlayer insulating film, 14 ... connecting hole, 15 ... conductive film, 16 ... lower electrode, 17 ... dielectric film, 17A ... silicon nitride film, 17B ... Silicon oxide film, 18: upper electrode, 19: M
ISFET, 20: capacitive element, WL: word line, DL ...
Data line.

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device having a capacitive element in which a lower electrode, a dielectric film, and an upper electrode are sequentially laminated, wherein a chlorine atom concentration is 2 × 10 ¹³ [atom].
s / cm ² ] or more of the silicon nitride film is formed, and thereafter, an oxidation treatment is performed to form a silicon oxide film on the surface of the silicon nitride film to form a dielectric film. A method for manufacturing a semiconductor integrated circuit device. 2. A method of manufacturing a semiconductor integrated circuit device having a capacitive element in which a lower electrode, a dielectric film, and an upper electrode are sequentially laminated, wherein a lower electrode made of a silicon film doped with impurities is formed. And a step of removing an oxide film formed on the surface of the lower electrode, and forming a silicon nitride film having a chlorine atom concentration of 2 × 10 ¹³ [atoms / cm ² ] or more on the surface of the lower electrode. And then performing an oxidation process to form a silicon oxide film on the surface of the silicon nitride film to form a dielectric film, and an upper electrode comprising a silicon film doped with impurities on the surface of the dielectric film. Forming a semiconductor integrated circuit device. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the silicon nitride film is formed by a chemical vapor deposition method using dichlorosilane and ammonia.