JPH1027040A - Computer resetting system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of a failure even when resetting operation is erroneously performed (a reset button is pressed) by performing a system stopping process and preserving necessary information. SOLUTION: When a reset button 11 is pressed, the software of a computer receives system resetting information 31 and performs a system stopping process (T5) and stops software processing by turning off a reset inhibit flag 13. When the flag 13 is turned off, a system-reset signal 26 is outputted to reset the computer. On the other hand, a forcible reset timer 12 constituted of hardware is set at time longer than the time required for performing the system stopping process and, when the reset button 11 is pressed, the timer is started. When the above-mentioned set time has elapsed, system resetting is executed by outputting the reset signal 26 regardless of whether or not the system stopping process is completed (the rest inhibiting flag 13 is turned on).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system reset method for a computer, and more particularly to a system reset method capable of cooperating with software stop processing (system stop processing) such as shutdown processing of an application program and an operating system specific to a system. About.

[0002]

2. Description of the Related Art In an industrial computer system, an application and an operation program unique to the system are operating, and an application program for controlling the system, a device controlled by the program, and an operation system are used when the operation of the computer is stopped. The system has a predetermined system stop processing procedure such as file storage or storage of data being processed.

In an industrial computer system,
It has a hardware system reset function. As this system reset function, hardware reset of a computer system and hardware reset of a control device connected to the computer are performed.

In the conventional industrial computer, "software stop processing (system stop processing)" for stopping software and "system reset processing" for stopping and resetting a hardware system are separate functions. There was no link between these functions.

FIG. 7 shows a conventional configuration. In FIG.
Reference numeral 11 denotes a reset button, and a signal from the reset button 11 is directly used as a system reset signal 26.

Next, the operation will be described. (1) In software processing, when the system is started (S1), (2) the "reset prohibition flag is turned ON" (S2), and (3) normal application program processing is performed (S3).

(4) When performing the system stop processing, the system stop processing is started by software or, depending on the type of computer, a shutdown signal is input (S
4), (5) System S / W
(Application) stop processing and OS stop processing (shutdown processing) are executed (S5).

(6) Set “reset prohibition flag OFF” (S6), and (7) Stop software processing (S6)
7). (8) On the other hand, by pressing the reset button 11,
The system reset signal 26 is transmitted regardless of the progress of the software processing, and the computer is reset.
Thus, there was no relation between the software processing and the system reset signal 26.

[0009]

As described above, in the prior art, since there is no relation between the software processing and the system reset signal, the operator may erroneously reset the system without performing a system stop processing such as a shutdown processing. In such a case, the file management information was not saved correctly, and there was a possibility of causing a serious failure.

Also, some types of industrial computers have a function of saving various information unique to the computer during the stop processing, and when the system is reset during the system stop processing, the information stored in the memory is stored. Had the potential to destroy various types of information.

According to the present invention, a reset operation (such as reset button input) is erroneously requested due to a malfunction of a reset signal (button) of an industrial computer by linking a reset signal (button) with a stop process by software. However, the present invention provides a system reset method that does not lead to a failure.

[0012]

[Means for Solving the Problems]

(1) A reset method for a computer according to the present invention is a reset method for performing a system reset of a computer, the method comprising a normal reset means, a forced reset means, and a timer, wherein the normal reset means executes the normal processing of the computer. When a system reset command is received, the system performs predetermined system stop processing, and then performs a system reset of the computer. The timer is set to be equal to or longer than the system stop processing time, and a timer activated by the system reset command is provided. The forced reset means is means for performing a system reset of the computer when the timer is activated by the system reset command and the set time is reached, regardless of whether or not the system stop processing is completed. It is.

(2) A reset method for resetting the system of a computer comprises a normal reset means, a forced reset means, and a timer, wherein the normal reset means issues a system reset command while the computer is executing normal processing. Upon receiving the predetermined system stop processing, the system resets the computer and sends a command to change the reset time of the timer according to the progress of the system stop processing. The timer is set to be longer than the system stop processing time, is started by the system reset command, and is a timer for changing the set time according to the reset time change command. The forced reset means is that the timer is started by the system reset command. At the time set above, the system stop processing is completed Regardless of whether, in which the means for performing a system reset of the computer.

(3) Further, in the above (1) or (2), an emergency reset means for resetting the system of the computer after a predetermined time has passed from the system reset command is provided.

(4) A reset command delay sending means for sending a system reset command when the system reset operation is continued for a predetermined time is provided, and this system reset command is used as the system reset command of (1) or (2). Things.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a block diagram of this embodiment. FIG. 2 is a timing chart of signals in the case of a normal stop. FIG. 3 is a timing chart of signals when the operation is stopped by the forced reset timer.

In FIG. 1, 11 is a reset button, 12 is a forced reset timer, and 13 is a reset prohibition flag.

The reset button 11 is used to start a reset process. When the reset button 11 is pressed, a software reset is notified 31 to the software process, and a forced reset timer activation signal 32 is used to reset the forced reset timer 1.
2 is turned ON.

The forced reset timer 12 has an appropriate set time until the system reset processing is forcibly executed when the system stop processing is not normally completed, and is forcibly reset by the forced reset timer start signal 32 to start ON. A forced reset timer signal 22 that is turned off when the time is up is output.

Note that the time-up time of the forced reset timer 12 is set to be equal to or longer than the system stop processing, and it may take several tens of seconds to several minutes, and in some cases, more than 10 minutes.

The reset prohibition flag 13 is a flag indicating a reset prohibition period during software operation. The reset prohibition flag 13 is turned on by a reset prohibition flag ON signal 33 when software processing is started, and is turned on by a reset prohibition flag OFF signal 34 before software processing is stopped. It is turned off.

41 is a flip-flop, 42 is a NAND
The circuit 43 is an AND circuit.

Next, the operation will be described. (1) In software processing, when the system is started (T1), (2) the "reset prohibition flag is turned on" (T2), and (3) normal application program processing (FIG. 2B) is performed (T3).

(4) When performing the system stop processing, the reset button 11 is depressed (FIG. 2A), a system reset notification is issued, and the system stop processing in software is started or a shutdown signal is inputted depending on the computer model. (T4).

(5) System stop processing (FIG. 2b) is executed (T5), (6) "reset prohibition flag OFF" (FIG. 2c, T6), and (7) software processing is stopped (T7).

(8) On the other hand, when the reset button 11 is pressed, the system reset signal 26 is sent out to reset the computer system (FIGS. 2g and 2b). To explain the operation of this system reset,

(1) Reset button 11 in system operating state
When the button is pressed, as a normal normal process, after the system stop processing in the software processing (FIG. 2B), the reset prohibition flag 13 is turned off by the reset prohibition flag OFF signal 34, and the reset prohibition flag signal 23 is turned off (FIG. 2C).

(2) The forced reset timer signal 22 is ON
In this state, when the reset prohibition flag signal 23 is turned off, the reset permission signal 25 is turned on (FIG. 2E). (3) On the other hand, when the reset button 11 is pressed, the flip-flop 41 outputs a latch and outputs the reset holding signal 24 (FIG. 2f).

(4) The system reset signal 26 is output from the AND circuit 43 in response to the reset permission signal 25 and the reset hold signal 24 (FIG. 2G), and the computer is reset (FIG. 2B).

The case where the stop processing is not normally completed in software will be described with reference to the timing chart of FIG. (1) By the time the forced reset timer 12 times out,
If the reset prohibition flag is not turned off, the forced reset timer signal 22 is turned off by the time-up of the forced reset timer 12 (FIG. 3D).

(2) The reset permission signal 25 of the NAND circuit 42 is turned ON (FIG. 3E), and (3) The system reset signal 26 is output from the AND circuit 43 in response to the reset permission signal 25 ON and the reset holding signal 24 (FIG. 3).
g), the computer is system reset (FIG. 3b).

When the reset prohibition flag 13 is OFF and the system is stopped, (1) the reset permission signal 25
Is ON and reset is permitted, so (2)
When the reset button 11 is pressed, the reset holding signal 25
N, and the system reset signal 26 is output without software processing and timer processing.

As described above, in the first embodiment,
For industrial computers that require system stop processing such as application stop processing and operation software shutdown processing, (1) In software, the reset prohibition flag 13 is turned on when the system is started, and the system is stopped when a reset request is input By starting the process and having the function to turn off the reset prohibition flag when the system stop process is completed, the system can be reset without performing the system stop process such as the shutdown process even if the reset operation is requested by mistake. To prevent.

(2) The hardware is provided with a forced reset timer 12 which is activated by a reset request and measures a preset time, and activates a system reset by turning off a reset prohibition flag or time-out of the forced reset timer. By doing so, even if a reset operation is erroneously requested while the system is operating, it is possible to prevent the system from being reset without performing the shutdown process.

(3) Even if the system stop processing is not normally completed by software, the system can be forcibly reset in any case by forcibly resetting the system by the expiration of the forced reset timer 12. .

Embodiment 2 FIG. 4 is a block diagram of the second embodiment. 4, the same reference numerals as those in FIG. 1 of the first embodiment denote the same parts, and a description thereof will be omitted.

In the figure, a forced reset timer 51
An appropriate set time is set as an initial setting value until the reset process is forcibly executed when the system stop process does not end normally. Also, during the system stop processing in the software processing, when the forced reset timer reset signals 35 and 36 which are the reset value update command are received,
The set time is sequentially changed by the instruction. Then, it is turned on by the forced reset timer start signal 32 and outputs a forced reset timer signal 22 which is turned off when the set time comes and turns off.

In the software processing, when the system reset notification signal 31 is received during the normal processing, the system stop processing is performed. In the present embodiment, the forced reset timer value is set during the system stop processing (steps U5, U7, U9). Read / write and change function (steps U6, U
8).

That is, in the software processing, after the system stop processing 1 (step U5) and the system stop processing 2 (step U7), the reset value is updated (step U6).
U8), the forced reset timer reset signal 1 (3
5) And the reset timer reset signal 2 (36) is output to change the set value of the forced reset timer 51.

Thus, the set value of the forced reset timer 51 can be reset to a value as small as possible.
The change of the set time of the forced reset timer 51 will be described with a specific example.

Generally, the stop processing time of the system S / W is as follows.
It varies greatly depending on the operation status of the system.
Suppose that it takes several minutes (for example, 8 minutes) to save many files accidentally at the time of stoppage, although it ends in minutes. Assuming that the OS stop time is 1 minute, the timer setting is 8 minutes + 1 minute + margin (1 minute) = 10 minutes.

Actually, the operation is stopped at about "1-2 minutes + 1 minute = 3 minutes". If there is no function to change the set time, there is a problem in the stop of the OS, and if the S / W does not stop normally, the OS is stopped by the 10-minute timer. If there is a function to change the set time, after the system S / W is finished in 2 minutes, if the OS is stopped and the margin is reset to 2 minutes, even if the OS does not stop normally, the reset button is pressed. It can be stopped 4 minutes after pressing. That is, it takes 10 minutes, but can be stopped in 4 minutes.

The reset value update will be described in a concrete example. System stop processing 1 normal 1 minute maximum 4 minutes System stop processing 2 normal 1 minute maximum 4 minutes OS stop processing 1 minute

(1) First, 10 minutes is set (initial setting of a timer) with 4 + 4 + 1 + 1 (margin) = 10. (2) At the end of the system stop process 1, the remaining processes are “system stop process 2” and “OS stop process”, so 4 + 1 + 1 (margin) = 66 minutes is set.

(3) At the end of the system stop processing 2, the remaining processing is "OS stop processing", so that 1 + 1 (margin) = 22 minutes is set. The above is a fixed setting example. However, it is also possible to calculate the time by measuring the size and the number of files that need to be processed, and to derive the set time of the timer based on the time.

The transmission of the system reset signal 26 by the operation of the logic circuit shown in FIG. 4 is the same as that of the first embodiment, and the description is omitted.

As described above, in the second embodiment,
In addition to the effects of the first embodiment, the software processing is provided with a timer value updating function of a forced reset timer, and the value of the timer value is changed at the end of a certain processing after the system stop processing is started in the software processing, so that a more granularity can be obtained. It is possible to set a detailed forced stop time.

Accordingly, the timer value set in the forced reset timer 51 is set to a value obtained by estimating the time until the end of the system stop processing with a margin in the initial setting, but the margin is re-estimated as the processing proceeds. It is possible.

In general, as the processing progresses, the margin is re-estimated to be smaller and the value of the forced reset timer is changed, so that the time until the forced reset in the case where the subsequent stop processing does not normally stop is performed. Can be reduced.

In the software processing, when the time until the end of the system stop processing is estimated to be larger than the forced reset timer value, the stop processing by the software is continued by resetting the timer value. Thus, forced reset during software processing can be prevented.

Embodiment 3 FIG. 5 is a block diagram of the third embodiment. FIG. 6 is a timing chart of the emergency system reset operation. 5 is different from FIG. 1 of the first embodiment in that an on-delay timer 44 and an O
An R circuit 45 is provided so that an emergency system reset can be performed before the system reset by the forced reset timer 51.

Next, the operation of the emergency reset will be described. (1) When the reset button 11 is pressed for more than the ON delay time of the ON delay timer 44 (FIG. 6A), (2) The ON delay timer 44 outputs the emergency reset signal 27 when the ON delay time comes, and the OR circuit 45 After that, the system reset signal 26 is output (FIG. 6B). (3) On the other hand, if the pressing time of the reset button 11 is shorter than the ON delay time of the ON delay timer 44 (FIG. 6)
a) Since the on-delay timer 44 does not output a signal (FIG. 6B), the reset button 11 shown in FIG.
Performs the same operation as the reset operation by pressing.

In the third embodiment, in addition to the effect of the first aspect, it is possible to urgently input a reset signal by continuously pressing the reset button for a predetermined time. Therefore, if a system reset is required for some reason during the system stop processing, which is usually expected to take a long time of several minutes to tens of minutes, this function can be used for an emergency reset.

Embodiment 4 This embodiment is intended to prevent the operator from stopping the system by erroneously operating the reset button. When the operator intentionally stops the system, the operator can press the reset button for a set time or longer. It is.

FIG. 7 is a block diagram of the fourth embodiment. FIG. 8 is a timing chart of signals in the case of a normal stop. FIG. 9 is a timing chart of signals when the operation is stopped by the forced reset timer.

FIG. 7 differs from the first embodiment in that an on-delay timer 44, a reset button signal lock circuit 46, and an OR circuit 47 are provided.

The operation characteristics of the on-delay timer 44 are the same as those of the on-delay timer 44 of the third embodiment, and are the same as those of FIG. 6, but in this embodiment, the output is not the system reset signal 26 but The output is the drive input 32 of the forced reset timer 32. The system reset notification 31 in the software processing 31 The input 20 to the OR circuit 47.

Next, the operation will be described. First, in the normal processing: (1) In the system operating state, the reset button 11 is pressed, and if the pressed time is less than the delay time of the on-delay timer 44, the on-delay timer 44 does not operate, and the computer performs the normal processing ( T3) is being executed.

(2) In the system operating state, the reset button 11 is depressed, and if the depressed time is longer than the delay time of the on-delay timer 44 (FIG. 8A), the on-delay timer 44 is turned on (FIG. 8B). And output the above. (3) The output 20 of the on-delay timer 44 is latched by the flip-flop 41 via the OR circuit 30 and becomes the reset holding signal 24 (FIG. 8G).

(4) On the other hand, the forced reset timer signal 22 of the forced reset timer 12 and the reset prohibition flag signal 23 perform the same operation as that of the first embodiment shown in FIG. That is, as shown in FIG. 8, all the operations are performed with a delay of the ON delay time, and the operations after the delay are the same as those in FIG.

Further, in the forced reset processing, as shown in FIG. 9, all operations are performed with a delay of the ON delay time, and the operation after the delay is the same as the operation of the first embodiment shown in FIG. Therefore, the description is omitted.

As described above, the reset process is not executed unless the reset button 11 is pressed for the ON delay time or longer.

Next, a case where the system is not operating in software processing will be described. (1) Since both the forced reset timer signal 22 and the reset prohibition flag signal 23 are OFF, the reset permission signal 25 is ON. (2) The input from the reset prohibition flag to the reset button signal lock circuit 46 is the reset prohibition flag signal 2
3 is turned ON because it is inverted.

(3) On the other hand, when the reset button 11 is pressed, the output 29 of the reset signal lock circuit 46 is turned on regardless of the pressing time, and
0, the flip-flop 41 latches and turns on the reset holding signal 24, and the system reset signal 26
Is sent and the computer is reset.

In the fourth embodiment, in addition to the effect of the first embodiment, when the reset operation (reset button 11 is pressed) for less than a predetermined time during the operation of the system, the reset operation is performed for a predetermined time without performing the reset processing. In the case, it has a function to start reset processing for the first time. This makes it possible to prevent the system from being stopped due to an erroneous reset operation, and to allow the operator to intentionally stop the system by continuing the reset operation for a set time.

Embodiment 5 The emergency system reset method according to the third embodiment can be applied to a case where the set time of the forced reset timer according to the second embodiment is changed according to the progress of the system stop processing. In this case, the on-delay timer 44 and the OR circuit 45 of the third and fifth embodiments are provided in FIG. 4 of the second embodiment.

Embodiment 6 FIG. The method of starting the system reset operation when the system reset operation is continued for a predetermined time by pressing the reset button according to the fourth embodiment is based on the case where the set time of the forced reset timer according to the second embodiment is changed according to the progress of the system stop processing. It can be applied to In this case, the ON delay timer 44, the reset button signal lock circuit 46, and the OR circuit 47 are provided in FIG. 4 of the second embodiment in FIG.

Embodiment 7 In the above-described embodiment, an industrial computer has been described, but the present invention can be applied to computers other than industrial computers. Further, in the above-described embodiment, a hardware timer has been described, but hardware and software are not limited as long as the timer is installed separately from a computer.

[0068]

【The invention's effect】

(1) As described above, according to the present invention, even if a reset operation is erroneously requested during the operation of the system, the system is prevented from being reset without performing the system stop processing. If the system stop processing does not end normally,
By forcibly resetting the system by the expiration of the forced reset timer, the system can be reliably reset.

(2) Since the reset time of the forced reset timer is changed according to the progress of the system stop processing, finer setting of the forced stop time is possible, and efficient forced reset can be performed. . In addition, a forced reset corresponding to the system stop processing time can be performed.

(3) Since the emergency system reset means is provided, the system can be reset irrespective of the processing state of the software.

(4) Since the system reset command is not output unless the system reset operation is continued for a predetermined time, it is possible to prevent a system reset due to an erroneous reset operation.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a reset method of a computer according to a first embodiment of the present invention.

FIG. 2 is a timing chart of an operation in a case of a normal stop according to the first embodiment of the present invention.

FIG. 3 is a timing chart of an operation when stopping by a forced reset timer according to the first embodiment of the present invention;

FIG. 4 is a configuration diagram showing a reset method of a computer according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram showing a reset method of a computer according to a third embodiment of the present invention.

FIG. 6 is a timing chart of the operation according to the third embodiment of the present invention.

FIG. 7 is a configuration diagram showing a reset method of a computer according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart of an operation when stopping by a forced reset timer according to a fourth embodiment of the present invention;

FIG. 9 is a configuration diagram showing a reset method of a computer according to a fourth embodiment of the present invention.

FIG. 10 is a configuration diagram showing a conventional computer reset method.

[Explanation of symbols]

11 reset button, 12 forced reset timer, 13
Reset prohibition flag, 21 reset button signal, 22 forced reset timer signal, 23 reset prohibition flag signal, 24 reset hold signal, 25 reset permission signal, 26 system reset signal, 27 emergency reset signal, 28 normal reset signal, 31 system reset notification Signal, 32 forced reset timer start signal, 33
Reset disable flag ON signal, 34 Reset disable flag OFF signal, 35 Force reset timer reset signal 1, 36 Force reset timer reset signal 2, 41 Flip-flop circuit, 42 NAND circuit, 43 AN
D circuit, 44 on-delay timer, 45 OR circuit,
46 reset button signal lock circuit, 51 forced reset timer.

Claims (4)

[Claims] 1. A reset system for performing a system reset of a computer, comprising a normal reset unit, a forced reset unit, and a timer, wherein the normal reset unit receives a system reset command while the computer is executing a normal process. After performing a predetermined system stop processing, as a means for performing a system reset of the computer, the timer is set to be longer than the system stop processing time, a timer started by the system reset command, the forced reset means, A computer resetting means for resetting the computer when the timer is started by the system reset command and the set time is reached, irrespective of whether the system stop processing is completed or not. . 2. A reset method for performing a system reset of a computer, comprising a normal reset means, a forced reset means, and a timer, wherein the normal reset means receives a system reset command while the computer is executing a normal process. Means for performing a system reset of the computer after performing a predetermined system stop process, and sending a command to change a reset time of the timer according to a progress state of the system stop process; The timer is set to be longer than the time, and is started by the system reset command, and a timer for changing the set time in response to the reset time change command is provided. At the set time, whether the system stop processing is completed or not However, a computer reset method characterized in that the computer is a means for resetting the system. 3. The computer reset method according to claim 1, further comprising an emergency reset means for resetting the computer system when a predetermined time elapses from a system reset command. 4. A reset command delay sending means for sending a system reset command when a system reset operation is continued for a predetermined time, wherein the system reset command is the system reset command according to claim 1 or 2. Computer reset method.