JPH10270281A - Laminated ceramic capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form dielectric layers which are free of deformations due to piezoelectricity and relax stresses due to piezoelectric deformation by connecting adjacent ones of some internal electrodes to one and the same external electrode, and connecting adjacent ones of the other internal electrodes to different external electrodes, respectively. SOLUTION: Adjacent electrodes 2C, 2D of internal electrodes are connected to a second external electrode 4B, and adjacent ones 2A, 2B, 2E, 2F of the other internal electrodes are connected to an external electrode 4A or the external electrode 4B, respectively. Thus, a structure wherein one dielectric layer 3A sandwiched between the same poles and two sets of two dielectric layers 3B sandwiched between different poles, placed below and above the dielectric layer 3A, respectively are laminated, is obtained. The dielectric layer 3A sandwiched between the same poles is uniformly placed between the dielectric layers 3B sandwiched between the different poles, so that its effect of relaxing stresses due to piezoelectric deformation can be obtained uniformly across the laminated ceramic capacitor 1. As a result, the problems of deterioration and breakdown due to repeated charging and discharging is eliminated and superior durability is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic ceramic capacitor, and more particularly to a monolithic ceramic capacitor capable of preventing deterioration and destruction due to repeated charging and discharging.

[0002]

2. Description of the Related Art A multilayer ceramic capacitor is formed by alternately laminating green sheets made of a ferroelectric ceramic composition and internal electrode materials, degreased the laminated body, and firing the laminated body. Electrodes).

FIG. 2 is a sectional view showing a conventional multilayer ceramic capacitor obtained in this manner. A capacitor chip 1 is composed of a plurality of internal electrodes 2 laminated via a dielectric layer 3. The external electrodes 4 (the first external electrode 4A and the second external electrode 4
B) is provided. One end of the internal electrode 2 is electrically connected to one of the external electrodes 4, and the other end is located inside the chip 1.

In the conventional multilayer ceramic capacitor, the internal electrodes 2 are adjacent to each other and have different external electrodes 4.
It is conducting. That is, in FIG. 2, the internal electrodes 2A,
2C and 2E conduct to the second external electrode 4B, and
B, 2D and 2F are electrically connected to the first external electrode 4A.

[0005]

In the conventional multilayer ceramic capacitor, since the ferroelectric ceramic composition forming the dielectric layer 3 has a large piezoelectric property, the two external electrodes 4A,
4B, a voltage is applied between the internal electrodes 2 and 2B.
The dielectric layer 3 made of the ferroelectric ceramic composition sandwiched between 2 deforms due to the piezoelectricity. In particular, when the device is used in an environment where charging and discharging are severe, the deformation is repeated, and thus the dielectric layer 3 made of the ferroelectric ceramic composition is deteriorated. May be reached.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multilayer ceramic capacitor which solves the above-mentioned conventional problems, suppresses the deformation of the dielectric layer due to piezoelectricity, and prevents deterioration and destruction due to repeated charging and discharging.

[0007]

According to the present invention, there is provided a multilayer ceramic capacitor comprising a capacitor chip having a plurality of internal electrodes laminated via a dielectric layer inside, and a pair of end faces provided with external electrodes. In the multilayer ceramic capacitor in which the internal electrodes are electrically connected to one of the external electrodes, some of the internal electrodes are adjacent to each other and are electrically connected to the same external electrode, and the other internal electrodes are adjacent to each other. It is characterized in that they are electrically connected to different external electrodes.

[0008] Among adjacent internal electrodes, the dielectric layer sandwiched between the internal electrodes connected to the same external electrode does not undergo deformation due to piezoelectricity. In the present invention, of the dielectric layers sandwiched between adjacent internal electrodes, a dielectric layer that does not undergo such deformation due to piezoelectricity is formed, and stress due to piezoelectric deformation is relaxed by this dielectric layer. To prevent deterioration and destruction due to repeated charging and discharging.

In the following, of adjacent internal electrodes, a dielectric layer sandwiched between internal electrodes connected to the same external electrode is referred to as a “dielectric layer sandwiched between the same electrodes”, and a different external electrode is used. The dielectric layer sandwiched between the internal electrodes that have been electrically connected to each other is referred to as a “dielectric layer sandwiched between different electrodes”.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the multilayer ceramic capacitor of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of the multilayer ceramic capacitor of the present invention. In FIG. 1, members having the same functions as those shown in FIG. 2 are denoted by the same reference numerals.

In the illustrated multilayer ceramic capacitor, the internal electrodes 2C and 2D are electrically connected to the second external electrode 4B adjacent to each other, and the other internal electrodes 2A, 2B, 2E and 2 are connected.
F is such that adjacent ones are electrically connected to different external electrodes 4A or 4B, so that two dielectric layers 3B sandwiched between different poles above and below a single dielectric layer 3A sandwiched between the same poles. It has a laminated structure.

In the present invention, the number of dielectric layers sandwiched between the same poles and the arrangement thereof are not particularly limited. One layer or two or more layers are provided according to the number of stacked layers. If the number of dielectric layers sandwiched between the same poles is too small, the effect of relaxing the stress of piezoelectric deformation cannot be obtained sufficiently.However, since the portion of the dielectric layer sandwiched between the same poles does not contribute to the capacitor function, excessive When the number of dielectric layers sandwiched between the same poles is increased, the capacitor characteristics are inferior to the number of stacked dielectric layers, which is not preferable.

The dielectric layers sandwiched between the same poles are provided in a uniform arrangement between the dielectric layers sandwiched between different poles so that the stress relaxation effect of the piezoelectric deformation can be obtained uniformly over the entire multilayer ceramic capacitor. Therefore, as shown in FIG. 1, when a single dielectric layer 3A sandwiched between the same poles is provided, the dielectric layer 3A sandwiched between the same poles is provided at the center in the stacking direction of the dielectric layers. It is preferable that the dielectric layers 3B sandwiched by the same number of different poles be stacked vertically. Also, in the case where two dielectric layers sandwiched between the same poles are provided, the number of dielectric layers sandwiched between different poles disposed on the first dielectric layer sandwiched between the same poles may be reduced. The number of dielectric layers sandwiched between different poles disposed between the dielectric layer sandwiched between the first same pole and the dielectric layer sandwiched between the second same pole; It is preferable that the number of dielectric layers sandwiched between different poles disposed below the dielectric layer sandwiched between the poles is substantially the same.

The thickness of the dielectric layer sandwiched between the different poles may be the same as the thickness of the dielectric layer sandwiched between the same poles. By making the dielectric layer sandwiched between the different poles thicker, it is possible to obtain an even greater stress relaxation effect of piezoelectric deformation. In this case, the thickness of the dielectric layer sandwiched between the same poles is preferably set to 1 to 10 times the thickness of the dielectric layer sandwiched between different poles.

In such a laminated ceramic capacitor of the present invention, when laminating green sheets on which internal electrodes are printed, the green sheets are laminated so that a dielectric layer sandwiched between the same electrodes is formed at a predetermined position. By doing so, it can be easily produced according to a conventional method.

[0017]

The present invention will be described more specifically with reference to examples and comparative examples, but the present invention is not limited to the following examples unless it exceeds the gist.

In the following Examples and Comparative Examples,
The production and evaluation of the multilayer ceramic capacitor were performed as follows.

PbO, La ₂ O ₃ , ZrO, TiO ₂ ,
MgO and WO ₃ were used as starting materials, mixed at a predetermined ratio, calcined and pulverized to obtain a ferroelectric ceramic composition having the following composition.

Pb _0.92 La _0.08 Zr _0.57 Ti _0.25 (Mg
_1/2 W _{1/2) 0.05} O _{3 Using} this ferroelectric porcelain composition, a green sheet is prepared according to a conventional method, and an Ag / Pd internal electrode is formed by printing, and then laminated, degreased and fired to form a capacitor. A chip was manufactured, and silver / palladium = 9/1 external electrodes were formed on the chip to obtain a multilayer ceramic capacitor.

With respect to the obtained multilayer ceramic capacitor, a charging current of 30 A and a discharging current of 50 V were applied at a voltage of 400 V.
A repeatedly charge and discharge with A, 10 times, 100 times, 100 times
After 0 times, 10000 times, and 50000 times of charging and discharging, the capacitance and the insulation resistance were measured, and the capacitance was 10 times smaller than the initial value.
%, Or when the insulation resistance was 10,000 MΩ or less, it was determined to be deteriorated, and the number of deteriorated samples out of 50 samples was examined.

In each of the examples and comparative examples, the number of dielectric layers sandwiched between different poles was 16. Also,
The thickness of the dielectric layer sandwiched between the different poles is 50 μm.
And the dimensions of the capacitor chip are 3.2 mm x 2.5 m
m × 1.4 mm.

The area of each of the internal electrodes is 2.8 m.
m × 1.9 mm, and the overlapping length of the internal electrodes (for example, the length of L in FIG. 3A) was 2.4 mm.

EXAMPLE 1 As shown in FIG. 3A, a multilayer ceramic capacitor having one dielectric layer sandwiched between the same poles and eight dielectric layers sandwiched between different poles above and below the same is formed. And Note that the thickness of the dielectric layer sandwiched between the same poles was set to 50 μm.

Embodiment 2 As shown in FIG. 3B, two dielectric layers sandwiched between the same poles are provided, five dielectric layers sandwiched between different poles, and a dielectric layer sandwiched between the same poles The laminated structure was composed of one layer, six dielectric layers sandwiched between different poles, one dielectric layer sandwiched between the same poles, and five dielectric layers sandwiched between different poles. The thickness of the dielectric layer sandwiched between the same poles was 50 μm.

Example 3 In Example 1, the thickness of the dielectric layer sandwiched between the same poles was 2
The same operation was performed except that the thickness was set to 00 μm and the thickness was made larger than the other layers.

Example 4 In Example 2, the thickness of the dielectric layer sandwiched between the same poles was 1
The same operation was performed except that the thickness was set to 00 μm and the thickness was made larger than the other layers.

Comparative Example 1 As shown in FIG. 3C, 16 dielectric layers sandwiched between different poles were provided without providing the dielectric layers sandwiched between the same poles.

Table 1 shows the evaluation results of Examples 1 to 4 and Comparative Example 1.

[0030]

[Table 1]

From Table 1, it can be seen that by providing a dielectric layer sandwiched between the same poles, it is possible to prevent deterioration due to repeated charging and discharging, and to increase the thickness of the dielectric layer sandwiched between the same poles. By doing so, it can be seen that a more excellent effect can be obtained.

[0032]

As described above in detail, according to the present invention, there is provided a multilayer ceramic capacitor which has no problem of deterioration and destruction due to repeated charging and discharging and has excellent durability.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of a multilayer ceramic capacitor according to the present invention.

FIG. 2 is a sectional view showing a conventional multilayer ceramic capacitor.

FIG. 3A is a schematic diagram showing the internal electrode arrangement of the capacitor chip of the multilayer ceramic capacitor manufactured in Example 1, and FIG. 3B is a diagram of the capacitor chip of the multilayer ceramic capacitor manufactured in Example 2. FIG. 3C is a schematic diagram showing the internal electrode arrangement, and FIG. 3C is a schematic diagram showing the internal electrode arrangement of the capacitor chip of the multilayer ceramic capacitor manufactured in Comparative Example 1.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Capacitor chip 2, 2A, 2B, 2C, 2D, 2E, 2F Internal electrode 3 Dielectric layer 3A Dielectric layer sandwiched between the same poles 3B Dielectric layer sandwiched between different poles 4, 4A, 4B External electrodes

Claims (1)

[Claims] An external electrode is provided on a pair of end surfaces of a capacitor chip in which a plurality of internal electrodes are laminated via a dielectric layer, and the internal electrode is electrically connected to one of the external electrodes. In the laminated ceramic capacitor, some of the internal electrodes are adjacent to each other and are electrically connected to the same external electrode, and other internal electrodes are adjacent to each other and are electrically connected to different external electrodes. A multilayer ceramic capacitor characterized by the following.