JPH10269185A - Barrier synchronization method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed barrier synchronization method by reducing the probability that barrier synchronization encounters timer interruption, by synchronizing the timing of the timer interruption generation of all calculation units on parallel computers. SOLUTION: In the parallel computers, timer interruption synchronization control parts 109 are provided on the respective calculation units and the timer interruption synchronization control parts 109 periodically perform the barrier synchronization among all the calculation units and set an interruption setting register 117 immediately after the barrier synchronization is established. Also, the generation scheduled time of a timer interruption processing is stored in timer interruption synchronization information 112, and in the timer interruption processing, the difference of the time of the actual timer interruption processing and the generation scheduled time is calculated and an interval timer is reset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a barrier synchronization method in a parallel computer.

[0002]

2. Description of the Related Art In a parallel computer, barrier synchronization is well known as a means for synchronizing between computation units. The barrier synchronization is used when a parallel program operating on each computing unit reaches a synchronization point, and provides a function of synchronizing all the computing units where the parallel program exists. That is, it waits for the parallel programs on all the related computing units to reach the synchronization point and issue the barrier synchronization, and resumes processing when all the computing units issue the barrier synchronization. As described above, since barrier synchronization affects the processing of a plurality of calculation units, it is necessary to have high performance, and a method has been proposed in which synchronization between the calculation units can be performed at high speed by dedicated hardware. Kai Hwang "ADVANCED COMP
UTER ARCHITECTURE ”pp365-3
According to No. 67, a method is shown in which each calculation unit has a register for barrier synchronization and the registers are connected to each other by an AND circuit. According to this method, when each calculation unit writes to the register, the result is immediately reflected in the register on each calculation unit. However, there is no mention of the processing until reaching the barrier synchronization point in each calculation unit.

Further, in the case of barrier synchronization realized by hardware, all the computation units in a parallel computer must participate in barrier synchronization, and there is a limit to the number of barrier synchronizations in which one computation unit can simultaneously participate. There are many restrictions on use conditions. For this reason, barrier synchronization by software, in which communication is performed between calculation units participating in barrier synchronization, is often used. In the barrier synchronization by software, the synchronization point arrival notification is collected using the communication means, and when all the synchronization point arrival notifications can be collected, the synchronization completion notification is transmitted to each barrier synchronization participation calculation unit again using the communication means. A method is used. In this case, in order to execute the processing in parallel, a virtual tree structure is constructed between the barrier synchronization calculation units, and a synchronization point arrival notification is collected and a synchronization completion notification is transmitted along the tree structure.

[0004]

As described above, in the barrier synchronization, all the other computing units wait until the participating computing units issue the barrier synchronization.
Therefore, if there is at least one calculation unit that delays issuing barrier synchronization, the barrier synchronization waiting time in other calculation units will increase. It is often a parallel program that runs on a computing unit that issues barrier synchronization, and the parallel program runs on an OS resident on the computing unit. In order for the OS to provide services such as timeout processing, each computing unit normally generates a timer interrupt periodically. When a timer interrupt occurs, the OS temporarily suspends execution of the user program and executes timer interrupt processing. If a timer interrupt occurs immediately before a parallel program executes barrier synchronization on a certain computation unit, barrier synchronization issuance in that computation unit will be delayed by the timer interrupt processing, and as a result, in another computation unit. Barrier synchronization waiting time increases. Conventionally, a timer interrupt is only generated periodically on each calculation unit, and generation of a synchronization between the calculation units has not been considered. For this reason, in the process of waiting between a plurality of calculation units such as barrier synchronization, as the number of calculation units participating in barrier synchronization increases, the probability of a timer interrupt occurring in any one of the calculation units increases. .

In the case where barrier synchronization is realized by software using communication, if transmission of a synchronization completion notification is performed along a tree structure, the reception time of the synchronization completion notification varies among the calculation units. In order to improve the performance of the parallel program, it is necessary to make the processing time in each calculation unit equal, and such a variation is not preferable. Further, in a calculation unit corresponding to a leaf node having a tree structure, a synchronization completion notification arrives with the latest delay, so that the waiting time for barrier synchronization increases.

An object of the present invention is to provide a high-speed barrier synchronization method by synchronizing the timing of occurrence of timer interrupts of all the computation units on a parallel computer, thereby reducing the probability of barrier synchronization encountering a timer interrupt. Is the thing.

Another object of the present invention is to use a broadcast for the synchronization point completion notification, thereby minimizing the time from when all the computation units reach the synchronization point to when execution is resumed, and at high speed. It is an object of the present invention to provide a barrier synchronization method which has the same simultaneity that all the computing units resume processing at the same time.

[0008]

According to the present invention, there is provided timer interrupt synchronizing means for synchronizing the timing of timer interrupt generation of all the computing units in a parallel computer by periodically using barrier synchronization.

Further, according to the present invention, there is provided a timer interrupt synchronizing means for changing a set value of an interval timer according to a deviation of an execution time of a timer interrupt process from a scheduled time.

Further, according to the present invention, there is provided a barrier synchronizing means for collecting a synchronization point arrival notification hierarchically using one-to-one communication and for synchronizing completion notification using broadcast communication.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

(Prior Art) Prior to the description of the embodiment of the present invention, the details of the prior art will be described with reference to FIGS.

FIG. 2 shows a parallel computer constructed by connecting computing units 201, 202 and 203 having the same configuration via a network 204. Calculation unit 20
1 has a processor 205, an interval timer 206, and a memory 208, and an OS 208 resides in the memory. The interval timer 206 has a function of interrupting the processor 205 with a timer when a specified time has elapsed. When the processor 205 receives the timer interrupt,
The currently executing process is temporarily suspended, and the interrupt process 21 in the OS 208 is interrupted.
After executing 0, the interrupted processing is resumed. In the interrupt processing 210, a timer interrupt is periodically generated in the processor 205 to set a constant value in the interval timer 206. According to the prior art, the calculation unit 20
In each of 1, 202, and 203, a timer interrupt occurs periodically, but the time at which the timer interrupt occurs is not synchronized between the calculation units. Even if they are synchronized at a certain timing, if the processor is in the interrupt disabled state when a timer interrupt occurs, the start time of the interrupt processing will be delayed, so the next timer interrupt time of the computation unit will be delayed. As a result, the synchronization of the timer interrupt time is lost.

FIG. 3 shows that the timer interrupt time is calculated by the calculation unit 2.
It is a figure explaining the influence of not being synchronized among 01, 202, and 203.

FIG. 3 shows the calculation units 201, 202, 2
03 shows the flow of processing of each calculation unit when the parallel program 209 is loaded into each memory and executed. The parallel program 209 includes a calculation 211, a barrier synchronization 212, a calculation 213, a barrier synchronization 214, and a calculation 2
The process proceeds in the order of 15.

In FIG. 3, a timer interrupt occurs during execution of the calculation 211 in the calculation unit 201. After execution of the timer interrupt processing 301, the execution of the calculation 211 is resumed. In addition, the calculation unit 203 restarts the execution of the calculation 213 after the timer interrupt occurs during the execution of the calculation 213 and the timer interrupt processing 304 is executed. Calculation unit 201
Then, the barrier synchronization 212
Is delayed until the barrier synchronization completion time 305, and as a result, the calculation units 202 and 203 wait for synchronization 303 and 30.
4 occurs. In the calculation unit 203, the execution of the barrier synchronization 214 is delayed until the barrier synchronization completion time 306 due to the timer interrupt processing 304. As a result, the calculation units 201 and 203 generate synchronization waits 307 and 308.

As described above, if at least one calculation unit delays the start of barrier synchronization due to the timer interrupt processing, the barrier synchronization waiting time of the other calculation units increases. Since the time of the interrupt processing 304 is shifted, the barrier synchronization 21
2 and barrier sync 214 are both affected.

The problem with the prior art is that, since the time of the timer interrupt is not synchronized between the calculation units, the probability that the timer interrupt processing will occur in any one of the calculation units with the increase in the number of calculation units. Is increased, and as a result, the probability that the barrier synchronization waiting time is increased is increased.

(Embodiment 1) Next, an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 shows the overall configuration of a parallel computer to which the present invention is applied. The parallel computer is configured by connecting the calculation units 101, 102, and 103 via a network 113. The calculation unit 101 is a processor 10
4. It has an interval timer 105, a memory 106, and a communication control unit 114. Calculation units 102, 103
Has a similar configuration.

The interval timer 105 is a real time counter 11 that counts up in synchronization with a machine cycle.
6. This real time counter 116 is the processor 1
04, the processor 104 can read the real-time counter 116 at any two points and find the difference between them, so that the absolute elapsed time can be known. Further, the interval timer 105 can set a timer interrupt time interval using the interrupt setting register 117. When the time set in the interrupt setting register 117 elapses, the interval timer 105 sets the processor 104.
Interrupt the timer. Upon receiving the timer interrupt, the processor 104 interrupts the current process and executes the timer interrupt process. When the timer interrupt process ends, the processor 104 continues the interrupted process. In the timer interrupt processing, the interrupt setting register 117 is reset so that the timer interrupt occurs again. The processor 104 has a state as to whether or not to accept a timer interrupt. If a timer interrupt occurs in a state in which the timer interrupt is not accepted, execution of the timer interrupt processing can accept the timer interrupt. Pending until it becomes

An OS 107 resides in the memory 106.
The OS 107 includes therein an interrupt processing program 115 to be executed at the time of a timer interrupt, and a timer interrupt synchronization control unit 109 and a barrier synchronization control unit 108 which are features of the present invention.

The barrier synchronization control unit 108 has barrier synchronization information 110 which is information such as a range of barrier synchronization, and a reception area 111 for notification data used in barrier synchronization.

The timer interrupt synchronization control section 109 has timer interrupt synchronization control information 112.

The timer interrupt synchronization process is basically performed by the timer interrupt synchronization control unit 109 in the timer interrupt process. The processing performed by the timer interrupt synchronization control unit includes an interval timer simultaneous setting processing for simultaneously setting an interval timer on all calculation units, and an interval timer correction processing for each calculation unit correcting the interval timer set value. One.

In order to perform these processes, the timer control unit 109 uses the timer interrupt synchronization control information shown in FIG. The timer interrupt time 801 is a scheduled time at which the next timer interrupt will occur in the calculation unit 101. The simultaneous setting time 802 is a scheduled time for performing the simultaneous setting process. The simultaneous setting interval 803 is a time interval for performing the simultaneous setting process. The timer interrupt interval 804 is a time interval for generating a timer interrupt. The simultaneous setting interval 803 and the timer interrupt interval 804 are predetermined fixed values, and the same value is used in all the calculation units. Also, the calculation unit 101
The time used by the timer interrupt synchronization control unit is a local time calculated inside the calculation unit 101 using the real time counter 116, and this time always coincides with other calculation units in the parallel computer. No need.

FIG. 5 shows the flow of the timer interrupt synchronous process in the timer interrupt process. First, in step 501, the simultaneous setting time 113 is compared with the current time, and it is checked whether the current time is after the simultaneous setting time 113.

If the current time has passed the simultaneous setting time 113, the simultaneous setting processing is performed in step 502, and if the current time has not passed the simultaneous setting time 113,
In step 503, an interval timer correction process is performed.

FIG. 6 shows details of the interval timer simultaneous setting process 502. First, step 601
Then, barrier synchronization between all the calculation units is performed. Immediately after the barrier synchronization is completed, an interval timer setting process is performed in step 602. Here, the value set for the interval timer uses the timer interrupt interval 804. Since all the calculation units set the same value in the interval timer immediately after the completion of the barrier synchronization, the next timer interrupt is completed in all the calculation units. Next, in step 603, the simultaneous set time is updated. This is a time obtained by adding the simultaneous setting interval 803 to the current time. Finally, step 604
To update the timer interrupt time. This time is a time obtained by adding the timer interrupt interval 804 to the time when the interval timer is set. The interval timer simultaneous setting process is performed not only in the timer interrupt process but also when the parallel computer is started.

FIG. 7 shows an interval timer correction process 50.
4 is a detail. First, in step 701, a value SET_VAL to be set in the interval timer is calculated. The current time is NOW_TIME and the timer interrupt time 801 is PRE_
Assuming that TIME and the timer interrupt interval 804 are INTERVAL, the value is obtained by the following formula: SET_VAL = INTERVAL- (NOW_TIME-PRE_TIME) --- (1) The reason why SET_VAL is not set to a fixed value but is calculated by the formula (1) is as follows. When the interval timer 105 interrupts the processor 106 with the timer, the processor 106 is in the timer interrupt disabled state,
If the start of the timer interrupt processing is delayed, the time for setting the interval timer is delayed by the delay of the start of the timer interrupt processing. If a fixed value is always set at this time, the next timer interrupt generation timing will be delayed from the other calculation units by the delay of the timer interrupt processing start. Therefore, the value set in the interval timer is set to INTE by the delay of the start of the timer interrupt processing as shown in equation (1).
Subtract from RVAL. When step 701 ends, next, in step 702, SET_VAL is set in the interval timer. Finally, at step 703, the timer interrupt time 80
1 is changed to a time obtained by adding SET_VAL to the time at which the interval timer is set.

If it is known that the deviation of the timer interrupt processing start time due to the timer interrupt prohibition hardly affects the barrier synchronization time, step 503 is executed.
It is not necessary to perform the interval timer correction processing described above, but only to set a fixed timer interrupt interval 804 in the interval timer 117.

The interval timer described here is based on the premise that once a timer interrupt is generated, it is necessary to set the interrupt setting register 117 again to generate the next timer interrupt. However, an interval timer that continuously generates a timer interrupt at the set timer interrupt interval may be used. In this case, the interval timer correction process in the timer interrupt synchronization process is unnecessary.

By using the above method, it becomes possible to synchronously generate the timer interrupts of all the calculation units inside the parallel computer. By executing the barrier synchronization in this state, it is possible to minimize the influence of the timer interrupt processing on the synchronization waiting time of the barrier synchronization.

The parallel program 2 used in the description of the prior art
FIG. 9 shows the flow of processing in the case where S.09 is executed by the parallel computer of FIG. 1 using the present invention. According to the present invention, the occurrence of the timer interrupt is synchronized between all the calculation units. Accordingly, in each of the calculation units 101, 102, and 103, a timer interrupt occurs at the same time, and the timer processing 401, 4
02 and 403 are executed simultaneously. Therefore, the timer interrupt processing affects only the barrier synchronization 212 completed at the barrier synchronization completion time 404, and the synchronization waiting 408 of each of the calculation units 101 and 103 in the barrier synchronization 214.
407 is not affected. The calculation units 101, 1
02 and 103 execute the timer interrupt processing at the same time.
06 and 409 are less affected than the prior art.

(Embodiment 2) Next, as Embodiment 2, a method of performing barrier synchronization between arbitrary calculation units will be described. According to the barrier synchronization method of the present invention, the synchronization point arrival notification from all the barrier synchronization participation calculation units is transmitted on a one-to-one basis.
The communication is hierarchically collected using communication, and the synchronization completion notification is performed by broadcast communication. Hereinafter, this embodiment will be described with reference to FIGS. 1 and 9 to 14.

In FIG. 1, barrier synchronization control section 108
Creates a hierarchical structure for collecting synchronization point arrival notifications using the barrier synchronization information 110, and collects synchronization point arrival notifications in one calculation unit based on this hierarchical structure.
FIG. 9 shows a binary tree 1001 as an example of this hierarchical structure. Each node of the binary tree 1001 corresponds to a computation unit participating in barrier synchronization. Each computing unit participating in barrier synchronization creates the same binary tree, so that the parent-child relationship between all the computing units participating in barrier synchronization can be uniquely determined. The calculation unit corresponding to each node of the binary tree 1001 is a calculation unit corresponding to all the child nodes of the own calculation unit (hereinafter, referred to as a child calculation unit).
, And when all of them are received, a synchronization point arrival notification is transmitted to a calculation unit (hereinafter, referred to as a parent calculation unit) corresponding to the parent node of the self-calculation unit. A calculation unit corresponding to the root node of the binary tree 1001 (hereinafter, referred to as a root calculation unit)
When receiving the synchronization point arrival notification from the calculation units corresponding to all of the child nodes, it broadcasts a synchronization completion notification to all the calculation units. All the barrier synchronization participation calculation units know the completion of the barrier synchronization by receiving the synchronization completion notification.

The one-to-one communication and the broadcast communication with other calculation units are provided by the communication control unit 114. The barrier synchronization control unit 108 uses the barrier synchronization information 110 to determine a communication method to be used with the calculation unit at the communication destination, and transmits the notification data using the communication control unit 114. The notification data received from the other calculation unit is transmitted to the communication control unit 11.
4 is written to the notification data receiving area. The communication performed by the communication control unit 114 can be realized by using, for example, the communication system of Japanese Patent Application Laid-Open No. HEI 6-110845 previously filed by the present applicant.

In the barrier synchronization according to the present invention, synchronization can be performed between a plurality of calculation units. A set of the plurality of calculation units is called a barrier synchronization group. Each calculation unit in the parallel computer can participate in a plurality of barrier synchronization groups. Therefore, the barrier synchronization control unit 108 holds the barrier synchronization information and the notification data reception area corresponding to each barrier synchronization group.

FIG. 10 shows the contents of the barrier synchronization information 110. The barrier synchronization information 110 is a set of barrier synchronization group information 1104. Barrier synchronization group information 11
04 is a barrier synchronization GR 1101, a barrier synchronization ID 110
2. It is composed of a calculation unit list.

The barrier synchronization GR 1101 is an identifier of the barrier synchronization group, and the barrier synchronization ID 1102 is an identifier of each barrier synchronization and a calculation unit list when the barrier synchronization is executed a plurality of times in the same barrier synchronization group.
It is a list of all the computation units included in the same barrier synchronization group.

FIG. 11 shows the configuration of the notification data receiving area 111. The notification data reception area is divided in units of barrier synchronization groups, and the position of the same barrier synchronization group from the head of the notification data reception area is ensured to be the same on all calculation units. The notification data reception area for each barrier synchronization group includes a synchronization completion notification data reception area 1201 and a synchronization point arrival notification data reception area 1202, 1203. Synchronization point arrival notification data reception areas 1202, 120
Reference numeral 3 denotes an area for receiving synchronization point arrival notification data from a child calculation unit of the own calculation unit, and a synchronization completion notification data reception area 1201 is an area for receiving synchronization completion notification data broadcast by the route calculation unit. . The number of the synchronization point arrival notification reception areas differs depending on the hierarchical structure used for collecting the synchronization point arrival notification. In the present embodiment, the number of synchronization point arrival notification reception areas is two because a binary tree is used. However, in general, when collecting synchronization point arrival notifications using an N-ary tree, N synchronization point arrival notifications are used. A reception area is provided.

FIG. 12 shows a format of the notification data written in the notification data receiving area 111. The notification data is composed of two fields, a barrier synchronization GR field 1301 and a barrier synchronization ID field 1302. The barrier synchronization GR field 1301 contains the barrier synchronization GR 110
1 is stored in the barrier synchronization ID field 1302, and the value of the barrier synchronization ID 1102 is stored in the barrier synchronization ID field 1302. As described above, the communication control unit 114 writes the received data directly in the notification data receiving area. Therefore, the barrier synchronization control unit 108
Is that the values of the barrier synchronization GR field 1301 and the barrier synchronization ID field 1302 are respectively the barrier synchronization GR 1101
And that the value is equal to the value of the barrier synchronization ID 1102 by a spin loop, thereby knowing that the notification data has been received.

FIG. 13 shows a flow of processing of the barrier synchronization control unit 108.

First, it is checked in step 1401 whether or not the initialization of the barrier synchronization group that is currently being processed has been completed. If the initialization has not been completed, step 1402 is performed, and then step 14
Go to 03. If the initialization has been completed, step 1403 proceeds directly to step 1403.

In step 1402, an initialization process is performed. In the initialization processing, a binary tree 1001 is created using the calculation unit list 1103, and the child calculation unit and the parent calculation unit of the self calculation unit are obtained. In the initialization process, the barrier synchronization ID 1102 is set to 1.

In step 1403, it is checked whether or not a child calculation unit of the self-calculation unit exists. If no child calculation unit exists, the process proceeds to step 1405.
If it has a child calculation unit, it proceeds to step 1405 after executing step 1404.

Step 1404 is processing for waiting for reception of a synchronization point arrival notification. As described above, the reception confirmation of the synchronization point arrival notification is performed in the synchronization point arrival notification receiving area 1202, 1203.
The value of the barrier synchronization GR field 1301 is equal to the barrier synchronization GR 1101 in the barrier synchronization information, and the barrier synchronization is performed.
This is performed by performing a spin loop until the value of the ID field 1302 becomes equal to the value of the barrier synchronization ID 1102. The reception confirmation of the synchronization point arrival notification is executed for the synchronization point arrival notification data reception areas from all the child calculation units.

Upon receiving the synchronization point arrival notification from all the child calculation units, it is checked in step 1405 whether the own calculation unit has a parent calculation unit. If there is a parent calculation unit, steps 1406, 1407, 1
409 is executed to end the barrier synchronization processing. If there is no calculation unit, the own calculation unit is a root calculation unit. In this case, steps 1408 and 1409 are executed, and the barrier synchronization processing ends.

Step 1406 is processing for notifying the parent computing unit of the synchronization point arrival notification data. The barrier synchronization GR 1101 and the barrier synchronization ID 110 in the barrier synchronization information 110
The notification data shown in FIG. 12 is created using the value of 2, and transmitted to the parent calculation unit using the communication control unit 114.

Step 1408 is a process of waiting for reception of a synchronization completion notification. In this process, similarly to the synchronization point arrival notification data reception waiting process, the value of the barrier synchronization GR field 1301 of the synchronization completion notification reception area 1201 is equal to the barrier synchronization GR 1101 in the barrier synchronization information, and the value of the barrier synchronization ID field 1302 is This is performed by performing a spin loop until the value becomes equal to the value of the barrier synchronization ID 1102.

Step 1407 is a synchronization completion notifying process. Similar to the synchronization point arrival notification processing, the barrier synchronization GR1101
The notification data shown in FIG. 12 is created using the value of the barrier synchronization ID 1102 and the value of the barrier synchronization ID 1102, and transmitted to all calculation units using the communication control unit 114.

Step 1409 is a process for updating the barrier synchronization information. Here, the barrier synchronization ID 1102 is incremented for use in the next barrier synchronization.

[0052]

As described above, according to the present invention,
By synchronizing the timer interrupts of all the calculation units in the parallel computer, the barrier synchronization performance can be improved.

Further, according to the present invention, when performing barrier synchronization between arbitrary calculation units, it is possible to provide high-speed and highly-synchronous barrier synchronization by using broadcast for the synchronization completion notification.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a parallel computer to which the present invention is applied.

FIG. 2 is a diagram showing a configuration of a parallel computer using a conventional technique.

FIG. 3 is a diagram showing execution of a parallel program using a conventional technique.

FIG. 4 is a diagram showing execution of a parallel program using the present invention.

FIG. 5 is a diagram illustrating a flowchart of a timer interrupt synchronization process.

FIG. 6 is a diagram showing a flowchart of an interval timer simultaneous setting process.

FIG. 7 is a diagram illustrating a flowchart of an interval timer correction process.

FIG. 8 is a diagram showing timer interrupt synchronization control information.

FIG. 9 is a diagram showing a binary tree.

FIG. 10 is a diagram showing barrier synchronization information.

FIG. 11 is a diagram showing a notification data receiving area.

FIG. 12 is a diagram showing a notification data format.

FIG. 13 is a diagram showing a flowchart of barrier synchronization processing.

[Explanation of symbols]

101, 102, 103, 201, 202, 203: calculation unit, 113, 204: network, 106,
207: memory, 105, 206: interval timer, 104, 205: processor, 114: communication control unit, 108: barrier synchronization control unit, 110: barrier synchronization information, 111: notification data reception area, 109: timer interrupt synchronization control Part, 112: timer interrupt synchronization control information, 11
5, 210: interrupt processing program

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yukihiro Akiyama 5030 Totsukacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Software Development Division, Hitachi, Ltd. (72) Inventor Kazuma Tobe 5030 Totsukacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Address Co., Ltd. Software Development Division, Hitachi, Ltd.

Claims (13)

[Claims] 1. A plurality of calculation units are connected by a network, each of said plurality of calculation units is capable of obtaining information capable of calculating an absolute elapsed time, a memory, a processor, and the same when a set time elapses. In a parallel computer having an interval timer that causes an interrupt in a processor in a computing unit, a timer interrupt that occurs in each of the computing units is synchronized by all of the computing units, and any one of the plurality of computing units is A barrier synchronization method characterized in that synchronization is performed. 2. The method according to claim 1, wherein the timer interrupt synchronization barrier synchronization is performed between all of the computation units, and each of the all computation units performs the timer interrupt synchronization. 2. The barrier synchronization method according to claim 1, wherein the same interrupt occurrence interval value is set in the interval timer immediately after the barrier synchronization is established, and the interval timer is reset when a timer interrupt occurs. . 3. A method of resetting an interval timer upon occurrence of a timer interrupt in the timer interrupt synchronization according to claim 2, wherein a scheduled timer interrupt occurrence time is stored, and when the timer interrupt occurs, the timer interrupt generation is performed. A value calculated using the difference between the time and the stored scheduled timer interrupt occurrence time and the interrupt occurrence interval value is set in the interval timer,
3. The barrier synchronization method according to claim 2, further comprising using a method of updating a scheduled timer interrupt occurrence time. 4. The timer according to claim 3, wherein the timer interrupt occurrence scheduled time is a time obtained by adding a value set in the interval timer to a time set in the interval timer. Barrier synchronization method. 5. A value to be set in the interval timer according to claim 3, wherein a difference between the timer interrupt occurrence time and the stored scheduled timer interrupt occurrence time is subtracted from the interrupt occurrence interval value. The barrier synchronization method according to claim 3 or 4, wherein: 6. The method according to claim 2, wherein the same interrupt occurrence interval value is set in an interval timer when resetting the interval timer upon occurrence of a timer interrupt in timer interrupt synchronization. 2. The barrier synchronization method according to 2. 7. The barrier synchronization method according to claim 2, wherein the barrier synchronization for timer interruption synchronization is performed when the parallel computer is started. 8. The barrier synchronization method according to claim 2, wherein the barrier synchronization for timer interruption synchronization is performed at a constant barrier synchronization time interval for timer interruption synchronization. 9. The barrier synchronization for timer interrupt synchronization according to claim 8, wherein the scheduled execution time of the barrier synchronization for timer interrupt synchronization is stored, and when a timer interrupt occurs, the timer interrupt occurrence time is set to the timer interrupt time. When the scheduled synchronization barrier synchronization execution time has passed, barrier synchronization for timer interrupt synchronization is performed. Immediately after the completion of the barrier synchronization for timer interrupt synchronization, the barrier synchronization completion time for timer interrupt synchronization and the fixed timer interrupt 9. The barrier synchronization method according to claim 8, wherein a time obtained by adding the barrier synchronization time interval value for interruption synchronization is updated as a scheduled execution time of barrier synchronization for timer interruption synchronization. 10. A plurality of computing units connected by a network, each of said plurality of computing units having a memory,
In a parallel computer having a processor and communication means for communicating with another calculation unit, each of the barrier synchronization participation calculation units holds barrier synchronization information and notifies that the barrier synchronization participation calculation unit has reached a synchronization point. Is collected in one calculation unit based on the barrier synchronization information, and when the synchronization point arrival notifications from all the barrier synchronization participating units can be collected in the one calculation unit, the one calculation unit broadcasts a synchronization completion notification. The barrier synchronization method is characterized in that all the barrier synchronization participation units determine the completion of synchronization by receiving the synchronization completion notification by the broadcast. 11. The method according to claim 10, wherein the synchronization point arrival notification is collected in one calculation unit by using the barrier synchronization information to create a tree structure having the one calculation unit as a root. The barrier synchronization method according to claim 10, wherein the collection is performed hierarchically based on a tree structure. 12. The barrier synchronization information according to claim 10, wherein the barrier synchronization information includes at least an identification number of the barrier synchronization and a list of numbers of all the calculation units participating in the barrier synchronization. 11 barrier synchronization methods 13. A method according to claim 1, wherein each of the barrier synchronization participation calculation units holds barrier synchronization information and the barrier synchronization participation calculation unit reaches a synchronization point. The synchronization point arrival notification that notifies the synchronization point arrival notification from all the barrier synchronization participating units can be collected in one calculation unit based on the barrier synchronization information. The barrier synchronization method according to claim 1, wherein the calculation unit broadcasts a synchronization completion notification, and all the barrier synchronization participation units determine the completion of the synchronization by receiving the synchronization completion notification by the broadcast.