JPH1083379A - Parallel computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform barrier synchronous control with a small hardware quantity by controlling barrier synchronism between a process which operates on a local computer and a process which operate on another computer according to a broadcasted job identifier. SOLUTION: A broadcasting means 11 of each computer 1 broadcasts process progress information on the process operating on the computer 1 itself and the identifier of its job to all computers 1 through a communication mechanism 2. A judging means 13a of each computer 1 judges whether or not the broadcasted job identifier is the same as the job that the process operating on the computer 1 belongs to and once it is judged that the broadcasted job identifier is the same with the job, a counting means 13b counts up a count value according to the broadcasted process progress information. Then a determination means 13c judges whether or not the count value reaches a prescribed to judge whether or not a barrier synchronism point is reached, and decides whether or not the process operating on the computer 1 is advanced to a next step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a plurality of computers and a communication mechanism for connecting the computers, and employs a configuration in which one job is divided into a plurality of processes and assigned to the computers. In particular, the present invention relates to a parallel computer system that executes processes allocated in synchronization with a process running on a parallel computer, and more particularly to a parallel computer system that can execute the synchronization process with a small amount of hardware.

A parallel computer system employs a configuration in which one job is divided into a plurality of processes and processed in parallel by a plurality of computers to execute the job at high speed. When executing this parallel processing, each computer executes barrier synchronization control for controlling to proceed to the next step on condition that the process to be processed by another computer has been processed to a certain point.

In order to operate a large number of parallel jobs simultaneously or in a time-division manner, a mechanism for simultaneously processing synchronization between processes in each job is required, and a large amount of hardware is generally required. Therefore, it is necessary to realize the barrier synchronization control with a small amount of hardware.

[0004]

2. Description of the Related Art The present inventor has disclosed a new invention concerning barrier synchronization control of a parallel computer system in Japanese Patent Application Laid-Open No. Hei 7-262142.

As described in Japanese Patent Application Laid-Open No. Hei 7-262142, a maximum of n programs can be executed in parallel in a parallel computer system, and all the programs may be freely allocated to each computer. Then, the execution state of the program in each computer can be represented by n bits when the execution state is indicated by, for example, “in execution / end of execution”.

[0006] Assuming that the number of computers constituting the parallel computer system is m, the execution state of the program in the parallel computer system is represented by nxm bits. Accordingly, the target state of this execution state is also represented by n × m bits, but since each computer may execute at most n programs, each computer manages the target state. That is, it is necessary to provide n registers having a size of n × m bits.

[0007]

As described above, in the conventional parallel computer system, in order to execute the barrier synchronization control, each computer manages the current execution state of the program notified via the communication mechanism. In addition to a status register having a size of n × m bits, a configuration having n mask registers having a size of n × m bits for managing a target state of the execution state is adopted.

Therefore, according to the prior art, there is a problem that a mask register having a large hardware amount of n.times.n.times.m bits must be prepared in order to execute the barrier synchronization control.

To address this problem, it is possible to adopt a configuration in which the amount of hardware is reduced by limiting the method of allocating processes to be allocated to each computer. This is disadvantageous because parallel jobs cannot run at the same time.

The present invention has been made in view of the above circumstances, and has as its object to provide a new parallel computer system capable of executing barrier synchronization control with a small amount of hardware.

[0011]

FIG. 1 and FIG. 2 show the principle configuration of the present invention. In the figure, reference numeral 1 denotes a plurality of computers constituting the parallel computer system of the present invention, and 2 denotes a communication mechanism for connecting the computers 1.

The parallel computer system of the present invention adopts a configuration in which one job is divided into a plurality of processes and assigned to the computer 1, and each computer 1 processes one or a plurality of processes operating on its own computer 1. The progress information is broadcast to all the computers 1 via the communication mechanism 2 and the communication mechanism 2
In accordance with the processing progress information broadcasted via the PC, a process that is allocated is executed while synchronizing with a process that operates on the other computer 1.

The computer 1 of the present invention, whose principle configuration is shown in FIG. 1, comprises a management means 10, a broadcasting means 11, and an addition means 12
, Control means 13, receiving means 14, and instruction means 15
, Reading means 16 and interrupt means 17.

The management means 10 manages processing progress information of a process operating on the computer 1 and an identifier of a job to which the process belongs. The broadcasting unit 11 broadcasts processing progress information of a process operating on the computer 1 and an identifier of a job to which the process belongs, broadcasts processing data and a job identifier, and transmits an interrupt notification and a job identifier. To broadcast. The adding unit 12 adds an operation code indicating the type of the information to the broadcast information broadcast by the broadcasting unit 11.

The control means 13 is prepared in association with the job identifier, and controls the barrier synchronization between the process operating on the own computer 1 and the process operating on the other computer 1 according to the broadcast job identifier. And a determining means 13a / counting means 13b / deciding means 13c. The receiving unit 14 receives information broadcast via the communication mechanism 2. The instruction unit 15 decodes the operation code of the information received by the reception unit 14.

The reading means 16 responds to the instruction from the instruction means 15 and, for example, when the broadcast job identifier is
The processing data received by the receiving unit 14 is read on the condition that the job is the same as the job to which the process that operates in (1) belongs. In response to the instruction from the instruction unit 15, the interruption unit 17 receives the job by the reception unit 14, for example, on condition that the job identifier to be broadcasted is the same as the job to which the process operating on the computer 1 belongs. An interrupt is generated for the CPU in response to the interrupt notification.

In the computer 1 constituting the parallel computer system according to the present invention shown in FIG. 1, the broadcasting means 11 of each computer 1 processes processing information of a process operating on its own computer 1 and its progress information. The job identifier to which the process belongs is broadcast to all the computers 1 via the communication mechanism 2.

In response to the broadcast, the determination means 13a of each computer 1 determines whether or not the broadcast job identifier is the same as the job to which the process running on the computer 1 belongs, and receives the determination result. When it is determined that the broadcast job identifier is the same as the job to which the process operating on the computer 1 belongs, the counting unit 13b counts up the count value according to the broadcast processing progress information. Then, in response to the counting process, the determining means 13c
Determines whether or not the count value of the counting means 13b has reached a specified value (the number of processes) to determine whether or not the barrier synchronization point has been reached. It is determined whether or not to proceed to the step.

At the time of adopting this configuration, the broadcasting means 1
1 may broadcast processing data or an interrupt notification in place of the processing progress information of the process.
Since the adding unit 12 adds the operation code to the broadcast information, the instruction unit 15 receives the operation code to be broadcast and activates the reading unit 16 to read the processing data. Or by activating the interrupt means 17 to execute an interrupt to the CPU.

Thus, in the computer 1 of the present invention whose principle configuration is shown in FIG. 1, for example, when one job is divided into eight processes and the computer 1 performs parallel processing,
The configuration is adopted in which the processing progress information of the process is broadcast together with the job identifier, and the barrier synchronization control is executed by detecting whether or not the processing progress information of reaching the eight barrier synchronization points for the job has been broadcast. With this configuration, barrier synchronization control can be performed with a small amount of hardware.

Then, while executing the barrier synchronization control, it becomes possible to write processing data to another computer 1 or to notify another computer 1 of an interrupt. On the other hand, the computer 1 of the present invention whose principle configuration is shown in FIG. 2 includes a management unit 20, a broadcasting unit 21, an adding unit 22, and a writing unit 2
3, determining means 24, receiving means 25, and instructing means 26
, Reading means 27, and interrupt means 28.

The management means 20 is prepared in association with a process operating on the computer 1, and manages an in-job number indicating a development position of the process in a job and an identifier of the job. And a first register 20a for storing a bit value indicating the process progress information of the process in the bit area and a first register 20a. And a second register means 20b for storing a bit value indicating the presence or absence of a process in a bit area.

The broadcasting means 21 broadcasts the processing progress information of the process operating on the computer 1, the identifier of the job to which the process belongs, and the job number of the process, and transmits the processing data and the job identifier. Broadcast or broadcast an interrupt notification and job identifier. Addition means 22
Adds an operation code indicating the type of information to the broadcast information broadcast by the broadcasting means 21.

The writing means 23 writes the processing progress information to be broadcast in the bit area of the first register means 20a indicated by the broadcast job identifier and the job number. The deciding means 24 includes data stored in the first register means 20a,
By comparing the data stored in the second register unit 20b with the pair, it is determined whether or not to proceed to the next step in the process operating on the own computer 1.

The receiving means 25 receives information broadcast via the communication mechanism 2. The instructing means 26 is
Decrypts the operation code of the received information. The reading unit 27 responds to the instruction of the instruction unit 26, for example, on the condition that the job identifier to be broadcasted is the same as the job to which the process operating on the computer 1 belongs, Read the data for use. Interruption means 28
In response to the instruction from the instruction unit 26, for example, on the condition that the broadcast job identifier is the same as the job to which the process operating on the computer 1 belongs,
In response to the interrupt notification received by the CPU.

In the computer 1 constituting the parallel computer system of the present invention shown in FIG. 2, the broadcasting means 21 of each computer 1 transmits the progress information of the process operating on its own computer 1 and the progress information of the process. Is broadcasted to all the computers 1 via the communication mechanism 2.

In response to the broadcast, the writing means 23 of each computer 1 writes the broadcast processing progress information to the first register means 20a indicated by the broadcast job identifier and the job number. Then, in response to the write result, the determination means 24 determines the data stored in the first register 20a,
By comparing the data stored in the second register unit 20b with the pair, it is determined whether or not the barrier synchronization point has been reached, and whether or not the process operating on the own computer 1 proceeds to the next step is determined. decide.

At the time of adopting this configuration, the broadcasting means 2
1 may broadcast processing data or an interrupt notification in place of the processing progress information of the process.
The adding means 22 adds an operation code to the information to be broadcast. Therefore, the instruction means 26 receives the operation code to be broadcast and activates the reading means 27 to execute the reading of the processing data. Alternatively, an interrupt to the CPU is executed by activating the interrupt means 28.

As described above, in the computer 1 of the present invention whose principle configuration is shown in FIG. 2, for example, when one job is divided into eight processes and the computer 1 performs parallel processing,
The process progress information of the process is broadcasted together with the job number / job identifier, and eight barrier synchronization points for the job are reached using the second register means 20b having a smaller number of bits than in the prior art. By detecting whether or not the processing progress information has been broadcast, barrier synchronization control is executed, so that barrier synchronization control can be executed with a small amount of hardware.

Then, while executing the barrier synchronization control, it becomes possible to write processing data to another computer 1 or to notify another computer 1 of an interrupt.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail according to embodiments. FIG. 3 shows an example of a parallel computer system equipped with the present invention.

The parallel computer system shown in FIG.
Computer 1 indicated by reference numeral 1 and computer 1 indicated by PE2
-2, a computer 1-3 indicated by PE3, and a computer 1-4 indicated by PE4, and employs a configuration in which one job is processed in parallel.

In the following, for convenience of explanation, one job having the job identifier "1234" is divided into eight processes 1 to 8, and as shown in FIG.
And the process 2 are executed, the computer 1-2 executes the processes 3 and 4, and the computer 1-3 executes the processes 5 and 6
And the computer 1-4 executes the process 7 and the process 8 in a parallel processing mode.

The computer 1 constituting the parallel computer system according to the present invention includes processing progress information of a process running on its own computer 1, an identifier of a job to which the process belongs, and a job number of the process (intra-job development). Indicate location)
In order to realize this, the communication mechanism 2 transmits the job identifier (jobid) / in-job number (pid) notified from each computer 1 as shown in FIG.
A configuration is provided that includes a selection circuit 200 that receives processing progress information (state) and transmits it to each computer 1 while selecting it.

FIG. 6 shows an embodiment of the computer 1 constituting the parallel computer system of the present invention. In the figure, 30 is C
PUs 31-i (i = 1 to n) are n barrier synchronization mechanisms provided for executing barrier synchronization control. Here, the n units correspond to the maximum number of processes that may be executed in parallel by one computer 1.

A selection circuit 32 receives a job identifier / in-job number / processing progress information output from each barrier synchronization mechanism 31-i and receives a job output from one of the barrier synchronization mechanisms 31-i. The identifier / in-job number / processing progress information is output to the communication mechanism 2.

Reference numeral 33 denotes a receiving circuit which receives the job identifier / in-job number / processing progress information broadcast from the communication mechanism 2 and notifies it to each barrier synchronization mechanism 31-i; A number indicating circuit, which is used by a process running on the CPU 30 for a barrier synchronization mechanism 31-i.
Is displayed.

A destination selection circuit 35 selects the barrier synchronization mechanism 31-i according to the mechanism number displayed by the mechanism number display circuit 34, and selects the barrier synchronization mechanism 31-i when the CPU 30 changes the process progress information of the process. Barrier synchronization mechanism 31
-i outputs the processing progress information.

Reference numeral 36 denotes a selection circuit, which is a barrier synchronization mechanism 31 according to the mechanism number displayed by the mechanism number display circuit 34.
When the selected barrier synchronization mechanism 31-i outputs a bit value indicating that barrier synchronization has been achieved, the output value is written to a prescribed register of the CPU 30.

Reference numeral 37 denotes an interrupt mask which is configured to manage whether or not to notify the CPU 30 of an interrupt.
When the barrier synchronization mechanism 31-i selects a barrier synchronization mechanism 31-i according to the mechanism number displayed by the mechanism number display circuit 34 and outputs a bit value indicating that barrier synchronization has been achieved, an interrupt notification is issued. When the setting is made, the interrupt is notified to the CPU 30 whether the process using the barrier synchronization mechanism 31-i is in operation or not.

The barrier synchronizing mechanism 31-i holds the job identifier of the process using it and selects the
2 and a selection circuit 3 which holds a job identifier register 40 to be output to the
2, a status register 42 for writing processing progress information notified from the destination selection circuit 35, and a bit area i (i = 1 to 8) having a bit area of 8 bits or more. And a status register 43 that stores a bit value (initial value is all “0”) indicating processing progress information of the process i (i = 1 to 8). A mask that stores a bit value “1” indicating the existence of the process i (i = 1 to 8) in i = 1 to 8) and stores a bit value “0” indicating the absence of the process in other bit areas. By comparing the bit value of the register 44 with the bit value of the status register 43 and the bit value of the mask register 44, it is detected whether or not barrier synchronization has been achieved, and the detection result is sent to the selection circuit 36 / interrupt mask 37. Output A period detection circuit 45, reception circuit 33
And the job identifier register 40
And a writing circuit 46 for writing the processing progress information to be broadcast in the bit area of the status register 43 indicated by the job number received by the receiving circuit 33 when the job identifier held by the receiving circuit 33 matches.

In the following, it is assumed that the number of bits of the status register 43 and the mask register 44 is 16 bits. This means that at the time of actual operation, each of the 16 computers 1 processes one process divided into 16 in parallel,
At the time of debugging, each of the less computer 1
This is because it is assumed that a configuration in which a debug process is executed by performing a plurality of processes in parallel is assumed.

In such a configuration, in order to execute the barrier synchronization control, in the prior art, as described above, a mask register having a size of 16 × n × n bits must be prepared. In contrast, in the present invention, 1
It is sufficient to prepare the mask register 44 having a size of 6 × n bits, so that the amount of hardware can be greatly reduced. Note that the status register 43 needs to have a size of 16 × n bits as in the related art.

Next, the present invention will be described in detail by specifically describing the operation processing of the computer 1 configured as described above. Here, as described with reference to FIG.
One job is divided into eight processes 1 to 8, the computer 1-1 executes the process 1 / process 2, the computer 1-2 executes the process 3 / process 4, and the computer 1-3 executes the process 5 / Execute process 6, and computer 1-4 executes process 7 /
Although a parallel processing mode of executing the process 8 is assumed, as shown in FIGS. 7 and 8, the process 1 uses the barrier synchronization mechanism 31-1 of the computer 1-1, and the process 2 uses the computer. 1-1 uses the barrier synchronization mechanism 31-2 of the computer 1-2, and the process 3 uses the barrier synchronization mechanism 31-1 of the computer 1-2.
The process 4 uses the barrier synchronization mechanism 31-2 of the computer 1-2, the process 5 uses the barrier synchronization mechanism 31-1 of the computer 1-3, and the process 6 uses the barrier synchronization mechanism 31 of the computer 1-3.
It is assumed that the process 7 uses the barrier synchronization mechanism 31-1 of the computer 1-4 and the process 8 uses the barrier synchronization mechanism 31-2 of the computer 1-4.

After the four computers 1-i enter the parallel processing of the processes 1 to 8, first, when the process 3 reaches the barrier synchronization point, as shown in FIG. The selection circuit 35 controls the barrier synchronization mechanism 3 used by the process 3
1-1, the process progress information of the bit value "1" indicating that the barrier synchronization has been reached is written into the status register 42 of the barrier synchronization mechanism 31-1. The selection circuit 32 of the information processing unit 32 transmits the processing progress information “1” written in the status register 42 to the barrier synchronization mechanism 3
Along with the job identifier “1234” / in-job number “3” managed by 1-1, it is broadcast to all the computers 1-i via the communication mechanism 2. Then, the process 3 enters a synchronization waiting state.

Upon receiving this broadcast, as shown in FIG.
Of the barrier synchronization mechanisms 31-i of the computer 1-1, the two barrier synchronization mechanisms 31-1 and 2 having the same job identifier function, and the writing circuit of the two barrier synchronization mechanisms 31-1 and 2 is used. 46
Writes a bit value "1" indicating that the barrier synchronization has been reached in the third bit area of the status register 43 of the two barrier synchronization mechanisms 31-1 and 31-2. Then, as shown in FIG. 9, the barrier synchronization mechanism 31 included in the computer 1-2.
-i, the two barrier synchronization mechanisms 31-1 and 2 having the same job identifier function, and the two barrier synchronization mechanisms 31-2 function.
The two write circuits 46 are provided with two barrier synchronization mechanisms 31-.
A bit value “1” indicating that the barrier synchronization has been reached is written in the third bit area of the status register 43 of 1 or 2.

Then, as shown in FIG.
Among the barrier synchronization mechanisms 31-i of the two, the two barrier synchronization mechanisms 31-1 and 2 having the same job identifier function, and
The write circuit 46 of the two barrier synchronization mechanisms 31-1 and 2
Status register 43 of two barrier synchronization mechanisms 31-1 and 2
A bit value “1” indicating that the barrier synchronization has been reached is written in the third bit area of “1”. Then, as shown in FIG. 12, of the barrier synchronization mechanism 31-i of the computer 1-4,
Two barrier synchronization mechanisms 31-1, 2 having the same job identifier
Functions, the write circuit 46 of the two barrier synchronization mechanisms 31-1 and 2 reaches barrier synchronization in the third bit area of the status register 43 of the two barrier synchronization mechanisms 31-1 and 2 Write a bit value “1” indicating that the operation has been performed.

Subsequently, when the process 5 reaches the barrier synchronization point, as shown in FIG. 14, the destination selection circuit 35 of the computer 1-3 sets the barrier synchronization mechanism 31-1 used by the process 5 to the next.
Is written in the status register 42 of the barrier synchronization mechanism 31-1, and the process progress information of the bit value "1" indicating that the barrier synchronization has been reached is received. Reference numeral 32 denotes the processing progress information “1” written in the status register 42 to the barrier synchronization mechanism 3
Along with the job identifier “1234” / in-job number “5” managed by 1-1, it is broadcast to all the computers 1-i via the communication mechanism 2. Then, the process 5 enters a synchronization waiting state.

Upon receiving this broadcast, as shown in FIG.
The write circuit 4 of the barrier synchronization mechanism 31-1, 2 of the computer 1-1
6 is the status register 4 of the barrier synchronization mechanism 31-1, 2
A bit value “1” indicating that barrier synchronization has been reached is written in the fifth bit area of No. 3. Then, as shown in FIG. 13, the write circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-2 stores the fifth bit area of the status register 43 of the barrier synchronization mechanism 31-1, 2 in the fifth bit area. The bit value “1” indicating that the barrier synchronization has been reached is written. And
As shown in FIG. 14, the barrier synchronization mechanism 31 of the computer 1-3
The write circuit 46 of the -1,2 writes a bit value "1" indicating that the barrier synchronization has been reached in the fifth bit area of the status register 43 of the barrier synchronization mechanism 31-1,2. Then, as shown in FIG. 14, the writing circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-4 has the fifth bit area of the status register 43 of the barrier synchronization mechanism 31-1, 2 stored therein. The bit value “1” indicating that the barrier synchronization has been reached is written.

Subsequently, when the process 1 reaches the barrier synchronization point, as shown in FIG. 15, the destination selection circuit 35 of the computer 1-1 sets the barrier synchronization mechanism 31-1 used by the process 1 to a new state.
Is written in the status register 42 of the barrier synchronization mechanism 31-1, and the process progress information of the bit value "1" indicating that the barrier synchronization has been reached is received. Reference numeral 32 denotes the processing progress information “1” written in the status register 42 to the barrier synchronization mechanism 3
Along with the job identifier “1234” / in-job number “1” managed by 1-1, it is broadcast to all the computers 1-i via the communication mechanism 2. Then, the process 1 enters a synchronization waiting state.

Upon receiving this broadcast, as shown in FIG.
The write circuit 4 of the barrier synchronization mechanism 31-1, 2 of the computer 1-1
6 is the status register 4 of the barrier synchronization mechanism 31-1, 2
In the first bit area of No. 3, a bit value “1” indicating that the barrier synchronization has been reached is written. Then, as shown in FIG. 15, the write circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-2 has the first bit area of the status register 43 of the barrier synchronization mechanism 31-1, 2. The bit value “1” indicating that the barrier synchronization has been reached is written. And
As shown in FIG. 16, the barrier synchronization mechanism 31 of the computer 1-3
The write circuit 46 of the -1,2 writes a bit value "1" indicating that the barrier synchronization has been reached in the first bit area of the status register 43 of the barrier synchronization mechanism 31-1,2. Then, as shown in FIG. 16, the writing circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-4 stores the first bit area of the status register 43 of the barrier synchronization mechanism 31-1, 2 in the first bit area. The bit value “1” indicating that the barrier synchronization has been reached is written.

Subsequently, when the process 6 reaches the barrier synchronization point, as shown in FIG. 18, the destination selecting circuit 35 of the computer 1-3 causes the barrier synchronization mechanism 31-2 used by the process 6 to operate.
Is written in the status register 42 of the barrier synchronization mechanism 31-2, and the process progress information of the bit value "1" indicating that the barrier synchronization has been reached is written. Reference numeral 32 denotes the processing progress information “1” written in the status register 42 to the barrier synchronization mechanism 3
Along with the job identifier “1234” / in-job number “6” managed by 1-2, it is broadcast to all the computers 1-i via the communication mechanism 2. Then, the process 6 enters a synchronization waiting state.

Upon receiving this broadcast, as shown in FIG.
The write circuit 4 of the barrier synchronization mechanism 31-1, 2 of the computer 1-1
6 is the status register 4 of the barrier synchronization mechanism 31-1, 2
A bit value “1” indicating that barrier synchronization has been reached is written in the sixth bit area of No. 3. Then, as shown in FIG. 17, the write circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-2 stores the data in the sixth bit area of the status register 43 of the barrier synchronization mechanism 31-1, 2. The bit value “1” indicating that the barrier synchronization has been reached is written. And
As shown in FIG. 18, the barrier synchronization mechanism 31 of the computer 1-3
The write circuit 46 of the -1,2 writes a bit value "1" indicating that the barrier synchronization has been reached in the sixth bit area of the status register 43 of the barrier synchronization mechanism 31-1,2. Then, as shown in FIG. 18, the write circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-4 has the sixth bit area of the status register 43 of the barrier synchronization mechanism 31-1, 2. The bit value “1” indicating that the barrier synchronization has been reached is written.

Subsequently, when the process 2 reaches the barrier synchronization point, as shown in FIG. 19, the destination selection circuit 35 of the computer 1-1 causes the barrier synchronization mechanism 31-2 used by the process 2 to operate.
Is written in the status register 42 of the barrier synchronization mechanism 31-2, and the processing progress information of the bit value “1” indicating that the barrier synchronization has been reached is written. Reference numeral 32 denotes the processing progress information “1” written in the status register 42 to the barrier synchronization mechanism 3
Along with the job identifier “1234” / in-job number “2” managed by 1-2, it is broadcast to all the computers 1-i via the communication mechanism 2. Then, the process 2 enters a synchronization waiting state.

Upon receiving this broadcast, as shown in FIG.
The write circuit 4 of the barrier synchronization mechanism 31-1, 2 of the computer 1-1
6 is the status register 4 of the barrier synchronization mechanism 31-1, 2
A bit value “1” indicating that barrier synchronization has been reached is written in the second bit area of No. 3. Then, as shown in FIG. 19, the writing circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-2 stores the write data 46 in the second bit area of the status register 43 of the barrier synchronization mechanism 31-1, 2. The bit value “1” indicating that the barrier synchronization has been reached is written. And
As shown in FIG. 20, the barrier synchronization mechanism 31 of the computer 1-3
The write circuit 46 of -1,2 writes a bit value "1" indicating that the barrier synchronization has been reached in the second bit area of the status register 43 of the barrier synchronization mechanism 31-1,2. Then, as shown in FIG. 20, the writing circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-4 has the second bit area of the status register 43 of the barrier synchronization mechanism 31-1, 2. The bit value “1” indicating that the barrier synchronization has been reached is written.

Subsequently, when the process 7 reaches the barrier synchronization point, as shown in FIG. 22, the destination selection circuit 35 of the computer 1-4 makes the barrier synchronization mechanism 31-1 used by the process 7 available.
Is written in the status register 42 of the barrier synchronization mechanism 31-1 and the processing progress information of the bit value “1” indicating that the barrier synchronization has been reached is received. Reference numeral 32 denotes the processing progress information “1” written in the status register 42 to the barrier synchronization mechanism 3
Along with the job identifier “1234” / in-job number “7” managed by 1-1, it is broadcast to all the computers 1-i via the communication mechanism 2. Then, the process 7 enters a synchronization waiting state.

Upon receiving this broadcast, as shown in FIG.
The write circuit 4 of the barrier synchronization mechanism 31-1, 2 of the computer 1-1
6 is the status register 4 of the barrier synchronization mechanism 31-1, 2
A bit value “1” indicating that barrier synchronization has been reached is written in the seventh bit area of No. 3. Then, as shown in FIG. 21, the writing circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-2 has a seventh bit area of the status register 43 of the barrier synchronization mechanism 31-1, 2. The bit value “1” indicating that the barrier synchronization has been reached is written. And
As shown in FIG. 22, the barrier synchronization mechanism 31 of the computer 1-3
The write circuit 46 of -1,2 writes a bit value "1" indicating that barrier synchronization has been reached in the seventh bit area of the status register 43 of the barrier synchronization mechanism 31-1,2. Then, as shown in FIG. 22, the writing circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-4 has a seventh bit area of the status register 43 of the barrier synchronization mechanism 31-1, 2. The bit value “1” indicating that the barrier synchronization has been reached is written.

Subsequently, when the process 4 reaches the barrier synchronization point, as shown in FIG. 23, the destination selecting circuit 35 of the computer 1-2 changes the barrier synchronization mechanism 31-2 used by the process 4
Is written in the status register 42 of the barrier synchronization mechanism 31-2, and the processing progress information of the bit value "1" indicating that the barrier synchronization has been reached is written. Reference numeral 32 denotes the processing progress information “1” written in the status register 42 to the barrier synchronization mechanism 3
Along with the job identifier “1234” / in-job number “4” managed by 1-2, it is broadcast to all the computers 1-i via the communication mechanism 2. Then, the process 4 enters a synchronization waiting state.

Upon receiving this broadcast, as shown in FIG.
The write circuit 4 of the barrier synchronization mechanism 31-1, 2 of the computer 1-1
6 is the status register 4 of the barrier synchronization mechanism 31-1, 2
A bit value “1” indicating that barrier synchronization has been reached is written in the fourth bit area of No. 3. Then, as shown in FIG. 23, the writing circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-2 stores the fourth bit area of the status register 43 of the barrier synchronization mechanism 31-1, 2 in the fourth bit area. The bit value “1” indicating that the barrier synchronization has been reached is written. And
As shown in FIG. 24, the barrier synchronization mechanism 31 of the computer 1-3
The write circuit 46 of -1,2 writes a bit value "1" indicating that the barrier synchronization has been reached in the fourth bit area of the status register 43 of the barrier synchronization mechanism 31-1,2. Then, as shown in FIG. 24, the write circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-4 has the fourth bit area of the status register 43 of the barrier synchronization mechanism 31-1, 2. The bit value “1” indicating that the barrier synchronization has been reached is written.

Subsequently, when the process 8 reaches the barrier synchronization point, as shown in FIG. 26, the destination selection circuit 35 of the computer 1-4 causes the barrier synchronization mechanism 31-2 used by the process 8 to operate.
Is written in the status register 42 of the barrier synchronization mechanism 31-2, and the process progress information of the bit value "1" indicating that the barrier synchronization has been reached is written. Reference numeral 32 denotes the processing progress information “1” written in the status register 42 to the barrier synchronization mechanism 3
Along with the job identifier “1234” / in-job number “8” managed by 1-2, it is broadcast to all the computers 1-i via the communication mechanism 2. Then, the process 8 enters a synchronization waiting state.
In response to this broadcast, as shown in FIG. 25, the writing circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-1 sets the eighth status register 43 of the barrier synchronization mechanism 31-1, 2 A bit value “1” indicating that the barrier synchronization has been reached is written in the bit area of “1”. Then, as shown in FIG. 25, the write circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-2.
Is the status register 43 of the barrier synchronization mechanism 31-1, 2
A bit value “1” indicating that the barrier synchronization has been reached is written in the eighth bit area of “1”. Then, as shown in FIG. 26, the write circuit 46 of the barrier synchronization mechanism 31-1, 2 of the computer 1-3 stores the data in the eighth bit area of the status register 43 of the barrier synchronization mechanism 31-1, 2. The bit value “1” indicating that the barrier synchronization has been reached is written. Then, as shown in FIG. 26, the barrier synchronization mechanism 31- of the computer 1-4.
The write circuit 46 of 1 and 2 writes a bit value “1” indicating that barrier synchronization has been reached in the eighth bit area of the status register 43 of the barrier synchronization mechanism 31-1 and 2.

As described above, when the processes 1 to 8 reach the barrier synchronization point in the order of “process 3 → process 5 → process 1 → process 6 → process 2 → process 7 → process 4 → process 8,” FIG. 27 and FIG.
As shown in the figure, the status register 43 of each computer 1-i
Is set to "1" in the bit area i (i = 1 to 8) and "0" is set to the other bit areas, whereby the data stored in the status register 43 and the data stored in the mask register 44 are set. Will match, so
The synchronization detection circuit 45 of the barrier synchronization mechanism 31-1, 2 of each computer 1-i determines that all the processes 1 to 8 have reached the barrier synchronization point, and notifies the selection circuit 36 / interrupt mask. 37, and in response, the CPU 30 knows that all the processes 1 to 8 have reached the barrier synchronization point.

As described above, the computer 1-i constituting the parallel computer system of the present invention can execute the barrier synchronization control by using the mask register 44 having a smaller amount of hardware than in the prior art.

In this embodiment, the status register 43
A configuration is employed in which all the processes 1 to 8 have reached the barrier synchronization point by using the / mask register 44, but which of the processes 1 to 8 has reached the barrier synchronization point. When you do not need to know whether or not, by counting the processing progress information using a simple counter,
It is also possible to adopt a configuration in which barrier synchronization control is executed by determining whether all processes 1 to 8 have reached the barrier synchronization point.

Further, in the parallel computer system, the computer 1
For -i, a small amount of data, such as a search end notification, may be transmitted to another computer 1-i. Further, there is a case where an interrupt is desired to be notified to another computer 1-i.

In order to cope with such a request, in the parallel computer system of the present invention, as shown in FIG. 29, the computer 1-i has a job identifier (jobid) / in-job number (pid).
In addition to a mode for transmitting processing progress information (state), a mode for transmitting a job identifier (jobid) / small amount of data and a mode for transmitting a job identifier (jobid) / interrupt notification are prepared. A configuration is adopted in which a unique operation code is assigned to a.

Then, each computer 1 is provided with an operation code decoding mechanism 60, and the operation code broadcast by using the operation code decoding mechanism 60 is used to transmit the transmission information transmitted from the other computer 1-i in any transmission mode. When it is determined whether the transmission mode is the transmission mode of the job identifier (jobid) / in-job number (pid) / processing progress information (state), the barrier mechanism 61 having the above-described configuration is activated. ,
When it is determined that the transmission mode is the job identifier (jobid) / small data transmission mode, the data reading mechanism 62 that executes a process of writing the transmitted small data to a prescribed memory area is started, and the job identifier ( When it is determined that the mode is the transmission mode of (jobid) / interrupt notification, a configuration is adopted in which the interrupt notification mechanism 63 that executes a process of notifying the CPU of an interrupt is activated.

Here, when adopting this configuration, when a specific job identifier is broadcast, a configuration is adopted in which a small amount of data is read regardless of the job identifier, or an interrupt is notified regardless of the job identifier. It is also possible to take.

[0068]

As described above, according to the parallel computer system of the present invention, a plurality of parallel jobs can run at the same time, one job is divided into a plurality of processes, and each process is freely provided to each computer. When performing parallel processing by allocating, barrier synchronization control can be executed with a smaller amount of hardware than before.

While executing the barrier synchronization control, it becomes possible to write processing data to another computer or to notify another computer of an interrupt.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a principle configuration diagram of the present invention.

FIG. 3 is an example of a parallel computer system.

FIG. 4 is an example of a parallel processing mode of a process.

FIG. 5 is an explanatory diagram of processing of a communication mechanism.

FIG. 6 is an example of a computer.

FIG. 7 is an explanatory diagram of a process using a barrier synchronization mechanism.

FIG. 8 is an explanatory diagram of a process using a barrier synchronization mechanism.

FIG. 9 is an operation explanatory diagram of the embodiment.

FIG. 10 is a diagram illustrating the operation of the embodiment.

FIG. 11 is an operation explanatory diagram of the embodiment.

FIG. 12 is an operation explanatory diagram of the embodiment.

FIG. 13 is an operation explanatory diagram of the embodiment.

FIG. 14 is an operation explanatory diagram of the embodiment.

FIG. 15 is a diagram illustrating the operation of the embodiment.

FIG. 16 is a diagram illustrating the operation of the embodiment.

FIG. 17 is an operation explanatory diagram of the embodiment.

FIG. 18 is an operation explanatory diagram of the embodiment.

FIG. 19 is an operation explanatory diagram of the embodiment.

FIG. 20 is a diagram illustrating the operation of the embodiment.

FIG. 21 is an operation explanatory diagram of the embodiment.

FIG. 22 is a diagram illustrating the operation of the embodiment.

FIG. 23 is a diagram illustrating the operation of the embodiment.

FIG. 24 is a diagram illustrating the operation of the embodiment.

FIG. 25 is an operation explanatory diagram of the embodiment.

FIG. 26 is an operation explanatory diagram of the embodiment.

FIG. 27 is a diagram illustrating the operation of the embodiment.

FIG. 28 is a diagram illustrating the operation of the embodiment.

FIG. 29 is an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Computer 2 Communication mechanism 10 Management means 11 Broadcast means 12 Addition means 13 Control means 13a Judgment means 13b Counting means 13c Determination means 14 Receiving means 15 Instruction means 16 Reading means 17 Interrupting means 20 Management means 20a First register means 20b 2 register means 21 broadcasting means 22 adding means 23 writing means 24 determining means 25 receiving means 26 indicating means 27 reading means 28 interrupting means

Claims (9)

[Claims] 1. A configuration in which a plurality of computers and a communication mechanism for connecting the plurality of computers are connected to each other, wherein one job is divided into a plurality of processes and assigned to the computers, and each computer operates on its own computer. The process progress information of one or a plurality of processes is broadcast to all the computers via the communication mechanism, and the process progress information broadcasted via the communication mechanism is allocated while synchronizing with a process operating on another computer in accordance with the process progress information. In a parallel computer system that executes a process to be executed, each computer broadcasts an identifier of a job to which a process operating on the computer belongs, together with processing progress information of the process. Having control means for controlling barrier synchronization between an operating process and a process operating on another computer, Parallel computer system with butterflies. 2. The parallel computer system according to claim 1, wherein the control means is prepared in association with the job identifier, and determines whether the broadcast job identifier is the same as the job identifier to which the process operating on the own computer belongs. Determining means for determining whether or not the job identifier is the same;
A counting means for counting up the count value in accordance with the broadcasted processing progress information; and determining whether or not the count value of the counting means has reached a prescribed value, to advance the process operating on the own computer to the next step. Determining means for determining whether or not the parallel processing is performed. 3. A configuration in which a plurality of computers and a communication mechanism for connecting the plurality of computers are connected, and one job is divided into a plurality of processes and assigned to the computers, and each computer operates on its own computer. The process progress information of one or a plurality of processes is broadcast to all the computers via the communication mechanism, and the process progress information broadcasted via the communication mechanism is allocated while synchronizing with a process operating on another computer in accordance with the process progress information. In a parallel computer system that executes a given process, each computer is prepared in association with a process that runs on its own computer, and manages an in-job number indicating a development position of the process in a job and an identifier of the job. Has at least a bit area corresponding to the number of processes of the job, and stores a bit value indicating processing progress information of the process in the bit area. Management means having first register means for performing processing, and second register means provided in association with the first register means for storing a bit value indicating the presence / absence of a process in a bit area; A broadcasting unit that broadcasts an in-job number and a job identifier of a process operating on a computer together with processing progress information of the process; and a bit area of the first register unit indicated by the broadcast job identifier and the in-job number. Writing means for writing the processing progress information to be broadcasted; and comparing the data stored in the first register means with the data stored in the second register means forming a pair,
Determining means for determining whether to proceed to the next step in a process operating on the own computer, a parallel computer system characterized by comprising: 4. The parallel computer system according to claim 3, wherein a serial number is used as an intra-job number, and the same serial number is assigned to a bit area of the first register means. Parallel computer system. 5. The parallel computer system according to claim 1, wherein the broadcasting means has a function of broadcasting processing data in addition to broadcasting processing progress information, and a broadcast job. A parallel computer system comprising: a reading unit that reads broadcast processing data when an identifier is the same as a job identifier to which a process operating on the computer belongs. 6. The parallel computer system according to claim 5, wherein the reading means reads, when a specific job identifier is broadcast, processing data broadcasted irrespective of a process running on the own computer. Parallel computer system. 7. The parallel computer system according to claim 1, wherein the broadcasting means has a function of broadcasting an interruption notification in addition to broadcasting processing progress information, and a broadcast job identifier. A parallel computer system comprising: an interrupt unit that generates an interrupt to a CPU in accordance with a broadcast interrupt notification when is the same as a job identifier to which a process operating on its own computer belongs. 8. The parallel computer system according to claim 7, wherein the interrupt unit generates an interrupt to the CPU when a specific job identifier is broadcast, irrespective of a process running on the own computer. Characteristic parallel computer system. 9. The parallel computer system according to claim 1, wherein the broadcasting means has a function of broadcasting processing data and a function of broadcasting an interrupt notification in addition to broadcasting the processing progress information. Means for adding an operation code indicating the type of the information to the information to be broadcast at the time of the broadcast processing of the broadcasting means, and decoding the operation code to be broadcast, and the decoding result indicates the processing progress information. When the barrier synchronization mechanism is activated, when the decoding result indicates the processing data, the reading of the processing data is instructed, and when the decoding result indicates the interrupt notification, the interruption to the CPU is instructed. A parallel computer system, comprising: