JPH10269175A - Address bus device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a microprocessor accessible to memory without taking a time without providing an address bus for memory and an address bus for an I/O differently. SOLUTION: In the address bus device which is provided with a memory 1, an I/O device 2, a microprocessor 3 which accesses either of accessed parts 10 that are the memory 1 and the device 2 in accordance with a selection signal and an address bus 6 which transmits an active signal that makes the parts 10 having an access destination active and a designation signal that designates the access destination in the accessed parts, the bus 6 simultaneously transmits the active signal and the designation signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address bus device for a microprocessor to access a memory or an I / O device.

[0002]

2. Description of the Related Art Conventionally, there is an address bus device of this type shown in FIG. This is a memory M having several kbytes or more, an I / O device IO having only a few bytes at most, and either a memory M or an I / O device IO depending on the selection signal IO / M. A microprocessor MP for accessing one of the accessed parts X, and an address bus A for transmitting an active signal for activating the accessed part X having an access destination and a designation signal for designating the access destination in the accessed part X; Have.

More specifically, the active signals include an active signal for memory and an active signal for I / O which are separately transmitted by the address bus A. The memory active signal and the I / O active signal are transmitted through a latch M provided between the memory M and the I / O device IO and the microprocessor MP. Note that several k
The memory designating signal for designating the access destination in the memory M having bytes or more requires a large bus space, and is transmitted separately from the memory active signal. Also, an I / O device IO having at most only a few bytes
Is transmitted at the same time as the I / O active signal, because a large bus space is not required.

Next, the operation of the above device will be described.
When the microprocessor MP accesses the I / O device IO, the latch L enters a so-called through state in which the I / O active signal passes as it is because the input to the G terminal is "H". Therefore, the I / O active signal that has passed through the latch L activates the desired I / O device IO that is the accessed portion X selected by the selection signal. On the other hand, the I / O designation signal transmitted at the same time as the I / O active signal by the address bus designates the access destination in the accessed portion X, and the microprocessor MP sends the I / O designation signal to the access destination designated by the memory designation signal. to access.

When the microprocessor MP accesses the memory M, the latch L sets the input to the G terminal to "L" by setting the flip-flop F,
A so-called non-through state is set. Therefore, at the same time when the write clock is supplied from the WT line, the memory active signal input each time activates the desired memory M, which is the accessed portion X selected by the selection signal. Then, the memory designating signal transmitted separately from the memory active signal via the address bus A in a state where no pulse is inputted to the flip-flop F designates the access destination in the accessed part X, and the microprocessor
The MP accesses the access destination designated by the memory designation signal. Thus, after the microprocessor accesses the access destination designated by the designation signal, the flip-flop F is reset to return the latch L to the through state.

[0006]

In the conventional address bus device described above, the memory address bus and the I / O
A memory and I / O active signal for activating a desired accessed portion X having an access destination using a limited address bus space without providing a separate address bus, A memory and I / O designation signal for designating an access destination can be transmitted.

However, when the microprocessor MP accesses the memory M, as described above, the latch L must be set to the non-through state before activating the memory M which is the access target X selected by the selection signal. In addition, since the microprocessor MP has to go through the procedure of returning the latch L to the through state after accessing the access destination, it takes time to access.

The present invention has been made in view of the above points, and an object of the present invention is to provide a microprocessor capable of saving time without providing a memory address bus and an I / O address bus separately. It is an object of the present invention to provide an address bus device which can access a memory without using a memory.

[0009]

In order to solve the above-mentioned problems, the invention according to claim 1 provides a memory, an I / O device, and one of a memory and an I / O device according to a selection signal. And an address bus for transmitting an active signal for activating the accessed part having an access destination and a designation signal for designating the access destination in the accessed part. The address bus is configured to simultaneously transmit the active signal and the designation signal.

According to a second aspect of the present invention, in the first aspect of the present invention, the active signal is a memory active signal and an I / O signal simultaneously transmitted by the address bus.
An active signal for O is provided, and a selector for selecting one of the active signal for memory and the active signal for I / O according to the selection signal is provided.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. This address bus device includes a memory 1, an I / O device 2, a microprocessor 3,
It comprises a selector 4, a decoder 5 and an address bus 6.

The memory 1 has a memory space of 2 Kbytes, for example, and when selected by a selection signal,
The access unit 10 is accessed by the microprocessor 3. The memory space of the memory 1 is not limited to 2K bytes. I / O device 2
It constitutes an I / O unit 20 together with the memory 1 and has an I / O space of, for example, 32 bytes. When selected by a selection signal, the microprocessor 3
To be accessed by the user. The I / O space of the I / O device 2 is not limited to 32 bytes. The I / O unit 20 constituted by the memory 1 and the I / O device 2 has 32 units, but the I / O unit 20 constituted is not limited to 32 units.

The microprocessor 3 constitutes a CPU unit 30 together with the selector 4, the decoder 5 and the like, and accesses the memory 1 or the I / O device 2 as described above.

The selector 4 comprises an input A terminal and an input B terminal.
Terminals are provided. The input A terminal is connected to the address bus 6, and the memory active signal is transmitted and input through A11 to A15. The input B terminal is also connected to the address bus 6, and an I / O active signal is transmitted and input through A5 to A9. The selector 4 is provided with an output Y terminal for outputting an active signal for activating one of the accessed parts 10 selected by the selection signal IO / M.
That is, when the memory 1 is selected by the selection signal IO / M, the memory active signal transmitted by A11 to A15 is output from the output Y terminal, and the I / O device is selected by the selection signal IO / M. When 2 is selected, the I / O active signal transmitted by A5 to A9 is output from the output Y terminal.

The decoder 5 is for decoding the active signal output from the output Y terminal of the selector 4 and is provided between the selector 4 and the memory 1 and the I / O device 2.

As described above, the address bus 6 supplies the active signals for memory and I / O, and the signals for memory and I / O.
The / O designation signal is transmitted. For details, see address bus 6
Transmits an active signal for memory and a designating signal for memory simultaneously, and simultaneously transmits an active signal for I / O and a designating signal for I / O. The memory active signal activates the memory 1 having the access destination when the accessed portion 10 is the memory 1. The I / O active signal is output when the accessed unit 10 is the I / O device 2.
Activate the I / O device 2 having the access destination.
The memory designation signal designates an access destination in the activated memory 1 when the accessed part 10 is the memory 1. The I / O designation signal is used when the accessed unit 10 is the I / O device 2.
Specify the access destination in device 2.

Next, the operation of this device will be described.
When the microprocessor 3 accesses the I / O device 2, the I / O device 2 is selected by the selection signal IO / M, and the I / O active signal transmitted by A5 to A9 is transmitted to the accessed unit 10 Desired I / O device
2 at the same time as the I / O designation signal transmitted by A0 to A4 designates the access destination in the accessed unit 10, and the microprocessor 3 sets the access destination designated by the I / O designation signal to the access destination designated by the I / O designation signal. to access.

When the microprocessor 3 accesses the memory 1, the memory is operated by a selection signal IO / M.
1 is selected and the active signal for memory transmitted by A11 to A15 activates the desired memory 1 which is the accessed part 10, and at the same time, the I / O designation signal transmitted by A0 to A10 is The access destination in the access unit 10 is designated, and the microprocessor 3 accesses the access destination designated by the memory designation signal.

In such an address bus device, the active signal and the designation signal transmitted through the address bus 6 are not limited to those for memories or I / Os. Without separately providing the address bus for I / O and the address bus for I / O,
Using a limited address bus space, memory and I / O
An active signal for O and a designation signal for memory and I / O can be transmitted. Moreover, address bus 6
Since the active signal and the designation signal are transmitted at the same time, it is not necessary to provide a latch for separately passing the designation signal for memory and the active signal for memory depending on the presence or absence of a pulse input to the flip-flop as in the conventional example. As a result, since the switching between the through state and the non-through state of the latch is not performed, the microprocessor 3 can access the memory 1 without taking much time.

In order to activate the accessed section 10, only one of the memory active signal and the I / O active signal selected by the selector 4 needs to be decoded. 5 in one.

[0021]

According to the first aspect of the present invention, the active signal and the designation signal transmitted by the address bus are not limited to those for the memory or the I / O. A memory and I / O active signal and a memory and I / O designation signal are transmitted using a limited address bus space without separately providing an address bus for I / O and an address bus for I / O. be able to. Moreover, since the address bus simultaneously transmits the active signal and the designation signal, a latch is provided as in the conventional example, which separately passes the memory designation signal and the memory active signal depending on the presence or absence of a pulse input to the flip-flop. This eliminates the need to switch between the through state and the non-through state of the latch, so that the microprocessor can access the memory in a short time.

According to a second aspect of the present invention, in addition to the effect of the first aspect of the invention, in order to activate the accessed portion, the active signal for the memory or the active signal for the I / O selected by the selector is selected. Since only one of them needs to be decoded, only one decoder is required for decoding.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional example.

[Explanation of symbols]

 1 Memory 2 I / O device 3 Microprocessor 4 Selector 6 Address bus 10 Accessed part

Claims (2)

[Claims] 1. A memory, an I / O device, a microprocessor for accessing one of a memory and an I / O device to be accessed in response to a selection signal, and an access target having an access destination is activated. An address bus for transmitting an active signal to be transmitted and a designation signal for designating an access destination in the accessed part. The address bus, wherein the address bus transmits the active signal and the designation signal simultaneously. An address bus device characterized by the following. 2. The memory device according to claim 1, wherein the active signal is a memory active signal transmitted simultaneously through the address bus.
2. A selector having an active signal for / O, wherein a selector for selecting one of the active signal for memory and the active signal for I / O according to the selection signal is provided. Address bus device as described.