JPH07175748A - Microcomputer system - Google Patents

Abstract

PURPOSE:To assign the optional address value to a peripheral circuit by means of an existing address decoding circuit by including an address latch, a decoder and a multiplexer in an address changing circuit. CONSTITUTION:An address changing circuit 27 is contained in a peripheral circuit 4. The circuit 27 includes an address latch 16 which holds the address of the circuit 4, a decoder 10 which compares the value of the latch 16 with the value of an address bus 2, and a multiplexer MPX 13 which selects an address latch write signal 21 and a chip selection signal 7 with active and inactive write signals 20 respectively. Thus the address value of the circuit 4 can be optionally set. Meanwhile the latch 16 has a resetting function and the circuit 4 has the default address value. Therefore the address value of only the peripheral circuit that sould be changed can be changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer system, and more particularly to a microcomputer system having a flexible peripheral addressing function.

[0002]

2. Description of the Related Art A first example of prior art is shown in FIG.

In this conventional example, for one peripheral circuit 4,
The comparison circuit 50, the address latches 53 and 54, and the setting decoder 70 for decoding the address of the address latch
And had. Similarly, another peripheral circuit 5 has one comparison circuit 51, two address latches 55 and 56, and one setting decoder 71.

In this conventional example, the address range is set for each peripheral circuit 4 via the data bus 3 if the value of the address bus matches the value of the set decoder.
54 and set the address bus 2 data and address
The values stored in the latches 53, 54 are determined by the comparison circuit 50, and the value of the address bus is determined by the address latches 53, 54.
If it is within the range of 54, the chip selection signal 7 becomes active and the peripheral circuit 4 is accessed.

A second example of the prior art is shown in FIG.

In the second conventional example, an address latch 16, a decoder 10, a write signal 20 for one peripheral circuit, an F / F 60 for the peripheral circuit of the next stage, and an address setting signal 65 for the address latch 16. A configuration decoder 62 was needed.

In the second conventional example, if the address write signal 20 is output and the address bus 2 indicates the value of the setty decoder 62, the address latch 1 is output.
The value of data bus 3 is written to 6. When the writing is completed, the write signal 63 becomes active and the value of the data bus is written in the address latch 17. Thus, once the address write mode is entered, the address values are sequentially written into the address latch.

As described above, according to the first and second conventional examples, since it is necessary to decode the address of the address latch circuit, the setting decoding circuit is necessary.

[0009]

As described above,
In the first and second conventional examples, since the address of the address latch circuit is required, the address latch address
A decoding circuit was needed. Further, since the address latch does not have an initial value, it is necessary to set the value in the address latch before accessing the peripheral circuit.

[0010]

According to the present invention, a CPU
In the microcomputer system having at least one peripheral circuit, an address changing circuit for the peripheral circuit, an address bus, and a data bus, the address changing circuit holds an address of the peripheral circuit and An address latch that latches the value of the data bus when the latch clock of the latch is active; a decoder that compares the value of the address bus with the value held in the address latch; A microcomputer system including a multiplexer for inputting an output signal and switching an output destination between a chip select signal of the peripheral circuit and a latch clock of the address latch according to a write signal output by the CPU. Is obtained.

According to the present invention, there is also provided a microcomputer system characterized in that the CPU outputs a reset signal for initializing the address latch.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A microcomputer system according to an embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the microcomputer system according to this embodiment includes a CPU 1, a peripheral circuit 4,
5, 6, address changing circuits 27, 28, ... 29 for the peripheral circuits 4, 5, .. 6, an address bus 2 and a data bus 3. The address changing circuits 27, 28, ... 29 hold the addresses of the peripheral circuits 4, 5, ... 6, respectively, and when the latch clock of the address latch is active, the value of the data bus 3 is changed. Latching address latch 16, 17, ...
.. 18, a decoder 10 for comparing the value of the address bus 2 with a value held in each address latch 16, 17, ..
The output signals of 0, 11, ... 12 are input, and the output destination is set to each peripheral circuit 4 according to the write signal output by the CPU 1.
5, 6 chip select signals and each address latch 1
Multiplexers (MPX) 13, 14, ... 1, which switch between latch clocks 6, 17 ,.
Built-in 5. Further, the CPU 1 outputs a reset signal for initializing the address latch.

As described above, in the microcomputer system of this embodiment, one address changing circuit 27 is built in for each peripheral circuit 4. The address changing circuit 27 stores the address of the peripheral circuit 4 and the value of the address latch 16 and the address latch 16 and the address
Decoder 10 and write signal 20 for comparing the values on bus 2
Address latch write signal 2 when is active
The MPX 13 selects 1 and selects the chip select signal 7 when the write signal 20 is inactive.

Next, the operation of the microcomputer system of this embodiment will be described with reference to FIGS.

For convenience of explanation, the default address value of the peripheral circuit 4 will be referred to as a, and the changed address value will be referred to as b.

Since the address slave latch 31 has a reset function, when the RESET signal 19 is input, the address slave latch 31 becomes a preset initial value a. To change the address value of the peripheral circuit 4, when the write signal 20 is activated, the MPX
13 selects the address latch write signal 21.
Next, when the CPU 1 (see FIG. 1) writes to the address value a, the initial value a is placed on the address bus 2 and b is placed on the data bus 3. When a is placed on the address bus 2, the decoder 10 outputs the coincidence signal 24, the address latch write signal 21 becomes active, and the address master latch 30 latches the value b on the data bus 3. . The next time the latch clock 32 becomes active, the address slave latch 31 will
Latch the value in master latch 30. This completes the change of the address value of the peripheral circuit 4.

As described above, the address value of the peripheral circuit 4 can be set arbitrarily. In the past, there was no default value, but address latch 1
Since 6 has a reset function, the peripheral circuit 4 has a default address value a. Therefore, it is possible to change only the address value of the peripheral circuit that needs to be changed.

The circuit can be made smaller by sharing the address of the address master latch 30 with the address of the peripheral circuit 4.

[0020]

As described above, according to the present invention,
With the addition of one MPX, any address value can be assigned to the peripheral circuit using the existing address decoding circuit.

Therefore, according to the present invention, it is possible to provide a microcomputer system having a flexible peripheral addressing function.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a detailed block diagram of an embodiment of the present invention.

FIG. 3 is a diagram showing a timing chart of the embodiment of the invention.

FIG. 4 is a block diagram of a first conventional example.

FIG. 5 is a block diagram of a second conventional example.

[Explanation of symbols]

1 CPU 2 Address Bus 3 Data Bus 4, 5, 6 Peripheral Circuits 7, 8, 9 Chip Select Signal (CS) 10, 11, 12 Address Decoder 13, 14, 15 MPX 16, 17, 18 Address Latch 19 reset signal 20 write signal 21,22,23 address latch latch signal 24,25,26 match signal 27,28,29 address change circuit 30 address master latch 31 address slave latch 32 latch clock 50, 51,52 comparator circuit 53,54,55,56,57,58 address latch 60,61 F / F 62 setting decoder 63,64 write signal 65 address setting signal 70,71,72 setting decoder

Claims (2)

[Claims] 1. A CPU and at least one peripheral circuit,
In a microcomputer system having an address changing circuit for the peripheral circuit, an address bus, and a data bus, the address changing circuit holds the address of the peripheral circuit and the latch clock of the address latch is active. An address latch for latching the value of the data bus, a decoder for comparing the value of the address bus with the value held in the address latch, and an output signal of the decoder are input and output by the CPU. A microcomputer system including a multiplexer for switching an output destination between a chip select signal of the peripheral circuit and a latch clock of the address latch according to a write signal to be performed. 2. The microcomputer system according to claim 1, wherein the CPU outputs a reset signal for initializing the address latch.