JPH10262225A - Symbol timing generating and recovery system and method to transmit data in analog video signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To synchronize data bits of a transmission analog video signal with a clock phase of a receiver so as to accurately extract data information from the video signal without using the data bits of the data information for providing clock phase information. SOLUTION: A phase locked loop 12 of a transmitter 10 locks a phase of a color burst subcarrier of a video signal to a local oscillator 14 in the phase locked loop and is used for locking a phase of a data clock to the subcarrier. A phase locked loop of a receiver also locks a phase of a subcarrier of a transmitted video signal to a local oscillator of the phase locked loop and is used for locking a phase of the data clock to the subcarrier. Digital data are effectively recovered without using additional data bits for clock phase information by locking a phase of the data clock to the subcarrier in both the transmitter 110 and the receiver so as to synchronize the data clock and the transmitter with the data clock and the receiver.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to the recovery of digital data from analog video signals and, more particularly, to the use of color subcarriers of a video signal for clock synchronization between a transmitter and a receiver. To recover digital data from analog video signals.

[0002]

2. Description of the Related Art Various video transmission systems, such as cable television and closed circuit television, include a transmitter for transmitting an analog video signal, and receiving the analog video signal and converting it into a signal suitable for viewing. To use with the receiver. Most of these transmission systems use a data encoding mechanism to convert digital data and / or data bit symbols into an analog video signal for a number of purposes, such as allowing descrambling, on-screen display, teletext, auxiliary functions, and closed captioning. Encode to When digital data is encoded into an analog video signal, some procedure must be provided to synchronize the transmitted digital data with the receiver clock signal for data recovery. This technique is commonly referred to as "bit synchronization," and is usually
This is achieved by phase locking the local clock source of the receiver with clock phase information transmitted with the digital data.

[0003] Usually, the transmission format of digital data is a data burst type in which a relatively long time interval exists between sequences of digital data in an analog signal. In this regard, a data burst refers to a sequence or group of digital data between no-data intervals in an analog signal without data. A color burst is the first 8 to 1 of each video line used to derive color demodulation information for each segment of video information.
A technical term for a zero cycle sine wave. Generally, digital data is transmitted in a vertical blanking interval of a video signal. The vertical blanking interval is the segment of the analog video signal at the beginning of each video field that does not contain video data. In this format, digital data bursts occur approximately 16-20 milliseconds apart.

[0004]

In a known video signal transmission system, when digital data is transmitted in a burst format, to provide clock phase information,
Some data bits in each burst must be sacrificed. This is because the receiver's data clock passes precisely through the time interval during which no digital data is received and still cannot be synchronized with the data. These digital data bits cannot be used to provide the desired information because they must be sacrificed to provide clock phase information. Therefore,
Additional data bits are required in addition to the bits containing this information. Digital data bits carrying clock phase information limit the amount of information that can be transmitted in each data burst because there is a limit on the portion of the analog video signal that can be used to transmit digital data.

Therefore, a bit synchronization technique for synchronizing a data bit of an analog video signal to be transmitted with a clock phase of a receiver and accurately extracting data information from the video signal is used. There is a need for a technique that does not use data bits of information. Therefore, it is an object of the present invention to provide such a bit synchronization technique.

[0006]

According to the technique of the present invention,
The disclosed video transmission systems and methods include techniques for deriving receiver clock information from a transmitted analog video signal and decrypting digital data encoded in the video signal. In one embodiment,
Digital data is encoded in the vertical blanking interval of the video signal. Using the phase locked loop of the transmitter, the color burst subcarrier of the video signal is phase locked to the local oscillator of the phase locked loop and the data clock is phase locked to the subcarrier. Further, the sub-carrier of the transmitted video signal is phase-locked to the local oscillator of the phase-locked loop using the phase-locked loop of the receiver, and the data clock is again phase-locked to the sub-carrier. By phase locking the data clock to the subcarrier at both the transmitter and the receiver, the data clock at the receiver can be synchronized with the data clock at the transmitter, with additional data bits for clock phase information. You can give effective digital data recovery without using.

[0007] In one particular embodiment, the digital data is Manchester encoded at the transmitter and Manchester demodulated at the receiver,
A valid data transition is provided. Furthermore, "Baker (Barke
r) "code is added to the digital data stream, giving an indication of the start of the digital data sequence. An introductory string of zeros precedes the digital data and the Baker code in the digital data sequence, and a zero detection circuit of the receiver detects the string of zeros and associates the subcarrier transmitted in the transmitted video signal with the data clock of the receiver. Synchronize to distinguish between the correct phase data clock of the receiver and the inverted phase data clock.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS Further objects, advantages and features of the present invention will become readily apparent from the following detailed description and appended claims, taken in conjunction with the accompanying drawings. The following description of a preferred embodiment of a bit synchronization and recovery technique for digital data bits encoded on an analog video signal of a transmitter and a receiver is merely exemplary and will not be construed as limiting the invention, its uses or uses. It is not limited to this.

FIG. 1 is a block diagram showing a part of a transmitter 10 for transmitting an analog video signal having encoded digital data. Analog video signals are in the form of being transmitted for various applications such as cable television, and are known to those skilled in the art.
Television System Committee), PAL (Phase Alte
rnating by Line) and SECAM (Sequential Coule)
ur Avec Memoire) in a number of different known types of video signal formats. In a particular application, the portion of the transmitter 10 shown is a scrambler that scrambles digital data onto an analog video signal for various reasons, such as allowing signal reception.

An analog video input signal that holds video information for transmission to be displayed after transmission and reception and that does not include encoded digital data bits is sent to a phase locked loop (PLL) 12. This PLL12
Is provided with a variable control oscillator 14 functioning as a local oscillator whose phase is fixed by the PLL 12 to the phase of a sine wave color burst subcarrier signal provided at the beginning of each line of video information in an analog video signal. The use of a color burst subcarrier signal to provide color information for an analog video signal is well known to those skilled in the art. FIG. 2 shows a color burst subcarrier signal of frequency Fsc. Locking the color burst subcarrier signal to a local oscillator in a phase locked loop has hitherto been
A digital phase error detector for locking to a color subcarrier of a video signal, filed on December 12, 1995, assigned to the assignee of the present invention and incorporated herein by reference.
or Subcarrier of Video Signals) "in U.S. patent application Ser. No. 08 / 571,018. PL
L12 generates a square wave output signal called the sample clock (SCLK) signal, which is
4 and has a frequency four times the frequency of the subcarrier Fsc, sufficient for video sampling.
FIG. 2 also shows this SCLK signal.

As described above, the phase of the variable control oscillator 14 of the PLL 12 is fixed with respect to the subcarrier present in the analog video signal. In the embodiment described here, the variable control oscillator 14 maintains a frequency four times the frequency Fsc of the sub-carrier, but may use another denominator of the sub-carrier frequency Fsc to provide the SCLK signal. In the case of PAL and NTSC signals, the frequency of the sub-carrier is a chrominance sub-carrier known to those skilled in the art, which can be derived from the color burst signal included in the video signal. For a SECAM signal, this frequency is
Any chrominance subcarrier (BY or RY)
Which are both transmitted at some point in the analog video signal.

The SCLK signal from PLL 12 is sent to divider 16. The phase information signal from PLL 12 is also sent to divider 16 to provide a more accurate phase relationship between the SCLK signal and the output of divider 16. Divider 16
Divides the SCLK signal by 8, and locks the data clock (DCL) phase-locked to the variable control oscillator 14 of the PLL 12.
K) signal, which provides a sufficiently low clock rate suitable for data encoding. Therefore, DCL
The K signal is suitable for providing digital data to an analog signal. The DCLK signal can have one of two possible phases, inverting or non-inverting, with respect to the carrier frequency Fsc. FIG. 2 also shows the DCLK signal. Divider 16 can divide the SCLK signal by another suitable divisor to provide a symbol period in the space of one chrominance subcarrier. This forms a ready source for the symbol (digital data) clock of the transmitter 10.

Since the DCLK signal is one-eighth the frequency of the SCLK of the transmitter 10, there is an ambiguity that the DCLK signal has eight possible phases. This is SC
This is alleviated by the design of the PLL 12 variable control oscillator used to synchronize the LK signal with the color subcarrier of the incoming video signal. Since the color subcarrier signal is used for the purpose of generating an SCLK signal synchronized to both the transmitter 10 and receiver circuits, both the transmitter 10 and receiver circuits require the internal circuitry required by the PLL 12. Access signals. One of these required signals is a fixed phase continuous clock with respect to the color subcarrier.
Since this signal is present in both the transmitter 10 and receiver circuits, it will only cause the DCLK signal to have the ambiguity of two phases: inverted or non-inverted.

The DCLK signal is sent to a symbol waveform generator 18, which encodes digital data on an analog input signal in phase with the DCLK signal. The digital data to be encoded in the vertical blanking interval of the analog video signal to encode various descrambling permits, teletext, closed caption, etc., signals are transmitted to a suitable computer (see FIG. (Not shown) to the waveform generator 18. The symbol waveform generator 18 knows when to send digital data to the DCLK signal according to a control signal from the controller 20. Also, controller 20 may be a computer that controls the operation of transmitter 10 or any other suitable controller known to those skilled in the art for the purposes described herein.

The symbol waveform generator 18 provides a run-in code with multiple zeros in a row to the data, and as described below, which of the two ambiguous clock phases is the correct phase for bit recovery. Is determined by the data recovery circuit. The symbol waveform generator 18 also provides a string of zeros followed by a 7-bit "baker" code. This Baker code is a fixed 7-bit sequence used to detect the start of each data burst. The Baker code allows the detection circuit to determine the correct bit position of all data bits in the data burst. For they are known to the bakery code.

FIG. 3 shows a baker code and a leading zero generator 24 which generates a baker code following a string of zeros.
FIG. The generator 24 comprises a parallel load, serial output shift register 26, which comprises:
A standard digital function block implemented by a series of registers with a multiplexer between each register to select either the previous register output or an external input. At a certain time near the start of the video data line, a predetermined baker code (1011) is stored in the register 26.
001) and a string of eight zeros are externally loaded. For example, a load control input from controller 20 instructs shift register 26 to output a baker code and a string of zeros at the appropriate time. Shift register 26 shifts out the string of zeros and the subsequent baker code at the DCLK signal rate. The output from shift register 26 is gated by multiplexer 28 into a digital data stream. The multiplexer 28 is controlled, for example, by a selection header signal from the controller 20. The select header signal enables the multiplexer 28 to output a Baker code after a string of zeros and then digital data to the Manchester encoder, as described below.
Before and after giving the selection header signal, the shift register 26
Is not used and its value is not a problem. As will be apparent to those skilled in the art, the load control and selection header signals and various other control signals are all generated by timing and control circuits within transmitter 10.

The digital data, the baker code, and the string of zeros are Manchester encoded in the waveform generator 18 at the DCLK signal rate. Manchester encoding is a known digital data encoding technique that guarantees proper transitions between data bits. Generally, Manchester encoding is performed by exclusive ORing the DCLK signal and data. FIG. 4 shows a logic circuit 30 describing a technique for Manchester encoding data suitable for the purposes described below. In this circuit 30, digital data is clocked into a flip-flop 32 which acts as a 1-bit register in synchronization with the DCLK signal. The digital data from register 32 is sent to XOR gate 34, which ORs the digital data with the DCLK signal. The Manchester-coded digital data is then output from XOR gate 34. FIG. 2 illustrates a data sequence and Manchester encoded data for the DCLK signal.

By Manchester encoding the digital data, the digital data has an average duty cycle of 50%. In addition, Manchester encoding of digital data provides a large number of transitions to the digital data, allowing more accurate clock recovery, and the digital data being symmetrical about an average independent of the digital data. Enables AC coupling of digital data if continued to switch. Without Manchester encoding, long strings of zeros or ones would tend to drift toward the average when AC coupled. Typically, digital data transmitted over an RF channel is AC-coupled in the baseband. For applications of the present invention, Manchester coding provides a "data average" that is independent of video signal level. This is necessary for data inserted into the video signal.
This is because the video signal is DC-recovered by an individual circuit in the data recovery circuit. If an average is not established for the data, the data becomes very sensitive to the signal level or gain of the baseband video signal.

The Manchester-coded digital data stream including the Baker code and leading zeros from the symbol waveform generator 18 is then passed to a video / data multiplexer 36.
Sent to The analog video input signal is also sent to the multiplexer 36. A control signal from the controller 38 is sent to the multiplexer 36 and the multiplexer 36
Know when to multiplex a digital data stream into a video input signal, such as during a vertical blanking interval. Controller 38 may be part of controller 20, or may be any type of suitable computer for the purposes described herein. The output of the multiplexer 36 is an analog video signal encoded with digital data containing clock information phase-locked to the frequency of the color burst subcarrier. The output of the multiplexer 36 is a data stream consisting of a Manchester-coded zero followed by a Manchester-coded Baker code followed by Manchester-coded data, which is output during the vertical blanking interval of the analog video signal. A data stream multiplexed into one or more lines of data. This signal is sent to a transmitting antenna (not shown) or other suitable transmitting device. FIG. 2 also shows this output signal.

FIG. 5 is a block diagram of a portion of a receiver 40 that acts as a descrambler for descrambling and recovering digital data encoded in the analog video signal transmitted from the transmitter 10. The video signal having the encoded digital data is sent to the PLL 42 of the receiver 40. The PLL 42 fixes the phase of the subcarrier of the video signal to a variable control oscillator 44 that functions as a local oscillator of the PLL 42. PLL4
The SCLK signal from 2 is phase locked to the local oscillator. The local oscillator of the PLL 42 is PLL1
Just as the two variable control oscillators 14 are phase-locked to the sub-carrier of the analog video input signal, they are phase-locked to the sub-carrier present in the video signal having encoded digital data.

The SCLK signal from the PLL 42 is
The SCLK signal from 12 is sent to divider 46 in the same manner as sent to divider 16. Further, if the phase information signal is P
The data is sent to the divider 46 from the LL 42. The divider 46 divides the SCLK signal in the same manner as the
And a DCLK 'signal whose phase is fixed to the subcarrier frequency of the video signal. PLL12
Is the same sub-carrier video signal sent to the PLL 42,
The LK ′ signal is phase-locked to the DCLK signal from the divider 14. The particular phase of the DCLK 'signal from divider 46 is inverted from the DCLK signal from divider 16, so that the DCLK signal is not fully synchronized to be suitable for data recovery.

The DCLK 'signal from the divider 44 and the video signal sent to the receiver 40 are sent to a symbol demodulator 48. The symbol demodulator 48 is controlled by a control signal from a controller 50. Controller 50 may be any suitable computer that controls the operation of receiver 40, or may be any other processor suitable for the purposes described herein, as will be apparent to those skilled in the art.

The symbol demodulator 48 includes various circuits for recovering digital data from a video signal. One of these circuits detects a string of zeros in the data stream and outputs the DCLK 'signal of the receiver 40 to the DC
This is a zero detection circuit used to match the LK signal. The string of zeros in the transmitted analog video signal is inverted in the DCLK 'signal of the receiver 40. An all-zeros or all-ones Manchester coded string is that they both have the original data clock (DCL).
K) Looks the same in that it resembles a signal. The only difference is which one of the two data clock phases the symbol demodulator 48 selects and looks at. The receiver 40 knows that a string is zero, in particular, the first data bit encountered in a data burst,
The correct phase of DCLK can be selected and demodulator 4
8 causes these bits to output a zero. Therefore, the rest of the data burst will also have the correct clock phase. If the incoming bit is a one, the state of the data clock is inverted and brought into the correct phase. Such a technique is described in the "Digital Color Burst Phase Switch for PAL Imaging System (Digit
al Color Burst Phase Switch for PAL Video System
s) ", the PAL disclosed in U.S. patent application Ser. No. 08 / 592,745, filed Dec. 12, 1995.
Similar to a switch.

As shown in FIG. 6, the symbol demodulator 48 is a Manchester demodulator 5 for performing Demanchester processing on digital data that is Manchester-coded on a video signal.
2 is provided. The DCLK signal is used to clock the Manchester demodulator 52 and is in phase with the transmitter 10 DCLK signal. Manchester demodulator 52
Comprises a series of four XOR gates 54 that receive the top four digital video samples of the analog signal.
Video signals can contain significant noise,
The Manchester decoding operation requires an operation that is more than simply ORing the video signal. Therefore, the Manchester demodulator 52 includes soft decision logic for the Manchester decoding operation. The output of each XOR gate 54 is sent to an accumulator 56 that includes an adder 58 and a register 60. Accumulator 56 is cleared by applying a clear signal to register 60 at the beginning of each data bit. A control circuit such as controller 50 generates a clear signal. The seven outputs are sent from adder 58 to register 60. The register 60 is a high-speed SCL
Clocked at the K signal rate, the seven outputs from adder 58 are therefore continuously clocked back to adder 58 at this rate for each group of four data bits input to adder 58. . Therefore, the value of adder 58 is positive if the original four data bits are zero, or negative if the original four data bits are one. The output from register 60 is sent to register 62, which is clocked at the DCLK signal rate. Register 6
The two output sign bits are provided as demodulated data, and the remaining bits are discarded.

FIG. 7 is a logic diagram of the zero detector 68 for performing the above-described zero detection and determining the appropriate clock phase of the DCLK 'signal at the receiver 40. The purpose of the zero detector 68 is to be in phase with DCLK 'or
The determination is to determine the correct phase of the DCLK signal which is 180 ° out of phase with the K ′ signal. The demanchester-processed data from the demodulator 52 is supplied to an accumulator 70 including an adder 72 and a 1-bit zero detection accumulator 74.
Sent to This accumulator 70 adds the number of ones received during a particular time interval between any of the horizontal lines of the video signal containing the digital data to be received. This time interval is chosen to match the expected position on the horizontal line of the transmitted string of zeros. In the preferred embodiment, a string of eight zeros is transmitted as shown in FIG. However, since there is some ambiguity in the location of the string of zeros in the received signal, the accumulation of the number of ones received is performed only during the time of 6 bits to account for some errors in bit positions.

The time interval of the accumulation is slightly ahead of the clear signal which forces the zero detect accumulator register 74 to a value of zero. The clear signal also clears the zero detection comparison register 76. This is because the XOR gate 78 is DC
The LK 'signal is passed so as to become the DCLK signal. Thus, DCLK 'and DCLK are initially in phase during the zero detection accumulation time interval. This same time interval is followed by a zero detect comparison signal, which causes the accumulated number of ones to be compared to a threshold value. The comparison is
Performed by a binary weighted digital comparator 80,
The one-bit result is registered in the zero detection comparison register 76. FIG. 8 shows the relationship between signals and the relationship with video signals.
Is shown in The video data lines provide the original sync signal, followed by the color burst frequency signal, followed by a string of zeros, followed by the Baker code, and then the data.

If no noise-induced errors occur during the accumulation of the received one's number, the accumulator 70
Should contain a value of 0 if all zeros were received, or a value of six if all ones were received. In a preferred embodiment, the number of ones received is compared to a value of three to take into account the potential for noise-induced errors and to provide some margin for such errors. Thus, if four, five or six ones are detected, the string is assumed to contain "almost one" and therefore the current phase of the DCLK signal is incorrect and must be corrected. It is also assumed that they do not.
Next, the comparison value registered in the zero detection comparison register 76 becomes 1, and this is used to invert the DCLK 'signal by the XOR gate 78, thereby causing the DCLK' signal to be 180 ° out of phase with DCLK. On the other hand, 0, 1,
If two or three ones are received, it is assumed that the received string contains "almost zero", thus:
The current DCLK 'phase is correct and DCLK and DC
It is also assumed that LK 'is kept in phase. In this case, the compare register 76 contains a 0 and the XOR gate 78 passes DCLK 'unchanged and the DCL
K.

The symbol demodulator 48 also includes a Baker code detector for detecting the start of each 7-bit Baker code in the digital data. FIG. 9 shows a baker code detector 86 that detects a baker code of digital data after the digital data has been subjected to Demanchester processing. The detector 86 has a 7-bit shift register 88 including seven registers 90. This shift register 88 receives the demanchestered data at the input of the leftmost register 90 and
0 is clocked by the DCLK signal. The output of each register 90 is sent to the input of a separate XOR gate 92. The other input of each XOR gate 92 is a predetermined Baker code bit that must be at that location in shift register 88. When the Baker code appears in shift register 88, the value of adder 94 is increased above a predetermined threshold, indicating the start of a series of data bits. In one embodiment, the average energy of the zero detector is used in conjunction with the energy of the baker code detector to provide a longer baker code and increase its noise immunity.

The various logic diagrams described above are provided by way of example to perform the specific functions described herein, and are not intended to be limiting. In practice, there are many ways to implement the logic described herein. For example, modern digital circuits perform these functions using a low gate count state machine. The description of these state machines is described in various flip-flops for the gate.
It is much more complex than the one described here because the flop contributes more than one function.

As described above, a number of effects can be realized by using the color burst subcarrier frequency of the video signal to provide clock phase information.
For example, it is not necessary to use data bits in receiver 40 just to recover the phase of the data clock.
The color burst is a digital data burst of 20 bits.
Since it occurs at a frequency of 0 or more times, it is more robust than the data clock recovery method based on only a few bits included in the digital data burst, and has a greater tolerance for channel noise.

As will be apparent to those skilled in the art, the preferred embodiment described herein uses a string of zeros at the beginning of the data transmission to resolve the phase ambiguity of the DCLK signal at the receiver, but is described herein. It is clear that a similar receiver can be designed using a DCLK signal at twice the frequency of the DCLK signal. In such a system, the data rate is twice that of the system described herein as the preferred embodiment, and the high data rate slightly reduces the bit error rate performance of the data transmission channel. However, since there is no phase ambiguity between the DCLK signal of the transmitter used to encode the transmitted data and the DCLK signal of the receiver used to decode the transmitted data, the string of zeros is Not required. In such a system, the bit time is the same as the cycle in which the color burst waveform cycles once.
The phase of the color burst signal is inherently known from the operation of the phase locked loop circuit that synchronizes the system clock with the incoming color burst signal.

The above description is merely illustrative of the present invention. Those skilled in the art will readily appreciate from the foregoing description, accompanying drawings and claims that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims. Like.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a portion of a transmitter for encoding and transmitting digital data on an analog video signal according to one embodiment of the present invention.

2 shows a series of signal curves for various signals of the transmitter of FIG. 1;

3 is a circuit diagram showing a Baker code and a leading zero generator for providing a Baker code and leading zeros before the digital data of the transmitter of FIG. 1;

FIG. 4 is a logic circuit diagram showing a technique for converting digital data into Manchester code in the transmitter of FIG. 1;

FIG. 5 is a block diagram illustrating a portion of a receiver that decodes digital data encoded into an analog video signal according to an embodiment of the present invention.

6 is a logic circuit diagram showing a Manchester demodulator for demodulating Manchester-coded data bits of an analog video signal sent to the receiver of FIG. 5;

FIG. 7 is a logic circuit diagram showing a zero detector for detecting zero of digital data received by the receiver of FIG. 5;

FIG. 8 is a timing diagram illustrating various timing signals of the zero detector of FIG. 7;

FIG. 9 is a logic circuit diagram showing a baker code detection system for detecting a baker code of a video signal sent to the receiver of FIG. 5;

[Explanation of symbols]

 Reference Signs List 10 Transmitter 12, 42 Phase locked loop (PLL) 14, 44 Variable control oscillator 16, 46 Divider 18 Symbolic waveform generator 20, 38, 50 Controller 24 Baker code and leading zero generator 26 Shift register 28, 36 Multiplexer 30 Logic Circuit 32 Flip-flop 34, 54 XOR gate 40 Receiver 48 Symbol demodulator 52 Manchester demodulator 68 Zero detector 70 Accumulator

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 5/455 H04N 9/475 9/475 11/04 C 11/04 H04L 7/02 B // H04L 7/033

Claims (20)

[Claims] 1. A system for transmitting and receiving an analog video signal, wherein a first local oscillator is phase locked to a subcarrier frequency of the video signal to generate a first phase locked sample clock signal. A fixed loop, a waveform generator for generating encoded digital data in response to a first data clock signal based on the first sample clock signal, and responsive to the encoded digital data and video signal And a video / data multiplexer for generating a video signal including the encoded digital data; and a second local oscillator responsive to the video signal including the encoded digital data, for controlling the encoded digital data. The phase is fixed to the subcarrier frequency of the video signal including A second phase locked loop for generating a pull clock signal; and a demodulator responsive to a second data clock signal based on the second sample clock signal, wherein the second data clock signal is A demodulator including demodulation means for extracting the encoded digital data in synchronization with the first data clock signal. 2. The system of claim 1 wherein said waveform generator comprises Manchester encoding means for encoding said encoded digital data to provide appropriate transitions between data bits of said digital data. . 3. The system of claim 1 wherein said waveform generator includes a Baker Code Generator that provides a known series of Baker Code data bits at the beginning of a series of data bits in said encoded digital data. 4. The system of claim 1, wherein the waveform generator includes a zero generator that generates a known number of strings of zero data bits at the beginning of a series of data bits in the encoded digital data. 5. The demodulator detects a string of zeros or ones in the encoded digital data to generate a phase orientation between the second data clock signal and the encoded digital data signal. The system of claim 1, comprising a detector that performs the detection. 6. The detector includes an accumulator that accumulates data from data bits of the encoded digital signal, the accumulator accumulating data at a rate of a sample clock signal, and the accumulator being accumulated. 6. The system of claim 5, wherein the generated data underlies a phase orientation between the second data clock signal and the encoded digital data signal. 7. The system of claim 2, wherein said demodulator comprises a Manchester demodulator for demodulating said Manchester encoded digital data. 8. The system of claim 7, wherein said Manchester demodulator includes an accumulator that accumulates data from said digital data to provide a soft decision for demodulating Manchester encoding. 9. The system of claim 3, wherein the demodulator includes a Baker Code Detector that detects Baker Code data bits in the encoded digital data. 10. The system of claim 1, wherein the subcarrier frequency of the video signal is a color burst frequency signal of the video signal used to derive color demodulation information. 11. The video / data multiplexer multiplexes encoded digital data into a vertical blanking interval of an analog video signal.
System. 12. A receiving data clock signal of a receiver,
A system for synchronizing a transmitted data clock signal of a transmitter in an analog video signal including encoded digital data received by the receiver, wherein the data clock signal of the transmitter is a sub-signal of the video signal. A phase locked loop for phase locking a local oscillator to a subcarrier frequency of the video signal in response to a video signal containing the encoded digital data, the system comprising: The loop generates a sample clock signal phase-locked to the sub-carrier frequency, the sample clock signal having a higher rate than the rate of the sub-carrier frequency, and a receiver data clock signal based on the sample clock signal. And a demodulator responsive to the data clock of the receiver. A demodulation means for synchronizing the clock signal with the data clock signal of the transmitter. 13. The system of claim 12, wherein said encoded digital data of a video signal comprises a series of data bits including a string of zeros, a predetermined code and subsequent data bits. 14. The demodulator according to claim 13, wherein the demodulator includes a detector that detects a string of zeros to generate a phase orientation between the data clock signal of the receiver and the data clock signal of the transmitter. The described system. 15. The detector includes an accumulator for accumulating data from a string of zeros, the accumulator accumulating data at a rate of the sample clock signal, wherein the accumulated data is 15. The system of claim 14, wherein the system is based on a phase orientation between a receiver data clock signal and the transmitter data clock signal. 16. The system of claim 12, wherein the subcarrier frequency is a color burst frequency signal of a video signal used to derive color demodulation information. 17. A method for transmitting and receiving an analog video signal, comprising: fixing a phase of a first local oscillator to a subcarrier frequency of the video signal to generate a first phase-locked sample clock signal; Generating a first data clock signal phase-locked to the signal, encoding the digital data into an analog signal at the rate of the first data clock signal, and locking the phase of the second local oscillator to the subcarrier frequency of the video signal; Generating a second phase-locked sample clock signal, and generating a second phase-locked sample clock signal.
Generating said data clock signal, and synchronizing said second data clock signal with said first data clock signal to extract encoded digital data. 18. The method of claim 17, further comprising providing a string of zeros at the beginning of a series of data bits in the encoded digital data. 19. The step of synchronizing a second data clock signal with a first data clock signal comprises detecting a string of zeros in the encoded digital data and combining the second data clock signal with the first data clock signal. 20. The method of claim 18, including generating a phase orientation with a data clock signal. 20. The method of claim 17, wherein the sub-carrier frequency of the video signal is a color burst frequency signal used to derive color demodulation information.