JPH10261904A - Dummy resistor for lumped constant-type isolator - Google Patents

Dummy resistor for lumped constant-type isolator

Info

Publication number
JPH10261904A
JPH10261904A JP10098621A JP9862198A JPH10261904A JP H10261904 A JPH10261904 A JP H10261904A JP 10098621 A JP10098621 A JP 10098621A JP 9862198 A JP9862198 A JP 9862198A JP H10261904 A JPH10261904 A JP H10261904A
Authority
JP
Japan
Prior art keywords
substrate
resistor
center
center conductor
dummy resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10098621A
Other languages
Japanese (ja)
Other versions
JP3209418B2 (en
Inventor
Manabu Yoshimoto
学 由本
Minoru Nozu
稔 野津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Proterial Ltd
Original Assignee
Hitachi Metals Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Metals Ltd filed Critical Hitachi Metals Ltd
Priority to JP09862198A priority Critical patent/JP3209418B2/en
Publication of JPH10261904A publication Critical patent/JPH10261904A/en
Application granted granted Critical
Publication of JP3209418B2 publication Critical patent/JP3209418B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To miniaturize a device and to provide a lumped constant-type isolator with large resistance to power by arranging ground electrode patterns on both end parts of one face in a substrate and setting the two resistors of the resistance pattern formed with a center conductor connection electrode pattern provided in the center to be parallel connection constitution. SOLUTION: In a center conductor part 3, a center conductor 5 is folded so that it surrounds a circular ferrite core 4 and the tips are formed as terminals 6a, 6b and 6c. A ground board 10 and a dielectric substrate 7 are overlapped and arranged on a lower case 12. The ferrite core 4 of the center conductor part 3a is inserted into a hole 8 at the center of the dielectric substrate 7. Two electrode patterns 18 connected to the center conductor are formed at the center of one face of the substrate. The resistance pattern is formed between the electrode patterns and the ground electrode patterns at the end parts on both sides and they are insulated by over glass. Chip resistor 17 is constituted by connecting two resistors in parallel and therefore dummy resistor with large resistance to power can be constituted.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明が属する技術分野】本発明は、VHF、UHF及
びマイクロ波帯などにおいて使用される集中定数型アイ
ソレータのダミー抵抗に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lumped constant type isolator used in VHF, UHF and microwave bands.

【0002】[0002]

【従来の技術】従来の集中定数型アイソレータの一例の
分解斜視図を図5に示す。この従来例は、下ケース65
上にパターン電極の形成された誘電体基板63を配置
し、ガーネット64と互いに絶縁状態で重ね合わされた
中心導体66とからなる中心導体部を誘電体基板に形成
された穴に配置し、各中心導体と誘電体基板上の所定の
パターン電極とを接続し、磁石67の装着された上ケー
ス68を被せて構成されている。この誘電体基板63の
69はダミー抵抗であり、70はアース電極である。こ
のアース電極に接続されたダミー抵抗により、中心導体
の一つの端子が終端されている。
2. Description of the Related Art FIG. 5 is an exploded perspective view of an example of a conventional lumped constant type isolator. In this conventional example, the lower case 65
A dielectric substrate 63 having a pattern electrode formed thereon is disposed, and a central conductor portion including a garnet 64 and a central conductor 66 superposed in an insulated state is disposed in a hole formed in the dielectric substrate. A conductor is connected to a predetermined pattern electrode on a dielectric substrate, and is configured to cover an upper case 68 on which a magnet 67 is mounted. Reference numeral 69 of the dielectric substrate 63 denotes a dummy resistor, and reference numeral 70 denotes a ground electrode. One terminal of the center conductor is terminated by the dummy resistor connected to the ground electrode.

【0003】[0003]

【発明が解決しようとする課題】従来の集中定数型アイ
ソレータでは、ダミー抵抗は、静電容量成分を構成する
誘電体基板上の一部に、印刷された抵抗により形成され
ている。この誘電体基板は、静電容量を得ることを主目
的としているので、放熱性が良くなく、スペース的にも
余裕がなかった。このため、ダミー抵抗部における耐電
力が小さく、せいぜい1W程度の耐電力しか実現出来な
かった。
In a conventional lumped constant type isolator, a dummy resistor is formed by a printed resistor on a part of a dielectric substrate constituting a capacitance component. Since the main purpose of this dielectric substrate is to obtain a capacitance, it has poor heat radiation properties and has no space. For this reason, the withstand power in the dummy resistor portion is small, and only a withstand power of about 1 W can be realized at most.

【0004】従って、耐電力を上げるためにスペースを
広げると小型化の流れに逆行することとなり、耐電力の
比較的小さい用途では良いが、比較的大きな耐電力を必
要とする用途では、小型の集中定数型アイソレータを構
成することが困難であった。
Therefore, if the space is increased to increase the withstand power, the flow of miniaturization is reversed, and it is good for an application having a relatively small withstand power, but is small for an application requiring a relatively large withstand power. It was difficult to construct a lumped constant type isolator.

【0005】本発明は、上記のことを鑑みて、小型でし
かも耐電力の大きい集中定数型アイソレータを構成する
ことができるダミー抵抗を提供する事を目的とする。
SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a dummy resistor which can form a lumped-constant type isolator which is small and has high power durability.

【0006】[0006]

【課題を解決するための手段】本発明は、集中定数型ア
イソレータ用ダミー抵抗において、前記ダミー抵抗は、
基板上に抵抗パターンを形成して構成されたチップ抵抗
であり、前記集中定数型アイソレータのケース内側の側
面に配設されることを特徴とする集中定数型アイソレー
タ用ダミー抵抗である。
According to the present invention, there is provided a dummy resistor for a lumped constant type isolator, wherein the dummy resistor comprises:
It is a chip resistor formed by forming a resistor pattern on a substrate, and is a dummy resistor for a lumped-constant isolator, which is provided on a side surface inside a case of the lumped-constant isolator.

【0007】また本発明は、前記ダミー抵抗は、前記基
板の一面の中央部に中心導体が接続される電極パターン
を有し、該基板の一面の両端端部にアース電極パターン
を有し、該アース電極パターンは該基板の裏面に形成さ
れたアース電極パターンに導通し、前記中心導体が接続
される電極パターンと端部のアース電極パターンの間に
それぞれ抵抗パターンが形成され、前記基板中央部の電
極パターンに前記中心導体が接続され、前記基板の裏面
のアース電極パターンが前記ケース内側側面に接続さ
れ、2つの抵抗が並列に接続される構成となっているこ
とを特徴とする集中定数型アイソレータ用ダミー抵抗で
ある。
Further, in the invention, it is preferable that the dummy resistor has an electrode pattern to which a center conductor is connected at a central portion of one surface of the substrate, and an earth electrode pattern at both ends of one surface of the substrate. The ground electrode pattern is electrically connected to the ground electrode pattern formed on the back surface of the substrate, and a resistance pattern is formed between the electrode pattern to which the center conductor is connected and the ground electrode pattern at the end. A lumped-constant isolator, wherein the central conductor is connected to an electrode pattern, a ground electrode pattern on the back surface of the substrate is connected to the inner side surface of the case, and two resistors are connected in parallel. Dummy resistor.

【0008】[0008]

【発明の実施の形態】本発明は、ダミー抵抗を、基板上
に形成したチップ抵抗とし、そのチップ抵抗を集中定数
型アイソレータのケース内面の側面に配設することによ
り、スペースを有効利用して、耐電力の大きなダミー抵
抗を構成するものである。しかも、小型のまま集中定数
型アイソレータを構成することが出来る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a dummy resistor is used as a chip resistor formed on a substrate, and the chip resistor is disposed on a side surface of an inner surface of a case of a lumped-constant isolator, thereby making effective use of space. , Constituting a dummy resistor having a large withstand power. In addition, a lumped-constant isolator can be configured with a small size.

【0009】また、基板上に印刷してダミー抵抗を構成
しているため、ダミー抵抗を薄型に形成できるととも
に、基板をケースに固定すると同時に、ダミー抵抗の一
端をアース接続する事ができる。このとき、ケースに固
定される面には、ほぼ全面に電極パターンを形成し、ほ
ぼ全面でケースと接続されることにより、放熱性を高め
ることが出来る。また基板としては、アルミナ基板を用
いる事が望ましい。このアルミナ基板では、放熱性が高
く、耐電力の大きいダミー抵抗を構成できる。もちろ
ん、このダミー抵抗の形成される基板は、静電容量の形
成される誘電体基板とは、別のものである。また、基板
の一面の端部のアース電極パターンと基板裏面のアース
電極パターンとは、側面のスルーホールで接続すること
ができる。もちろん、他の接続方法であっても良い。ま
た、ダミー抵抗を2つの抵抗を並列に接続する構成とす
る事により、耐電力の大きいダミー抵抗を構成できる。
Further, since the dummy resistor is formed by printing on the substrate, the dummy resistor can be formed thin, and the substrate can be fixed to the case and one end of the dummy resistor can be grounded. At this time, the electrode pattern is formed on substantially the entire surface of the surface fixed to the case, and connected to the case on almost the entire surface, so that heat radiation can be improved. It is desirable to use an alumina substrate as the substrate. In this alumina substrate, a dummy resistor having high heat dissipation and high power durability can be formed. Of course, the substrate on which the dummy resistor is formed is different from the dielectric substrate on which the capacitance is formed. Further, the ground electrode pattern on one end of the substrate and the ground electrode pattern on the back surface of the substrate can be connected by through holes on the side surfaces. Of course, other connection methods may be used. Further, by using a configuration in which two resistors are connected in parallel to each other, a dummy resistor having high power durability can be configured.

【0010】また本発明の集中定数型アイソレータの好
ましい構成は、ケース、誘電体基板、ガーネット、中心
導体、永久磁石、ダミー抵抗である。ケースは、アース
接続されるとともに、アイソレータ全体を包む様に構成
され、シールドケースとしての効果も有り、上下に分割
されている。誘電体基板は、静電容量を形成するもので
あり、ケース上に配置され、ガーネットが収納される穴
を有している。中心導体は、ガーネット上に、互いに絶
縁された少なくとも3つの中心導体を有し、一端は前記
の静電容量に接続され、他端はアース接続される。永久
磁石は、ガーネットに直流磁界を印加するためのもので
ある。そして、ダミー抵抗はケース側面に配置され、一
つの中心導体が接続される。又、ケースと誘電体基板の
間にアース板を配置してもよく、ケースの下に、実装用
のプリント基板を配置しても良い。
A preferred configuration of the lumped constant type isolator of the present invention is a case, a dielectric substrate, a garnet, a center conductor, a permanent magnet, and a dummy resistor. The case is connected to the ground and is configured to wrap the entire isolator, and has an effect as a shield case, and is divided into upper and lower parts. The dielectric substrate forms a capacitance, is disposed on a case, and has a hole for accommodating garnet. The center conductor has at least three center conductors insulated from each other on the garnet, one end of which is connected to the capacitance, and the other end of which is grounded. The permanent magnet is for applying a DC magnetic field to the garnet. Then, the dummy resistor is arranged on the side surface of the case, and one central conductor is connected. Further, an earth plate may be arranged between the case and the dielectric substrate, and a printed circuit board for mounting may be arranged below the case.

【0011】[0011]

【実施例】本発明に係る一実施例の構成分解斜視図を図
1に示す。この実施例の構造を説明する。まず、ニッケ
ルメッキが施された上ケース1と、永久磁石2と、中心
導体部3と、誘電体基板7と、アース板10と、ニッケ
ルメッキされた下ケース12と、プリント基板13とか
ら構成されている。この中心導体部3は、円板状のフェ
ライトコア(ガーネット)4を包むように中心導体5が
折り重ねられて、その先端が端子6a、6b、6cとし
て形成されている。そして、下ケース12の上にアース
板10、誘電体基板7を重ねて配置し、その誘電体基板
7の中央の穴8に中心導体部3のフェライトコア4が挿
入されるように配置される。
FIG. 1 is an exploded perspective view showing the construction of an embodiment according to the present invention. The structure of this embodiment will be described. First, a nickel-plated upper case 1, a permanent magnet 2, a center conductor 3, a dielectric substrate 7, a ground plate 10, a nickel-plated lower case 12, and a printed circuit board 13 Have been. The center conductor 3 is formed by folding a center conductor 5 so as to enclose a disk-shaped ferrite core (garnet) 4, and the ends of the center conductor 5 are formed as terminals 6a, 6b, and 6c. Then, the ground plate 10 and the dielectric substrate 7 are arranged on the lower case 12 so as to overlap with each other, and the ferrite core 4 of the center conductor 3 is inserted into the center hole 8 of the dielectric substrate 7. .

【0012】この下ケース12の側面には、チップ抵抗
17が半田付けされている。このチップ抵抗17の正面
図を図2に、裏面図を図3に示す。このチップ抵抗17
は、中心導体に接続される電極パターン18が基板の一
面の中央に2つ形成されており、この電極パターン18
と両側の端部のアース電極パターン20との間に抵抗パ
ターン19が形成され、この抵抗パターン19はオーバ
ーガラスにより絶縁されている。また、このチップ抵抗
17の裏面は、全面にアース電極パターン21が形成さ
れており、側面のスルーホール22で前記一面の両端端
部のアース電極パターンと接続されている。そして、中
心導体5から伸びる端子6aを誘電体基板7に形成され
ている静電容量形成用の電極9aに接合させ、更にチッ
プ抵抗17の電極パターン18に接合する。このチップ
抵抗17は、2つの抵抗を並列に接続して構成されてい
る。それぞれ100Ωであり、並列接続で、50Ωとし
ている。また、この中央の中心導体に接続される電極パ
ターンは、各抵抗パターン毎に別れていることが好まし
い。
A chip resistor 17 is soldered to a side surface of the lower case 12. FIG. 2 is a front view of the chip resistor 17, and FIG. This chip resistor 17
Has two electrode patterns 18 connected to the center conductor at the center of one surface of the substrate.
A resistance pattern 19 is formed between the resistor pattern 19 and the ground electrode patterns 20 at both ends, and the resistance pattern 19 is insulated by overglass. A ground electrode pattern 21 is formed on the entire back surface of the chip resistor 17, and is connected to ground electrode patterns at both ends of the one surface through through holes 22 on the side surface. Then, the terminal 6 a extending from the center conductor 5 is joined to the capacitance forming electrode 9 a formed on the dielectric substrate 7, and further joined to the electrode pattern 18 of the chip resistor 17. The chip resistor 17 is configured by connecting two resistors in parallel. Each is 100Ω, and is 50Ω in parallel connection. Further, it is preferable that the electrode pattern connected to the center conductor at the center is separated for each resistance pattern.

【0013】また、下ケース12の下側には、アース電
極14が形成されているプリント基板13が接合され
る。そして、中心導体5から伸びる端子6b、6cを誘
電体基板7に形成されている静電容量形成用の電極9
b、9cに接合させ、更に折り曲げてプリント基板13
の裏側へ折り返されている。また、アース板10にも突
片11が形成されており、更に折り曲げてプリント基板
13の裏側へ折り返されている。このプリント基板13
の裏面の平面図を図4に示す。このプリント基板13の
裏面には、各中心導体5から伸びる端子6b、6cを接
続する電極部15とアース板10の突片11を接続する
アース用電極部16とが形成されており、各端子の固定
と面実装化を可能としている。そして、永久磁石2が固
定された上ケース1を下ケース12にはめ込んで、集中
定数型アイソレータを構成している。この構成により、
外形が7mm角の小型のアイソレータを構成できた。
A printed circuit board 13 on which a ground electrode 14 is formed is joined to the lower side of the lower case 12. The terminals 6 b and 6 c extending from the center conductor 5 are connected to the electrodes 9 for forming the capacitance formed on the dielectric substrate 7.
b, 9c, and further bent to make the printed circuit board 13
Is folded back. A protruding piece 11 is also formed on the ground plate 10, and is further bent and folded back to the back side of the printed circuit board 13. This printed circuit board 13
FIG. 4 shows a plan view of the back surface of FIG. On the rear surface of the printed circuit board 13, an electrode portion 15 for connecting the terminals 6b and 6c extending from each central conductor 5 and an earth electrode portion 16 for connecting the protruding piece 11 of the earth plate 10 are formed. And surface mounting are possible. Then, the upper case 1 to which the permanent magnets 2 are fixed is fitted into the lower case 12 to constitute a lumped constant type isolator. With this configuration,
A small isolator with an outer shape of 7 mm square was constructed.

【0014】この実施例では、800MHz用の集中定
数型アイソレータであり、挿入損失が0.7dB、アイ
ソレーションが15dBで、耐電力2Wの特性を達成で
きた。また、本発明と同様の構成にて、7mm角の1.
9GHz用の集中定数型アイソレータであり、挿入損失
が0.6dB、アイソレーションが15dBで、耐電力
2Wの特性を達成できた。
In this embodiment, a lumped-constant isolator for 800 MHz is used. The insertion loss is 0.7 dB, the isolation is 15 dB, and the characteristics of withstand power of 2 W can be achieved. Further, in the same configuration as the present invention, a 7 mm square 1.
This is a lumped-constant isolator for 9 GHz, with an insertion loss of 0.6 dB, an isolation of 15 dB, and a characteristic of withstand power of 2 W.

【0015】本発明では、チップ抵抗をケース内側側面
に半田付けで固定し、チップ抵抗を固定することと、ダ
ミー抵抗のアース接続を同時に行う事が出来る。また、
従来使用されていなかったケース側面を使用することに
より、従来よりも大きなダミー抵抗を集中定数型アイソ
レータ内部に構成でき、しかも従来の誘電体基板上に形
成するよりもはるかに放熱性の高いアルミナ基板上にチ
ップ抵抗を配設するが可能となり、耐電力の大きいダミ
ー抵抗を構成できた。しかも集中定数型を小型のままで
行なうことが出来た。また、上記実施例では、7mm角
の集中定数型アイソレータを構成したが、本発明では、
特に小型(10mm角以下)の集中定数型アイソレータ
において有効である。
In the present invention, the chip resistor is fixed to the inner side surface of the case by soldering, so that the chip resistor can be fixed and the ground connection of the dummy resistor can be simultaneously performed. Also,
By using a case side that has not been used in the past, a larger dummy resistor can be configured inside the lumped-constant isolator than before, and the alumina substrate has much higher heat dissipation than a conventional dielectric substrate. A chip resistor can be provided on the upper portion, and a dummy resistor having a large power resistance can be formed. In addition, the lumped constant type can be performed with a small size. In the above embodiment, the lumped-constant isolator of 7 mm square is configured.
In particular, it is effective for a compact (10 mm square or less) lumped-constant isolator.

【0016】[0016]

【発明の効果】本発明により、耐電力が大きく、小型の
集中定数型アイソレータを得ることができ、例えば携帯
電話等においてミスマッチングによる耐反射電力の増加
によるアンプの保護に、極めて有効なものである。
According to the present invention, it is possible to obtain a small lumped-constant type isolator having a large withstand power and a very effective protection for an amplifier, for example, in a cellular phone or the like by increasing the anti-reflection power due to mismatching. is there.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る一実施例の構成分解斜視図であ
る。
FIG. 1 is an exploded perspective view of a configuration of an embodiment according to the present invention.

【図2】本発明に係る一チップ抵抗の正面図である。FIG. 2 is a front view of a one-chip resistor according to the present invention.

【図3】本発明に係る一チップ抵抗の裏面図である。FIG. 3 is a rear view of the one-chip resistor according to the present invention.

【図4】本発明に係る一実施例のプリント基板の裏面の
平面図である。
FIG. 4 is a plan view of the back surface of the printed circuit board according to one embodiment of the present invention.

【図5】従来例の分解斜視図である。FIG. 5 is an exploded perspective view of a conventional example.

【符号の説明】[Explanation of symbols]

1 上ケース 2 永久磁石 3 中心導体部 4 フェライトコア 5 中心導体 6 端子 7 誘電体基板 9 静電容量形成用電極 10 アース板 12 下ケース 13 プリント基板 17 チップ抵抗 18 電極パターン 19 抵抗パターン 20、21 アース電極パターン 22 スルーホール DESCRIPTION OF SYMBOLS 1 Upper case 2 Permanent magnet 3 Center conductor part 4 Ferrite core 5 Center conductor 6 Terminal 7 Dielectric substrate 9 Electrode for capacitance formation 10 Ground plate 12 Lower case 13 Printed circuit board 17 Chip resistor 18 Electrode pattern 19 Resistance pattern 20, 21 Earth electrode pattern 22 Through hole

フロントページの続き (51)Int.Cl.6 識別記号 FI H05K 1/16 H05K 1/16 C Continued on the front page (51) Int.Cl. 6 Identification code FI H05K 1/16 H05K 1/16 C

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 集中定数型アイソレータ用ダミー抵抗に
おいて、前記ダミー抵抗は、基板上に抵抗パターンを形
成して構成されたチップ抵抗であり、前記集中定数型ア
イソレータのケース内側の側面に配設されることを特徴
とする集中定数型アイソレータ用ダミー抵抗。
In a lumped-constant isolator dummy resistor, the dummy resistor is a chip resistor formed by forming a resistor pattern on a substrate, and is disposed on a side surface inside a case of the lumped-constant isolator. A dummy resistor for a lumped-constant isolator, characterized in that:
【請求項2】 前記ダミー抵抗は、前記基板の一面の中
央部に中心導体が接続される電極パターンを有し、該基
板の一面の両端端部にアース電極パターンを有し、該ア
ース電極パターンは該基板の裏面に形成されたアース電
極パターンに導通し、前記中心導体が接続される電極パ
ターンと端部のアース電極パターンの間にそれぞれ抵抗
パターンが形成され、前記基板中央部の電極パターンに
前記中心導体が接続され、前記基板の裏面のアース電極
パターンが前記ケース内側側面に接続され、2つの抵抗
が並列に接続される構成となっていることを特徴とする
請求項1記載の集中定数型アイソレータ用ダミー抵抗。
2. The dummy resistor has an electrode pattern to which a central conductor is connected at the center of one surface of the substrate, and has ground electrode patterns at both ends of one surface of the substrate. Is electrically connected to the ground electrode pattern formed on the back surface of the substrate, a resistance pattern is formed between the electrode pattern to which the center conductor is connected and the ground electrode pattern at the end, and the electrode pattern at the center of the substrate is formed. The lumped constant according to claim 1, wherein the central conductor is connected, a ground electrode pattern on the back surface of the substrate is connected to the inner side surface of the case, and two resistors are connected in parallel. Dummy resistor for type isolator.
JP09862198A 1998-04-10 1998-04-10 Dummy resistor for lumped constant type isolator Expired - Lifetime JP3209418B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09862198A JP3209418B2 (en) 1998-04-10 1998-04-10 Dummy resistor for lumped constant type isolator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09862198A JP3209418B2 (en) 1998-04-10 1998-04-10 Dummy resistor for lumped constant type isolator

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP15733395A Division JPH098509A (en) 1995-06-23 1995-06-23 Lumped constant type isolator

Publications (2)

Publication Number Publication Date
JPH10261904A true JPH10261904A (en) 1998-09-29
JP3209418B2 JP3209418B2 (en) 2001-09-17

Family

ID=14224631

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3209418B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002305403A (en) * 2001-04-04 2002-10-18 Matsushita Electric Ind Co Ltd Non-reciprocal circuit element
KR20040013730A (en) * 2002-08-08 2004-02-14 셀레콤 주식회사 High bandwidth and power termination, and register using RF cable
KR100431502B1 (en) * 1999-11-30 2004-05-14 가부시키가이샤 무라타 세이사쿠쇼 Nonreciprocal Circuit Device, Communication Apparatus and Method for Manufacturing Nonreciprocal Circuit Device
US6765453B2 (en) 2001-04-04 2004-07-20 Matsushita Electric Industrial Co., Ltd. Non-reciprocal circuit device having a thermal conductor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100431502B1 (en) * 1999-11-30 2004-05-14 가부시키가이샤 무라타 세이사쿠쇼 Nonreciprocal Circuit Device, Communication Apparatus and Method for Manufacturing Nonreciprocal Circuit Device
JP2002305403A (en) * 2001-04-04 2002-10-18 Matsushita Electric Ind Co Ltd Non-reciprocal circuit element
US6765453B2 (en) 2001-04-04 2004-07-20 Matsushita Electric Industrial Co., Ltd. Non-reciprocal circuit device having a thermal conductor
JP4507436B2 (en) * 2001-04-04 2010-07-21 パナソニック株式会社 Non-reciprocal circuit element
KR20040013730A (en) * 2002-08-08 2004-02-14 셀레콤 주식회사 High bandwidth and power termination, and register using RF cable

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