JPH10261732A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH10261732A JPH10261732A JP6517397A JP6517397A JPH10261732A JP H10261732 A JPH10261732 A JP H10261732A JP 6517397 A JP6517397 A JP 6517397A JP 6517397 A JP6517397 A JP 6517397A JP H10261732 A JPH10261732 A JP H10261732A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- ball
- lead frame
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置のパッケ
ージに関し、特にＢＧＡ（Ｂａｌｌ ＧｒｉｄＡｒｒａ
ｙ．ボール・グリッド・アレイ）またはＢＧＡタイプの
ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ．チップ
・サイズ・パッケージ或いはＣｈｉｐＳｃａｌｅ Ｐａ
ｃｋａｇｅ．チップ・スケール・パッケージ）に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package, and more particularly to a BGA (Ball Grid Array).
y. Ball Grid Array (BGA) or BGA type CSP (Chip Size Package. Chip Size Package or ChipScale Pa)
cage. Chip scale package).
【０００２】[0002]
【従来の技術】リードフレームをインターポーザーに用
いたＢＧＡの例としては特開平８−８３８７８がある。
断面図を図２として示す。図２において、１はＩＣチッ
プ、２はリードフレーム、３は絶縁接着剤、４はワイ
ヤ、５は樹脂、６は半田ボールである。2. Description of the Related Art An example of a BGA using a lead frame as an interposer is disclosed in JP-A-8-83878.
A cross-sectional view is shown in FIG. In FIG. 2, 1 is an IC chip, 2 is a lead frame, 3 is an insulating adhesive, 4 is a wire, 5 is a resin, and 6 is a solder ball.
【０００３】特開平８−８３８７８に述べられた実施例
によれば、リードフレームとＩＣチップの接着は、リー
ドフレーム２上面に半硬化状態のポリイミド系若しくは
エポキシ系の絶縁接着剤３を塗布し、その上にＩＣチッ
プ１を載せてから絶縁接着剤を熱硬化させて接着すると
している。According to the embodiment described in JP-A-8-83878, the bonding between the lead frame and the IC chip is performed by applying a semi-cured polyimide or epoxy insulating adhesive 3 on the upper surface of the lead frame 2. It is stated that the IC chip 1 is mounted thereon, and then the insulating adhesive is thermally cured to bond.
【０００４】[0004]
【発明が解決しようとする課題】上記方法では、第１に
リードフレームとＩＣチップとの絶縁を再現性よく保証
する事が困難であり、第２にリードフレームの配線が細
く且つ薄いため、しなってバラバラするので扱い難いと
いう課題があった。In the above method, firstly, it is difficult to guarantee the insulation between the lead frame and the IC chip with good reproducibility, and secondly, the wiring of the lead frame is thin and thin. There was a problem that it was difficult to handle because it fell apart.
【０００５】本発明の目的は、第１にリードフレームと
ＩＣチップとの絶縁を再現性よく確実にすること、第２
にリードフレームの配線がバラつかず扱い易くする事で
ある。It is an object of the present invention to firstly ensure insulation between a lead frame and an IC chip with good reproducibility;
In addition, the wiring of the lead frame does not vary, and it is easy to handle.
【０００６】[0006]
【課題を解決するための手段】本発明による半導体装置
においては、複数の配線と複数のボールランドとを備え
た金属配線層と、複数の電極パッドを備え、絶縁性接着
膜により該金属配線層の第１面に接着された半導体素子
と、該電極パッドと該配線とを接続する金属細線と、該
半導体素子と該金属細線と該絶縁性接着膜と該金属配線
層との接合体の表面のうち少なくとも、該金属配線層の
第１面側と、該金属配線層の第１面と反対の第２面のう
ち該ボールランドの部分を除いた面を覆う樹脂と、該ボ
ールランドの該樹脂に覆われていない面に接着し、該樹
脂表面から突出した複数のボール電極とから成る半導体
装置において、該絶縁性接着膜が、樹脂薄膜と、該樹脂
薄膜の該金属配線層と接着する側に塗布された熱硬化性
接着剤と、該樹脂薄膜の該半導体素子と接着する側に塗
布された熱可塑性接着剤とから成ることを特徴とする。A semiconductor device according to the present invention includes a metal wiring layer having a plurality of wirings and a plurality of ball lands, a plurality of electrode pads, and a metal wiring layer having an insulating adhesive film. A semiconductor element bonded to the first surface, a thin metal wire connecting the electrode pad and the wiring, and a surface of a joined body of the semiconductor element, the thin metal wire, the insulating adhesive film, and the metal wiring layer A resin covering at least a first surface side of the metal wiring layer, a second surface opposite to the first surface of the metal wiring layer, excluding a portion of the ball land; In a semiconductor device comprising a plurality of ball electrodes bonded to a surface not covered with resin and projecting from the resin surface, the insulating adhesive film is bonded to a resin thin film and the metal wiring layer of the resin thin film. Thermosetting adhesive applied to the side and the resin Characterized in that it consists of a thermoplastic adhesive applied on the side of bonding with the semiconductor device of the film.
【０００７】また、本発明による半導体装置の製造方法
においては、複数の配線と複数のボールランドとを備え
たリードフレームの第１面と、おもて面に熱可塑性接着
剤が塗布された樹脂薄膜のうら面とを熱硬化性接着剤に
より接着する工程と、該樹脂薄膜のおもて面に複数の電
極パッドを備えた半導体素子を搭載し、加熱して熱可塑
性接着剤により接着する工程と、該電極パッドと該配線
とを金属細線により接続する工程と、該半導体素子と該
金属細線と該絶縁性接着膜と該リードフレームとの接合
体の表面のうち少なくとも、該リードフレームの第１面
側と、該リードフレームの第１面と反対の第２面のうち
該ボールランドの部分を除いた面を樹脂により覆う工程
と、該ボールランドの該樹脂に覆われていない面に金属
ボールを熔着して複数のボール電極を形成する工程と、
該リードフレームの該樹脂からはみ出した部分を切除す
る工程とから成ることを特徴とする。In the method of manufacturing a semiconductor device according to the present invention, a resin having a first surface of a lead frame having a plurality of wirings and a plurality of ball lands, and a front surface coated with a thermoplastic adhesive is provided. A step of bonding the back surface of the thin film with a thermosetting adhesive, and a step of mounting a semiconductor element having a plurality of electrode pads on the front surface of the resin thin film and heating and bonding with a thermoplastic adhesive. Connecting the electrode pad and the wiring with a thin metal wire, and at least a surface of the joined body of the semiconductor element, the thin metal wire, the insulating adhesive film, and the lead frame, A step of covering the one surface side and the second surface opposite to the first surface of the lead frame excluding the ball land portion with a resin; Weld the ball Forming a ball electrode number,
Cutting off the portion of the lead frame that protrudes from the resin.
【０００８】[0008]
【発明の実施の形態】本発明を実施例をもとに詳細に説
明する。図１は本発明の一実施例で、半導体装置の断面
図である。図１において、１はＩＣチップ（半導体素
子）、２ａは金属配線層で後述するリードフレーム２の
樹脂５内に封止された部分である。さらに、３は樹脂薄
膜、３ａは熱可塑性接着剤、３ｂは熱硬化性接着剤であ
り、樹脂薄膜３、熱可塑性接着剤３ａ、熱硬化性接着剤
３ｂで絶縁性接着膜を形成している。４は金ワイヤ（金
属細線）、５は樹脂、６はボール電極（半田ボール）で
ある。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail based on embodiments. FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an IC chip (semiconductor element), and reference numeral 2a denotes a metal wiring layer which is sealed in a resin 5 of a lead frame 2 described later. Further, 3 is a resin thin film, 3a is a thermoplastic adhesive, 3b is a thermosetting adhesive, and an insulating adhesive film is formed by the resin thin film 3, the thermoplastic adhesive 3a, and the thermosetting adhesive 3b. . Reference numeral 4 denotes a gold wire (fine metal wire), 5 denotes a resin, and 6 denotes a ball electrode (solder ball).
【０００９】本発明の半導体装置の製造方法を説明す
る。まず、リードフレーム２を用意する。このリードフ
レーム２の平面形状を図４に示す。図４において、２１
は後に金属ボールを熔着するためのボールランド、２２
は配線、２３は配線の一部で後に金属細線をボンディン
グする部分、２５は樹脂封止工程において樹脂の流れ止
めとするダムバーである。リードフレームの材料として
は、最も一般的に用いられていてコストも安い４２アロ
イや銅アロイなどでよい。リードフレームの製造にあた
っても特別のことは必要なく、半導体のプラスチックパ
ッケージ（ＱＦＰ、ＳＯＰ、ＰＬＣＣなど）に用いられ
るリードフレームと同様に製造できる。A method for manufacturing a semiconductor device according to the present invention will be described. First, the lead frame 2 is prepared. FIG. 4 shows the plan shape of the lead frame 2. In FIG.
Is a ball land for welding a metal ball later, 22
Is a wiring, 23 is a part of the wiring, to which a fine metal wire is to be bonded later, and 25 is a dam bar for preventing resin from flowing in the resin sealing step. As a material for the lead frame, a 42 alloy, a copper alloy, or the like, which is most commonly used and is inexpensive, may be used. There is no special need for manufacturing the lead frame, and the lead frame can be manufactured in the same manner as a lead frame used for a semiconductor plastic package (QFP, SOP, PLCC, etc.).
【００１０】一方、耐熱性樹脂薄膜を用意し、そのおも
て面に熱可塑性接着剤を塗布したのち加熱して溶剤を除
去し、熱可塑性接着剤層３ａを形成する。On the other hand, a heat-resistant resin thin film is prepared, a thermoplastic adhesive is applied to its front surface, and then heated to remove the solvent, thereby forming a thermoplastic adhesive layer 3a.
【００１１】次に図３（ａ）に示すように、樹脂薄膜３
のうら面又はリードフレーム２のＩＣチップ搭載側の面
にエポキシ系の熱硬化性樹脂３ｂを塗布し、樹脂薄膜３
のうら面とリードフレーム２のＩＣチップ搭載側の面を
接触させ、１００〜２００℃で１〜２時間程度加熱して
硬化させ、樹脂薄膜３のうら面とリードフレーム２のＩ
Ｃチップ搭載側の面を貼り合わせる。Next, as shown in FIG.
An epoxy thermosetting resin 3b is applied to the back surface or the surface of the lead frame 2 on the IC chip mounting side, and the resin thin film 3
The back surface of the lead frame 2 is brought into contact with the surface of the lead frame 2 on the IC chip mounting side, and is heated and cured at 100 to 200 ° C. for about 1 to 2 hours.
Attach the surface on the C chip mounting side.
【００１２】次に図３（ｂ）に示すように、樹脂薄膜３
上にＩＣチップ１を載せ、２５０〜３５０℃で１〜１０
秒程度加熱して接着する。リードフレーム２とＩＣチッ
プ１の間に樹脂薄膜３があるので電気的な絶縁を再現性
よく確保できる。Next, as shown in FIG.
Place IC chip 1 on the top
Heat for about a second to bond. Since the resin thin film 3 exists between the lead frame 2 and the IC chip 1, electrical insulation can be ensured with good reproducibility.
【００１３】次に図３（ｃ）に示すように、ＩＣチップ
１上の電極パッドとリードフレーム２の配線の一部分２
３とを金ワイヤ（金属細線）４で接続する。このとき超
音波併用熱圧着法を用いても、リードフレームは４２ア
ロイや銅アロイなどでできているため加熱しても軟化す
ることはなく、超音波は十分効くので必要十分な接合強
度が得られる。ワイヤボンディングが終わった接合体
（ＩＣチップ、絶縁性接着膜、金ワイヤ）を上から見た
図を図５として示す。図５において、５０は後に形成さ
れる樹脂の外形線である。Next, as shown in FIG. 3C, the electrode pads on the IC chip 1 and a part 2 of the wiring of the lead frame 2 are formed.
3 are connected by a gold wire (a thin metal wire) 4. At this time, even if the thermocompression bonding method using ultrasonic waves is used, since the lead frame is made of 42 alloy or copper alloy, it does not soften even when heated, and the ultrasonic waves are sufficiently effective, so that necessary and sufficient bonding strength is obtained. Can be FIG. 5 shows a top view of the joined body (IC chip, insulating adhesive film, gold wire) after wire bonding. In FIG. 5, reference numeral 50 denotes an outline of a resin to be formed later.
【００１４】次に図３（ｄ）に示すように、前記の接合
体をリードフレームのボールランド２１が下金型３１の
突起部３５に当接するように載せ、その上から上金型３
０を載せてリードフレームを上下金型で挟み、ゲート３
４から液化した樹脂を注入し硬化させる。図６に下金型
を斜め上方から見た俯瞰図を示す。下金型３１の内壁下
面には突起３５が設けられていて、この突起がリードフ
レームのボールランド２１に当たった状態で樹脂が注入
されるため、樹脂が硬化したときボールランドの下面が
樹脂から露出する。Next, as shown in FIG. 3 (d), the joined body is placed so that the ball lands 21 of the lead frame are in contact with the projections 35 of the lower mold 31, and the upper mold 3 is placed from above.
0, put the lead frame between the upper and lower molds,
The liquefied resin is injected from Step 4 and cured. FIG. 6 is a bird's-eye view of the lower mold as viewed from obliquely above. A projection 35 is provided on the lower surface of the inner wall of the lower mold 31, and the resin is injected in a state where the projection is in contact with the ball land 21 of the lead frame. Exposed.
【００１５】次に図３（ｅ）に示すように、樹脂５から
露出したボールランドに半田ボールを熔着して外部電極
とする。ボールランドにフラックスを塗布し、その上に
半田ボール４０を載せ、半田の融点以上に加熱して接着
させたのち、フラックスを洗い流す。本発明のパッケー
ジでは、ボールランドの周りに摺り鉢状の壁を持った樹
脂の丘があるため、フラックスをランド毎に分離し易
く、また半田ボール同士が過度に近接するのを防ぐの
で、半田ボール溶融時に複数の半田ボールが合体してし
まう不具合を防止することが容易である。また別法とし
て、スクリーン印刷などによりボールランド上に半田ペ
ーストを塗布したのち、加熱溶融してボール電極を形成
することもできる。Next, as shown in FIG. 3E, solder balls are welded to the ball lands exposed from the resin 5 to form external electrodes. A flux is applied to the ball land, a solder ball 40 is placed thereon, and the solder is heated to a temperature equal to or higher than the melting point of the solder, and then the flux is washed away. In the package of the present invention, since there is a resin hill having a mortar-shaped wall around the ball land, it is easy to separate the flux for each land, and to prevent the solder balls from being excessively close to each other. It is easy to prevent a defect that a plurality of solder balls are united when the balls are melted. Alternatively, a ball electrode can be formed by applying a solder paste on a ball land by screen printing or the like, and then heating and melting the solder paste.
【００１６】次に図３（ｆ）に示すように、リードフレ
ームの樹脂５からはみ出した部分２ｂを切除する。２ａ
は樹脂外形内に残ったリードフレームの部分、２ｃはリ
ードフレームの切断面である。Next, as shown in FIG. 3 (f), the portion 2b of the lead frame that protrudes from the resin 5 is cut off. 2a
Denotes a portion of the lead frame remaining in the outer shape of the resin, and 2c denotes a cut surface of the lead frame.
【００１７】ＢＧＡタイプのＣＳＰを通常の有機配線基
板に実装した場合、ＣＳＰはＩＣチップの基材であるシ
リコンの熱膨張係数（約４ｐｐｍ）に近い比較的小さな
熱膨張係数を持っているのに対し、有機配線基板は約１
６ｐｐｍという比較的大きな熱膨張係数を持っているの
で、温度変化によりＣＳＰと配線基板を接合している半
田ボールに通常のＢＧＡよりも大きな応力がかかる。イ
ンターポーザーに有機配線基板を用いた通常のＢＧＡに
おいては、半田ボールの材料として共晶半田を用いるの
が一般的であるが、ＣＳＰにおいては耐応力性が優れた
インジウムやアンチモンを含んだ半田を用いるのが好
い。When a BGA-type CSP is mounted on a normal organic wiring board, the CSP has a relatively small coefficient of thermal expansion (about 4 ppm) close to that of silicon as a base material of an IC chip. On the other hand, about 1 organic circuit board
Since it has a relatively large coefficient of thermal expansion of 6 ppm, a larger stress is applied to the solder ball joining the CSP and the wiring board than a normal BGA due to a temperature change. In a normal BGA using an organic wiring board as an interposer, it is common to use eutectic solder as a material for a solder ball, but in a CSP, a solder containing indium or antimony having excellent stress resistance is used. It is preferable to use.
【００１８】[0018]
【発明の効果】第１に、リードフレームとＩＣチップの
接着に樹脂薄膜を介在させているので、絶縁性が再現性
よく保証され、製造歩留まりが良く、信頼性の高い半導
体装置を得ることができる。First, since a resin thin film is interposed between the lead frame and the IC chip, the insulating property is assured with good reproducibility, and the manufacturing yield is good and a highly reliable semiconductor device can be obtained. it can.
【００１９】第２に、リードフレームの細くて薄い配線
が、樹脂薄膜と接着固定されることにより、バラつかず
扱い易くなった。Second, the thin and thin wiring of the lead frame is adhered and fixed to the resin thin film, so that it is easy to handle without variation.
【００２０】第３に、本発明のパッケージでは、外部電
極に耐応力性が優れたインジウムやアンチモンを含んだ
半田を用いたので、有機配線基板に実装した場合の接合
信頼性が高い。Third, in the package of the present invention, since solder containing indium or antimony having excellent stress resistance is used for the external electrodes, the bonding reliability when mounted on an organic wiring board is high.
【図１】本発明の実施例で、半導体装置の断面図。FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
【図２】従来技術の例で、半導体装置の断面図。FIG. 2 is a cross-sectional view of a semiconductor device in an example of the related art.
【図３】本発明の実施例で、半導体装置の製造方法を説
明する図。FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device in an example of the present invention.
【図４】本発明の実施例で、リードフレーム要部の平面
図。FIG. 4 is a plan view of a main part of a lead frame according to the embodiment of the present invention.
【図５】本発明の実施例で、半導体装置製造工程のワイ
ヤボンディング終了状態を示す平面図。FIG. 5 is a plan view showing a completed state of wire bonding in a semiconductor device manufacturing process in the embodiment of the present invention.
【図６】本発明の実施例で、下金型の俯瞰図。FIG. 6 is an overhead view of a lower mold according to the embodiment of the present invention.
１ ＩＣチップ（半導体素子） ２ リードフレーム ２ａ 金属配線層（リードフレームの樹脂封止された部
分） ２ｂ リードフレームの樹脂封止後に切除された部分 ２ｃ リードフレームの切断面 ３ 樹脂薄膜 ３ａ 熱可塑性接着剤 ３ｂ 熱硬化性接着剤 ４ 金ワイヤ（金属細線） ５ 樹脂 ６ ボール電極（半田ボール） ２１ ボールランド ２２ 配線 ２３ 配線の一部で金属細線をボンディングする部分 ２５ ダムバー ３０ 上金型 ３１ 下金型 ３４ ゲート ３５ 突起部 ４０ 半田ボール ５０ 樹脂の外形線Reference Signs List 1 IC chip (semiconductor element) 2 Lead frame 2a Metal wiring layer (resin-sealed part of lead frame) 2b Part cut off after resin sealing of lead frame 2c Cut surface of lead frame 3 Resin thin film 3a Thermoplastic bonding Agent 3b Thermosetting adhesive 4 Gold wire (thin metal wire) 5 Resin 6 Ball electrode (solder ball) 21 Ball land 22 Wiring 23 Part where thin metal wire is bonded in part of wiring 25 Dam bar 30 Upper die 31 Lower die 34 Gate 35 Projection 40 Solder ball 50 Outline of resin
Claims (9)
た金属配線層と、複数の電極パッドを備え、絶縁性接着
膜により該金属配線層の第１面に接着された半導体素子
と、該電極パッドと該配線とを接続する金属細線と、該
半導体素子と該金属細線と該絶縁性接着膜と該金属配線
層との接合体の表面のうち少なくとも、該金属配線層の
第１面側と、該金属配線層の第１面と反対の第２面のう
ち該ボールランドの部分を除いた面を覆う樹脂と、該ボ
ールランドの該樹脂に覆われていない面に接着し、該樹
脂表面から突出した複数のボール電極とから成る半導体
装置において、該絶縁性接着膜が、樹脂薄膜と、該樹脂
薄膜の該金属配線層と接着する側に塗布された熱硬化性
接着剤と、該樹脂薄膜の該半導体素子と接着する側に塗
布された熱可塑性接着剤とから成ることを特徴とした半
導体装置。A semiconductor element having a plurality of wirings and a plurality of ball lands; a plurality of electrode pads; and a semiconductor element bonded to a first surface of the metal wiring layer by an insulating adhesive film; At least a first surface of the metal wiring layer among a surface of a thin metal wire connecting the electrode pad and the wiring, and a surface of a joined body of the semiconductor element, the fine metal wire, the insulating adhesive film, and the metal wiring layer; And a resin covering a surface of the metal wiring layer opposite to the first surface of the metal wiring layer except for the ball land portion, and a resin bonded to a surface of the ball land not covered with the resin, In a semiconductor device comprising a plurality of ball electrodes protruding from a resin surface, the insulating adhesive film is a resin thin film, and a thermosetting adhesive applied to a side of the resin thin film that adheres to the metal wiring layer, Thermoplastic applied to the side of the resin thin film that adheres to the semiconductor element Semiconductor device characterized by comprising a Chakuzai.
ールランドと該ボール電極の接着面が該樹脂表面の内側
にあることを特徴とした半導体装置。2. The semiconductor device according to claim 1, wherein the bonding surface between the ball land and the ball electrode is inside the resin surface.
ール電極がインジウムを含んだ半田から成ることを特徴
とした半導体装置。3. The semiconductor device according to claim 1, wherein said ball electrode is made of solder containing indium.
ール電極がアンチモンを含んだ半田から成ることを特徴
とした半導体装置。4. The semiconductor device according to claim 1, wherein said ball electrode is made of solder containing antimony.
たリードフレームの第１面と、おもて面に熱可塑性接着
剤が塗布された樹脂薄膜のうら面とを熱硬化性接着剤に
より接着する工程と、該樹脂薄膜のおもて面に複数の電
極パッドを備えた半導体素子を搭載し、加熱して熱可塑
性接着剤により接着する工程と、該電極パッドと該配線
とを金属細線により接続する工程と、該半導体素子と該
金属細線と該絶縁性接着膜と該リードフレームとの接合
体の表面のうち少なくとも、該リードフレームの第１面
側と、該リードフレームの第１面と反対の第２面のうち
該ボールランドの部分を除いた面を樹脂により覆う工程
と、該ボールランドの該樹脂に覆われていない面上に複
数のボール電極を形成する工程と、該リードフレームの
該樹脂からはみ出した部分を切除する工程とを含んで成
ることを特徴とした半導体装置の製造方法。5. A thermosetting adhesive comprising: a first surface of a lead frame having a plurality of wirings and a plurality of ball lands; and a back surface of a resin thin film having a front surface coated with a thermoplastic adhesive. Bonding a semiconductor element provided with a plurality of electrode pads on the front surface of the resin thin film, heating and bonding with a thermoplastic adhesive, and bonding the electrode pads and the wiring with a metal. Connecting the semiconductor device, the thin metal wire, the insulating adhesive film, and the lead frame at least on the first surface side of the lead frame; Covering a surface of the second surface opposite to the surface excluding the ball land portion with a resin; forming a plurality of ball electrodes on a surface of the ball land that is not covered with the resin; The lead frame protrudes from the resin The method of manufacturing a semiconductor device in which part was characterized by the comprising the step of ablating.
いて、上下２体の金型を用いて樹脂封止することを特徴
とした半導体装置の製造方法。6. The method for manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is sealed with a resin using two upper and lower molds.
いて、下金型の内面には複数の突起が配設され、該ボー
ルランドの一面が該突起に接した状態で樹脂封止するこ
とを特徴とした半導体装置の製造方法。7. A method of manufacturing a semiconductor device according to claim 6, wherein a plurality of projections are provided on an inner surface of the lower mold, and the ball land is sealed with a resin while one surface thereof is in contact with the projections. A method for manufacturing a semiconductor device, comprising:
いて、該ボールランドの該樹脂に覆われていない面上に
複数の金属ボールを熔着して複数のボール電極を形成す
ることを特徴とした半導体装置の製造方法。8. The method for manufacturing a semiconductor device according to claim 5, wherein a plurality of metal balls are welded on a surface of said ball land which is not covered with said resin to form a plurality of ball electrodes. Of manufacturing a semiconductor device.
いて、該ボールランドの該樹脂に覆われていない面上に
半田ペーストを塗布したのち加熱溶融して複数のボール
電極を形成することを特徴とした半導体装置の製造方
法。9. A method for manufacturing a semiconductor device according to claim 5, wherein a plurality of ball electrodes are formed by applying a solder paste to a surface of the ball land that is not covered with the resin and then heating and melting the solder paste. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6517397A JPH10261732A (en) | 1997-03-18 | 1997-03-18 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6517397A JPH10261732A (en) | 1997-03-18 | 1997-03-18 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10261732A true JPH10261732A (en) | 1998-09-29 |
Family
ID=13279250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6517397A Withdrawn JPH10261732A (en) | 1997-03-18 | 1997-03-18 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10261732A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003046055A (en) * | 2001-07-31 | 2003-02-14 | Sanyo Electric Co Ltd | Planar body, lead frame, and method for manufacturing semiconductor device |
-
1997
- 1997-03-18 JP JP6517397A patent/JPH10261732A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003046055A (en) * | 2001-07-31 | 2003-02-14 | Sanyo Electric Co Ltd | Planar body, lead frame, and method for manufacturing semiconductor device |
| JP4663172B2 (en) * | 2001-07-31 | 2011-03-30 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
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