JPH10261666A - Semiconductor device and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a second bond area from becoming far and to miniaturize a package at the time of bonding a wire on a surface and the back by forming a thin part at a lead tip. SOLUTION: A first semiconductor chip 10 is fixed to the first main face 15 of an island 14 and a second semiconductor chip 11 is fixed to a second main face 16. A first bonding pad 15 and the thin part 26 provided at the tip part of a lead terminal 19 are wire-bonded by a first bonding wire 23. A second bonding pad 13 and the second main face 21 of the lead terminal 19 are wire- bonded by a second bonding wire 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to miniaturization of a semiconductor device having two semiconductor chips fixed to the front and back surfaces of an island.

[0002]

2. Description of the Related Art Waves of miniaturization and weight reduction of various electronic devices are unavoidable, and semiconductor devices incorporated therein are required to have higher capacity, higher function and higher integration. Therefore, a technique for sealing a plurality of semiconductor chips in a single package, which has existed as an idea (for example, Japanese Patent Application Laid-Open No. 55-1111517), has been attracting attention, and a move toward realization has emerged.

For example, as shown in FIG. 5A, a first semiconductor chip 1a is fixed on an island 3, and a second semiconductor chip 1b is fixed on the first semiconductor chip 1a.
The corresponding bonding pad and lead 4 are connected by bonding wires 5a and 5b and sealed with resin 2 or, as shown in FIG. The chips 1a and 1b are fixed, respectively, wire-bonded, and sealed with a resin 18.

[0004]

When the semiconductor chips 1a and 1b are fixed to the front and back surfaces of the island 3, one (first semiconductor chip 1a) is wire-bonded to the other (second semiconductor chip 1a). When wire bonding is performed on the semiconductor chip 1b), it is necessary to provide a relief portion for releasing the wire on a heating stage where the work is performed so that the previously formed wire is not crushed. When the second wire bonding is performed on the lead terminal 4, a second bond must be formed in a portion where the lead terminal 4 can be fixed, that is, in a region where the lead terminal 4 and the heating stage are in contact with each other, avoiding a relief portion. Must. As a result, 2n of the second semiconductor chip 1b
There is a disadvantage that the d-bond area becomes farther than necessary from the chip, and the lateral size of the package is increased.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems. A thin portion having a reduced thickness is formed at a leading end portion of a lead terminal, and a first bonding wire is connected to the thin portion. It is an object of the present invention to provide a semiconductor device in which a 2nd bond area of a second bonding wire can be made closer to the vicinity of an island by performing a 2nd bond to a portion.

In addition, by positioning the end of the relief portion of the heating stage in such a positional relationship as to substantially coincide with the end of the thin portion, the second bonding area of the second bonding wire can be made closer to the vicinity of the island. It is intended to provide a method of manufacturing the device. According to the present invention,
Since the wire length of the second bonding wire can be shortened, the lateral dimension of the package can be reduced, or a large-sized semiconductor chip can be mounted in the same size package.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. First, FIG.
FIG. 3B is a sectional view showing the semiconductor device of the present invention, and FIG. 3 is a plan view showing the semiconductor device of the present invention. 2A is a sectional view taken along the line AA in FIG. 3, and FIG. 2B is a sectional view taken along the line BB in FIG.

In FIG. 1, reference numerals 10 and 11 denote first and second semiconductor chips, respectively. First and second semiconductor chips 1
Various active and passive circuit elements are formed on the silicon surfaces 0 and 11 in the previous process. A chip using an N-type semiconductor substrate is used as the first semiconductor chip 10, and a VDD potential is applied as a substrate potential.
A chip using a P-type semiconductor substrate is used as the second semiconductor chip, and a VSS potential is applied as a substrate potential.

A first bonding pad 12 for external connection is formed in a peripheral portion of the chip of the first semiconductor chip 10. Similarly, a second bonding pad 13 is formed on the surface of the second semiconductor chip 11. A passivation film such as a silicon nitride film, a silicon oxide film, or a polyimide-based insulating film is formed so as to cover each of the bonding pads 12a and 12b. The upper portions of the bonding pads 12a and 12b are opened for electrical connection. These semiconductor chips 10 and 11 are polished on the back surface by a back grinding process immediately before the assembling process to have a thickness of 250 to 300 μm.

The island 14 has a first main surface 1 on the back side.
5 and a second main surface 16 on the front side. On the first main surface 15 of the island 14, the first semiconductor chip 10
g is paste-bonded with an epoxy-based conductive adhesive 17 such as a paste.
The semiconductor chip 11 is fixed by an insulating epoxy adhesive 18.

The lead terminal 19 for external connection, which has a tip close to the island 14, also has a first main surface 20 on the back surface side and a second main surface 21 on the front surface side. The island 14 and the lead terminal 19 are supplied in the form of a lead frame. The lead frame is formed by etching or punching a copper or iron plate material having a plate thickness of about 130 μ to form the island 14 and the lead terminal. Each part such as the terminal 19 and the tie bar 22 is molded. This value is almost the limit value for maintaining the mechanical strength of each part. Each part is held by the frame of the lead frame until it is cut after the molding step, and the height of the island 14, the lead terminal 19, and the height of the frame coincide with each other in the held state.

A first stamping process (crushing process) or a half etching process is performed on the first main surface 20 at the leading end portion of the lead terminal 19 so that the thickness of the first main surface 20 is reduced to about half. A part 26 is provided. Then, the bonding pad 12 of the first semiconductor chip 10 and the thin portion 26 at the tip of the lead terminal 19 are wire-bonded by the first bonding wire 23, and the bonding pad 13 of the second semiconductor chip 11 and the lead terminal 19 are similarly connected. Second main surface 21 at the tip
Are wire-bonded by a second bonding wire 24.

The first and second semiconductor chips 10 and 11, the tips of the lead terminals 19, and the bonding wires 2
A main part including the parts 3 and 24 is molded around with an epoxy-based thermosetting resin 25, and is packaged in a shape having a height of about 1 mm in external dimensions. The lead terminal 19 is led out from a position about half the thickness of the resin 25 on the side wall of the package, and is lead-formed in a Z shape for surface mounting. This forming shape is a shape for surface mounting use, in which the fixed portion on the rear surface side of the lead terminal 19 is adhered to the conductive pattern formed on the printed circuit board. The island 14 is not stepped with respect to the tip of the lead terminal 19, and the two constitute a horizontal plane. Therefore, in the device after completion, the tie bar 22 holding the island 14 is also led out from the position about half the thickness of the resin 25 on the side wall of the package, and the cut surface is exposed on the surface of the resin 25 to terminate.

FIG. 4 is a cross-sectional view for explaining the die bonding and wire bonding steps of such an apparatus. FIG.
Referring to (A), first, the prepared lead frame is placed on a substantially flat stage 27, and an appropriate amount of an insulating epoxy-based adhesive is dropped on second main surface 21 of island 14 to form a vacuum collet. The second semiconductor chip 11 adsorbed on the second semiconductor chip 11 is placed on the island 14, the second semiconductor chip 11 is pressed by the collet so as to expand the adhesive on average, and the heat treatment is performed at 200 ° C. for several hours. Die bonding by solidifying the adhesive.

Referring to FIG. 4 (B), the lead frame is inverted and placed on a second stage 27 having a relief portion 28 of the second semiconductor chip 11, and a conductive adhesive such as Ag paste is also used. The first semiconductor chip 1
0 is set, and die bonding is performed by heat treatment at 200 ° C. for several hours. With reference to FIG.
The first bonding pad 1 on the first semiconductor chip 10 is set on a third heating stage 27 having
2 and the first bond is applied to the thin portion 26 of the lead terminal 19.
The first bonding wire 23 is wire-bonded by hitting a second bond on the surface. At this time, the thin portion 26
Is used as a target for automatic position recognition, the wire bonding process can be simplified.

Referring to FIG. 4D, the lead frame is moved onto a fourth heating stage 27 having a relief portion 28, and the first bonding is performed on second bonding pad 13 on second semiconductor chip 11. And the second of the lead terminals 19
The second bonding wire 24 is wire-bonded by hitting a second bond on the surface of the main surface 21. Then, the lead frame and the lead terminal 19 are positioned so that the island 14 is located in the cavity provided in the upper and lower molds.
Is sandwiched between upper and lower molds, resin is injected and cured in such a state, unnecessary portions of the lead frame are removed, and the lead 19 is removed.
The semiconductor device shown in FIG. 2 can be obtained by lead forming the tip portion of the semiconductor device.

FIG. 1A is an enlarged sectional view showing a wire portion in the step of FIG. 4D. FIG. 1B is a perspective view showing a tip end portion of the lead terminal 19. Heating stage 27
Is separated into a portion 27a that contacts the lead terminal 19 and a portion 27b that contacts the surface of the first semiconductor chip 10,
At the same time, there is provided a height difference of about the thickness of the first semiconductor chip 10, and at the same time, a relief portion 28 deeper than the loop height of the first bonding wire 23 is provided between the two. While the first bonding wire 23 is bonded 2nd to the surface of the thin portion 26, the second bonding wire 24 is bonded 2nd to the second main surface 21 of the lead terminal 19.
Bonded. At this time, the heating stage 27a
In order to avoid contact with the bonding wire 23, the first bonding wire 23 must be retracted backward in consideration of positioning variations and the like. On the other hand, the second
The lead terminal 19 cannot withstand the pressure of the capillary tool at the time of the 2nd bond unless the 2nd bond of the bonding wire 24 is directly above the heating stage 27a. In the case of the conventional first wire (dotted line 5a shown) directly bonded to the first main surface 20 by 2nd, the heating stage 27a must be retracted to about the dotted line portion 30, and as a result, the second wire (dotted line 5b shown) 2nd bond area was also located far away.

On the other hand, according to the present invention, the first main surface 20
By providing the thin portion 26, the first bonding wire 23 and the end 31 of the escape portion 28 can be vertically separated from each other. If the plate thickness of the lead terminal 19 is 130 μm, it is possible to process the depth of the thin portion 26 (t in FIG. 1B) to about half, that is, about 60 μm. Therefore the first
If the diameter of the bonding wire 23 is up to about 50 μm, the 2nd bond portion of the first bonding wire 23 is embedded in the thin portion 26 so that the wire does not protrude from the first main surface 20. Dimensional design is also possible. Accordingly, the end 31 of the escape portion 28 of the heating stage 27 is the same as the end 32 of the thin portion 26,
Side position. As a result, the second bond area of the second bonding wire 24 can be made closer to the island 14 side than before. Therefore,
Expansion of the external dimensions, particularly in the lateral direction, can be suppressed, and a larger semiconductor chip can be mounted.

The first and second semiconductor chips 10, 11
For different types of chips with different sizes as a combination of
If the small chip where the pad position is far away is the first semiconductor chip 10 and the large semiconductor chip is the second semiconductor chip 11, both the first and second bonding wires 23 and 24 are extremely extreme. Therefore, it is easy to secure reliability. Furthermore, by assembling in the order of die-bond, die-bond, wire-bond, and wire-bond, the process that involves the danger that the wire that is the most vulnerable as an assembly comes into contact with the heating stage can be completed only once, thus improving reliability. Easiness is ensured.

[0020]

As described above, according to the present invention,
By stacking a plurality of semiconductor chips 10 and 11 in one package, there is an advantage that a product of high-density mounting can be provided according to a demand for reduction in size and size of electronic equipment. Also,
When the two chips are stored, the heating stage 27 is provided by providing the thin portion 26 at the tip of the lead terminal 19.
The end 31 of the escape portion 28 can be arranged on the island 14 side, and the second bond position of the second bonding wire 24 can be designed on the island 14 side. As a result, there is an advantage that a package having a reduced outer dimension in the lateral direction can be manufactured. Also, if the external dimensions are the same,
There is an advantage that a semiconductor chip having a larger chip size can be housed in the same package.

Furthermore, the lead terminal 19 is formed by the thin portion 26.
And the first bonding wire 23 can be vertically separated from each other, so that the positioning accuracy when the lead frame is installed on the heating stage 27 can be given a margin, and a contact accident between the two can be reduced, so that the production yield can be reduced. Can be improved. Furthermore, by performing the process of die bonding, die bonding, wire bonding, and wire bonding, the process of lowering the wire can be completed only once.
This has the advantage of reducing the possibility of accidents such as wire breakage.

By using the thin portion 26 as a target for automatic position recognition, an accident such as a mistake in the wire bonding step can be prevented.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view for explaining the present invention, and FIG.
It is sectional drawing.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a plan view for explaining the present invention.

FIG. 4 is a cross-sectional view for explaining the present invention.

FIG. 5 is a sectional view for explaining a conventional example.

Claims (4)

[Claims] An island having a first main surface and a second main surface; a first semiconductor chip formed on a first main surface of the island; and a second semiconductor chip formed on a second main surface of the island. A second bonding pad formed on the surface of the second semiconductor chip; a first bonding pad formed on the surface of the first semiconductor chip; a second bonding pad formed on the surface of the second semiconductor chip; A lead terminal having a surface, and a tip of the lead terminal being close to the island; a thin portion formed at a tip portion of the first main surface of the lead terminal, the thickness of which is partially reduced; A resin for sealing the periphery of the second semiconductor chip, a first bonding pad and a first of the lead terminals.
A first bonding wire that electrically connects the thin portion surface of the main surface, a second bonding pad and a second of the lead terminals.
And a second bonding wire for electrically connecting the main surface to the semiconductor device. 2. A step of fixing a first semiconductor chip to a first main surface of an island; a first bonding pad formed on a surface of the first semiconductor chip; and a lead terminal having a tip close to the island. Wire bonding a thin portion formed at the tip of the first main surface to a thin portion partially with a first bonding wire; and bonding a second semiconductor chip to a second main surface of the island. And when the first main surface of the island is turned down, the first main terminal of the lead terminal is placed on a stage in which a concave escape portion for escaping the first semiconductor chip and the first bonding wire is formed. Placing the lead terminal and the island in a positional relationship such that a surface is in contact and an end of the relief portion substantially coincides with an end of the thin portion; Serial second lead terminal
And a step of wire bonding the main surface with a second bonding wire. 3. The semiconductor device according to claim 1, wherein the first semiconductor chip has a smaller chip size than the second semiconductor chip, and the position of the bonding pad is far away. 3. The method for manufacturing a semiconductor device according to item 2. 4. The method for manufacturing a semiconductor device according to claim 1, wherein a depth of said thin portion is larger than a diameter of said first bonding wire.