JP3172471B2 - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enlarge a chip size of a semiconductor chip which is laminated on a device, by performing wire bonding in a track without a back loop. SOLUTION: A first semiconductor chip 10 is fixed on an island 13. A second semiconductor chip 11 is fixed on the first semiconductor chip 10. A first bonding pad 12a and a lead terminal 17 undergo wire bonding on a track without a back loop. A second bonding pad 12b and the lead terminal 17 undergo the wire bonding with the back loop being provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a plurality of semiconductor chips are stacked and molded, and the chip size of a semiconductor chip to be mounted can be increased.

[0002]

2. Description of the Related Art As a technique for encapsulating a semiconductor device, a transfer mold for encapsulating a semiconductor chip 1 with a thermosetting epoxy resin 2 as shown in FIG. Technology. A lead frame is used as a support material for the semiconductor chip 1. The semiconductor chip 1 is die-bonded to the island 3 of the lead frame, and the bonding pads of the semiconductor chip 1 and the leads 4 are connected to the wires 5.
It is manufactured by setting a lead frame in a mold having a desired outer shape, injecting an epoxy resin into the mold, and curing the lead frame.

On the other hand, the wave of miniaturization and weight reduction of various electronic devices is unavoidable, and semiconductor devices incorporated therein are required to have higher capacity, higher function, and higher integration. Therefore, it has existed as an idea before (for example, Japanese Patent Application Laid-Open No. 55-1111517).
Attention has been paid to a technique for sealing a plurality of semiconductor chips in one package, and there has been a movement to realize it. That is, FIG.
As shown in (B), a first semiconductor chip 1a is fixed on the island 3 and a second semiconductor chip 1a is fixed on the first semiconductor chip 1a.
The semiconductor chip 1b is fixed, the corresponding bonding pad and the lead 4 are connected by bonding wires 5a and 5b, and sealed with the resin 2.

[0004] In such a semiconductor device, a wire bonding step to the first semiconductor chip 1a is as follows. That is, referring to FIGS. 8 and 9, the gold ball at the tip of the wire inserted into the center hole of the capillary 6 is first-bonded to the bonding pad 6 of the first semiconductor chip 1a (FIG. 8A), as indicated by reference numeral 7a. Then, the capillary 6 is raised in the vertical direction (FIG. 8 (B)), and at that position the second
(FIG. 8 (C)), and rises again in the vertical direction as indicated by reference numeral 7c (FIG. 9 (A)), and returns to reference numeral 7d.
The second bond is made on the surface of the lead terminal 4 while drawing a semicircle as shown in FIG. 9 (FIG. 9B), and the wire is cut by raising the capillary 6. The movement of reference numeral 7b is called a back loop, and A bent portion 8 of the wire is formed, and the bent portion 8 becomes the top of the wire loop.

[0005]

However, in order to draw a back loop forming the vertex of the loop, the capillary 9 is indicated by reference numeral 9 in FIG. 9A so as not to collide with the second semiconductor chip 1b. As described above, the second semiconductor chip 1
b must be retracted to a position where the back loop has a margin. The retreat amount of the back loop is about 100 μm, and furthermore, the diameter of the capillary 6 and the like are related. Therefore, since the chip size of the second semiconductor chip 1b is limited, there is a disadvantage that a chip having a larger size cannot be mounted. Further, the loop height of the second bonding wire 5b is inevitably increased in order to avoid a short circuit between the first and second bonding wires 5a and 5b, and the resin thickness indicated by X in FIG. There was a disadvantage that the size was increased.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has been described in connection with the "launching" in which the surface of a first semiconductor chip is lowered with respect to the position of a lead terminal of a first bonding wire. And the first bonding wire rises vertically after the first bonding,
A method of manufacturing a semiconductor device in which a second semiconductor chip is horizontally moved to a lead terminal side without a back loop and wire bonding is performed along a locus for performing a second bond on a surface of the lead terminal, thereby eliminating a chip size restriction on a second semiconductor chip. Is provided.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. First, a completed semiconductor device will be described. 5A and 5B are cross-sectional views of FIG.
(A) and (B) are a top view and a back view. In addition, FIG.
Is a cross-sectional view taken along the line AA in FIG. 4, and FIG.
It is a line sectional view.

In FIG. 1, reference numerals 10 and 11 denote first and second semiconductor chips, respectively. First and second semiconductor chips 1
Various active and passive circuit elements are formed on the silicon surfaces 0 and 11 in the previous process. Bonding pads 12 for external connection are formed in peripheral portions of the first and second semiconductor chips 10 and 11. A passivation film such as a silicon nitride film, a silicon oxide film, or a polyimide-based insulating film is formed so as to cover each bonding pad 12, and an upper portion of the bonding pad 12 is opened for electrical connection.

The first semiconductor chip 10 is die-bonded on the island 13 of the lead frame by an epoxy-based conductive or insulating adhesive 14 such as Ag paste,
The semiconductor chip 11 is provided with an insulating epoxy-based adhesive 15 on the passivation film of the first semiconductor chip 10.
Is fixed. One end of a bonding wire 16 such as a gold wire is wire-bonded to the surface of the bonding pad 12 on the surface of each of the semiconductor chips 10 and 11, and the other end of the bonding wire 16 is connected to a tip 17 a of a lead terminal 17 for external lead-out. Wire bonded.

[0010] First and second semiconductor chips 10 and 11, leading end 17a of lead terminal, and bonding wire 1
The main part including 6 is made of an epoxy-based thermosetting resin 18 around the periphery.
And packaged. Lead terminal 17
Is led out from a position on the side wall of the package which is about half the thickness of the resin 18. That is, referring to FIG. 3 (A), from the lead 17, the upper resin thickness t1 and the lower resin thickness t2
Are almost the same thickness. The lead terminal 17 led out of the resin 18 is bent downward at one end, bent again, and formed into a Z-shape. This forming shape corresponds to the back side fixed portion 17 of the lead terminal 17.
This is a shape for surface mounting applications where b is opposed to a conductive pattern formed on a printed circuit board.

In this semiconductor device, first, the holding tie bars 1 provided at the four corners of the island 13 in the state of a lead frame are provided.
9, the height of the island 13 and the height of the lead terminal tip 17a are made different, and the first and second semiconductor chips 10 and
11 is die-bonded, and the bonding pad 12 and the tip 17a of the lead terminal are wire-bonded. 1
7 can be obtained by sandwiching and fixing the upper and lower molds, and injecting and curing a resin in such a state.

The lead frame has a thickness of 150 to 2
Each part such as the island 13 and the lead terminal 17 is formed by etching or punching a 00 μm copper- or iron-based plate-like material, and each part is a lead frame until cut off after the molding process. It is held in the body. In the held state, the height of the leading end portion 17a of the lead terminal and the height of the frame coincide with each other, and only the island 13 is stepped to have a different height. Therefore, in the completed device, the tie bar 19 holding the island 13 is bent upward inside the resin 18, extends substantially horizontally again at a position corresponding to the height of the lead 14, and
8 The cut surface is exposed on the surface and terminated.

Each of the semiconductor chips 10 and 11 is polished on the back surface by a back grinding process immediately before the assembling process to obtain a 250
The thickness is about 300 μm. The thickness of the lead terminal 17 (t3 in FIG. 3A) is about 130 μm. Since the island 13 is formed at the same time from the plate-like material, the plate thickness of the island 13 is also the same value, which is almost the limit value for maintaining the mechanical strength of each part.

The island 13 includes the first semiconductor chip 1
It is smaller than 0 and supports only the central portion of the first semiconductor chip 10. Diver 1 supporting island 13
9 extends in the horizontal direction as much as possible so as to bypass the second semiconductor chip 11 and is bent toward the inside of the resin 18 as described above. The back surface of the island 13 is exposed on the surface of the resin 18 (13a in FIG. 6B), and the tie bar 1
The back surface of the bypass extending portion 9 is also exposed (illustration 19a in FIG. 6B). First semiconductor chip 10
Has a rectangular elongated shape with a long side × short side of 3.0 mm × 8.5 mm, for example.
Has a nearly square shape, for example, 5.6 mm × 6.5 μ. Since both sides of the second semiconductor chip 11 are longer than the short sides of the first semiconductor chip 10, the second semiconductor chip 11 has a protruding portion 20 that protrudes from the first semiconductor chip 10 when overlapped. When the first and second semiconductor chips 10 and 11 are inverted and stacked, a part of the bonding pad 12 is hidden, so that the bonding pads 12 cannot be stacked except in this order.

Hereinafter, the wire bonding step of the above-described semiconductor device will be described in detail. First, the device after the die bonding step is set on a work bench of the wire bonding device.
Incidentally, the die bonding step is performed by bonding the adhesive 14 on the island 13.
Is supplied in an appropriate amount, the first semiconductor chip 10 is placed thereon, the adhesive 14 is solidified by baking to fix the first semiconductor chip 10, and then the first semiconductor chip 1
An appropriate amount of the insulating adhesive 15 is supplied on the substrate 0, the second semiconductor chip 11 is placed thereon, and the adhesive 15 is solidified by baking to fix the second semiconductor chip 11. Will be

Referring to FIG. 1A, a wire having a diameter of 100 μm, which is larger than the center hole, is melted by a flame torch or a spark method at the tip of a wire 16 inserted into the center hole of a substantially cylindrical capillary 20. Approximately gold balls 21 are formed. The gold ball 21 is moved by moving the capillary 20 fixed to an arm movable in the XYZ-axis directions and the first bonding pad 1 of the first semiconductor chip 10 is moved.
The gold ball 21 is fixed to the surface of the first bonding pad 12a by pressing the work table 2a with a predetermined pressure, heating the work table and applying ultrasonic vibration through the capillary 20 (first bond).

Referring to FIG. 1B, the capillary 20 is raised vertically at the position of the first bonding pad 12a as indicated by reference numeral 22a. The length of the wire pulled out at this time determines the length of the wire loop. FIG. 1 (C)
, The capillary 20 is connected to the second semiconductor chip 1.
Immediately in the substantially horizontal direction as indicated by reference numeral 22b toward the lead terminal 17 without drawing a back loop to one side. The wire 16 bends at the portion of the recrystallized region that has once melted and solidified again when the gold ball 21 is formed. The bend (height) can be adjusted to some extent by the composition of the wire 16. At this time capillary 2
The clamper (not shown) installed above the wire 0 does not fix the wire 16.

Referring to FIG. 2A, a horizontal movement is made and the height is lowered so as to draw a loop as indicated by reference numeral 22c. Further, the capillary 20 is lowered to press the bonding area of the lead terminal 14 with a predetermined pressure, and the wire 16 is stitch-bonded to the surface of the lead terminal 17 by ultrasonic vibration thermocompression (second bond).

As shown in FIG. 2B, the wire 16 is sandwiched and fixed by the clamper, and the capillary 20 is fixed.
To cut the wire 16. While the first bonding wire 16a is formed by this “uplift”, the second bonding wire 16b is formed by “down”
To perform wire bonding. That is, referring to FIGS.
The gold ball 21 at the tip of the wire 16 inserted into the center hole of the capillary 20 is first bonded to the second bonding pad 12b of the second semiconductor chip 11 (FIG. 3).
(A)), the capillary 20 is raised in the vertical direction as indicated by reference numeral 23a (FIG. 3 (B)), and a back loop is performed at that position as indicated by reference numeral 23b (FIG. 3 (C)). (FIG. 4A), second bonding is performed on the surface of the lead terminal 17 while drawing a semicircle as indicated by reference numeral 23d (FIG. 5B), and the capillary 20 is raised to cut the wire. (FIG. 4C).

In order to enable the first bonding wire 16a to be formed with a locus without a back loop, it becomes possible by setting the position of the second bond higher than the position of the first bond to "launch". For example, the second
When the same method is used for “down” as in the case of wire bonding of the semiconductor chip 11, the wire loop height is insufficient and electrical contact with the chip end is likely to occur.

In the above-described wire bonding step, since the back loop is not formed in the step of FIG. 1B, the distance between the second semiconductor chip 11 and the first bonding pad 12a (illustrated 24) is reduced. It can be narrower than before. Therefore, the chip size of the second semiconductor chip 11 stacked thereon can be increased, and the degree of freedom of the combination of the chip sizes of the first and second semiconductor chips 10 and 11 can be increased.

Further, since the height of the loop can be minimized by performing “launch”, the second bonding wire 1
6b (see FIG. 4C, 25) can be easily maintained, and the risk of electrical short-circuit between the two can be reduced. Further, the second bonding pad 12 b is connected to the lead terminal 17.
Therefore, the loop length and the loop height of the second bonding wire 16b can be reduced inevitably. Therefore, the height of the outer shape of the device can be reduced.

The present invention can be practiced even if the number of chips is increased to two or three, and the effect of the present invention is exerted by performing wire bonding on a locus without a back loop except for the topmost chip. be able to.

[0024]

As described above, according to the present invention,
By setting the wire bonding process of the first semiconductor chip 10 to “launch” and performing the wire bonding on the trajectory in which the back loop is eliminated, the capillary 20 is prevented from colliding with the second semiconductor chip 11, thereby preventing the second semiconductor chip 11 from colliding. This has the advantage that the distance (24) between the semiconductor chip 11 and the second bonding pad 12a can be reduced to increase the chip size of the second semiconductor chip 11.

Since the locus without the back loop means that the wire loop height can be minimized, the first bonding wire 16a and the second bonding wire 1a
6b can be increased. This means that the first and second bonding wires 16a, 16b
This also has the advantage of reducing the possibility of a contact accident between the two when they cross.

Further, by reducing the loop height of the first bonding wire, the loop height of the second bonding wire can be naturally suppressed, whereby even if a plurality of chips are mounted, the loop height can be reduced within a thin package. It also has the advantage that it can be stored.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a first wire bonding step of the present invention.

FIG. 2 is a cross-sectional view for explaining a first wire bonding step of the present invention.

FIG. 3 is a cross-sectional view for explaining a first wire bonding step of the present invention.

FIG. 4 is a cross-sectional view for explaining a first wire bonding step of the present invention.

FIG. 5 is a sectional view showing a semiconductor device after completion of the present invention.

6A is a top view and FIG. 6B is a back view showing a semiconductor device after completion of the present invention.

FIG. 7 is a cross-sectional view illustrating a conventional example.

FIG. 8 is a sectional view for explaining a conventional example.

FIG. 9 is a cross-sectional view for explaining a conventional example.

Claims (2)

(57) [Claims] 1. A first semiconductor chip is fixed on an island, a second semiconductor chip is fixed on the first semiconductor chip, and the lead is higher than a height of a bonding pad of the first semiconductor chip. The height of the terminal is higher, the height of the lead alone is lower than the height of the bonding pad of the second semiconductor chip, and the bonding pad of the first semiconductor chip and the lead terminal are connected by a first bonding wire. A method of manufacturing a semiconductor device, comprising: connecting a bonding pad of the second semiconductor chip and the lead terminal with a second bonding wire, wherein the first bonding wire moves a capillary to form the second bonding wire. Performing a first bond on a surface of a bonding pad of the semiconductor chip; and bonding the capillary to the bonding pad. Moving the semiconductor device in the vertical direction; moving the semiconductor device in the vertical direction; moving the semiconductor device to the lead terminal side without performing a back loop moving to the second semiconductor chip side; Performing a bonding process. 2. The method according to claim 1, wherein the second bonding wire includes the back loop.