JPH10260828A - Information processor having control storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To continue processing without being accompanied by the exchange of chips and the reproduction of a chip when the failure of ROM of a control storage and a bug of a micro program occur. SOLUTION: An IDM(instruction decode memory) 20 decodes the heading address of a micro instruction, accesses a cache 4 and CROM 42, selects their outputs with a selector 46 and uses for the processing of the macro instruction. When a failure detector 48 detects the error of the CROM 42, it uses a control circuit 54 and an SVP (service processor) 100 to forcibly select the output of the cache 4 and rewrites an access instruction bit 21 in the IDM 20. A micro instruction from an MMU(main memory unit) 60 is written in the cache 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus having a control memory.

[0002]

2. Description of the Related Art It is difficult to mount a large-capacity control memory in a one-chip microprocessor, which has become mainstream these days, in order to hold all microprograms on one chip. Therefore, in order to achieve high performance with a small amount of hardware, the control storage may be configured by combining a read only memory (ROM) and a cache memory.

A ROM is used for a rewritable memory (RAM: Random Access Memory).
This is because the degree of integration is much higher than in y), so that when compared with the same area, a larger amount of microprograms can be held than in RAM. If all the microprograms cannot be stored in the ROM alone, the microprograms requiring performance are stored in the ROM, and the other microprograms are stored in the cache memory. Reduce the amount of wear. The microprogram stored in the cache memory may cause a penalty due to a cache miss when reading from the cache memory.
The microprogram stored in the OM and the microprogram stored in the cache are carefully determined.

In such a control memory, when a failure occurs in the ROM or when it becomes necessary to correct the microprogram stored in the ROM due to a bug in the microprogram or the like, it is determined that the failure has occurred. If the microprocessor is not replaced immediately, processing cannot be continued, and if a bug occurs, correct processing cannot be performed until the microprocessor is recreated in order to correct the microprogram in the ROM. .

[0005] To solve the above problem, conventionally, for example,
As in the technique described in Japanese Patent Application Laid-Open No. 1-199232, a control storage constituted by a ROM is divided into a plurality of blocks, and validity indicating whether a microprogram in the ROM is valid or invalid is corresponding to each block. ROM for storing information
And a RAM for storing a block-by-block microprogram including a microprogram corresponding to a failure or bug detected when a microprogram is read from the ROM.
A microprogram in a block unit including a microprogram in which a failure or a bug has occurred is stored in the ROM, and a corresponding bit in an effective block information storage circuit in the ROM is turned off, thereby reading the ROM of the microprogram in which the failure or a bug occurs.
There is a technology for switching reading from the RAM to reading from the RAM.

[0006]

The problem with the prior art described above is that the amount of hardware is increased by providing an extra RAM which is not required unless a failure or a bug occurs, thereby increasing the amount of hardware and one chip of the processor. It is an obstacle to the development.

The reason is that a ROM in which a failure or a bug has occurred
This is because there is provided a RAM for newly storing the micro-programs therein.

An object of the present invention is to minimize the amount of hardware to be added and to reduce the amount of hardware to be added, and at the same time, when a failure or a bug occurs in a microprogram in a ROM, the processing of a computer can be performed without replacing a chip or recreating a chip. An object of the present invention is to provide an information processing apparatus having a control memory that can be continued.

[0009]

An information processing apparatus having a first control storage according to the present invention comprises: (a) a control storage storing a microprogram and having a read-only memory and a cache; and (b) a macro instruction. And (c) an access corresponding to each entry of the instruction decode memory and instructing whether to access the read-only memory or the cache memory. When the instruction bit and (d) the access instruction bit indicate the read-only memory, the micro-instruction read from the read-only memory is selected and supplied to indicate the cache memory. The micro-instruction read from the cache memory is selected. Means, and failure detecting means for detecting a failure of the read-only memory checks microinstructions read from the (e) said read-only memory,
(F) when the access instruction bit indicates reading of the microinstruction from the read only memory, the failure detecting means detects that the microinstruction read from the read only memory has a failure; Switching means for forcibly switching the access instruction of the access instruction bit to the access instruction to the cache; and (g) changing the content of the access instruction bit from the access to the read-only memory to the access to the cache. Rewriting means for rewriting; and (h) supply means for reading and supplying a microinstruction switched from access to the read-only memory to access to the cache from the cache.

An information processing apparatus having a second control storage according to the present invention is an information processing apparatus having the first control storage, wherein when a microprogram stored in the read-only memory is changed, , Means for rewriting the access instruction bit.

An information processing apparatus having a third control storage according to the present invention is an information processing apparatus having the first or second control storage, wherein the selecting means includes a microinstruction from the read only memory. A selector circuit for selecting one of the microinstructions from the cache; and an access instruction bit register for storing the access instruction bit for controlling the selector circuit.

An information processing device having a fourth control storage according to the present invention is the information processing device having the third control storage, wherein the switching means performs a logical inversion of an output of the access instruction bit register. An inverting circuit, a first AND circuit for outputting the logical product of the output of the fault detecting means and the inverting circuit, and a logical product of a cache hit signal from the cache and an output of the access instruction bit register. 2 AND circuit, an OR circuit that outputs an OR of the output of the first AND circuit and the second AND circuit, and a first register that holds the output of the OR circuit. Have.

An information processing apparatus having a fifth control memory according to the present invention is the information processing apparatus having the fourth control memory, wherein the rewriting means holds an output of the first AND circuit. A second register; and a control circuit that controls the read-only memory based on an output of the second register.

[Operation] Means for detecting the occurrence of a failure when reading a microprogram from the ROM is as follows:
The contents of the access instruction bits are forcibly switched from accessing the ROM to accessing the cache. Therefore, the corresponding microprogram can be read from the cache, and the processing can be continued while avoiding the failure of the microprogram in the ROM.

Further, when a bug occurs in the microprogram in the ROM, the content of the access instruction bit is set to RO.
By providing a means for rewriting the access to M to the access to the cache, it becomes possible to read the bugged microprogram from the cache,
If the modified microprogram is stored in the main storage device, the modified microprogram can be read out through the cache, and processing can be continued without recreating the microprocessor.

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the following description, abbreviations of the names of the respective blocks in FIG. 1 are shown in parentheses. For the second and subsequent times, this abbreviation is used.

In FIG. 1, an instruction register (IR) 10
Is a register for storing a macro instruction, and has an operation code (OP) 11. The instruction decode memory (IDM) 20 is addressed by the OP11 of the IR 10 and decodes the head address of the corresponding microprogram. The head address of the microprogram matches the address of the main memory (MMU) 60 that stores the macro instruction, the operand data, and the microprogram. Each entry of the IDM 20 is a cache 4 having a cache memory address array (CAA) 40 and a cache memory data array (CDA) 41.
And a control storage ROM (CROM) 42, and an access instruction bit 21 for instructing whether to access the CROM 42 and a head address 22 of the microprogram.

The access instruction bit 21 is constituted by a RAM, and the head address 22 of the microprogram is constituted by a ROM. The access instruction bit 21 has a value “0” and C
The access to the ROM 42 is instructed, and the access to the cache 4 is instructed by the value “1”. The access instruction bit 21 and the microprogram head address 22 read from the IDM 20 are set in an access instruction bit register (AIR) 30 and a microprogram address register (MARA) 31, respectively.

The read address of the CROM 42 is
It corresponds to the lower part of the microprogram address,
The lower part of the head address 22 of the microprogram read from the IDM 20 is set in a read address register (CAR) 34 for the CROM 42. The cache memory address array (CAA) 40 stores an index address of the cache 4. This index address consists of the upper part of the microprogram address. Cache memory data array (CDA)
Reference numeral 41 denotes a data portion of the cache 4 for storing a microprogram. The CROM 42 stores a microprogram that requires performance. Comparator (COM) 43
Is the upper part of the microprogram address and CAA40
When the COM 43 detects a match, it outputs a value “0”, and a desired microprogram is output from the CDA4.
Indicates that it is held at 1. This is called a cache hit. If a mismatch is detected, a value "1" is output, indicating that the desired microprogram is not held in the CDA 41, and the desired microprogram must be read from the MMU 60. This is called a cache miss.

The failure detector 48 detects whether the microprogram read from the CROM 42 has a parity error or not, and checks the validity of the parity bit of the microprogram. If a parity error is detected, it is regarded as a failure of the CROM 42. When this failure is detected, a value “1” is output, and when no failure is detected, a value “0” is output. When the failure detector 48 detects a failure when the access to the CROM 42 is instructed, the result is set in the registers 51 and 53 through the OR gate 45 and the AND gate 49, respectively. The micro program address register (MARB) 50
This register holds the address of the microprogram.
When a cache miss occurs, a microprogram address is supplied to the MMU 60 to read a desired microprogram from the MMU 60. Register 51
Are used when a cache miss occurs and when the CROM 42
The value "1" is set when a failure occurs in the reading of the data. When the value “1” is set, the MMU 60 is instructed to read the microprogram. The selector 46 is
A selector for selectively outputting a microprogram read from the CDA 41 and the CROM 42 in accordance with the instruction of the access instruction bit 21. The micro program data register (MPD) 52 is a register that holds the micro program selected by the selector 46 and supplies the macro program to an instruction execution unit (not shown).
The register 53 is a register that is set to a value “1” when a failure is detected when accessing the CROM 42.
The result is notified to the control circuit 54, the selector 12, and the service processor (SVP) 100. The control circuit 54 gives an instruction to rewrite the access instruction bit 21 to the IDM 20 when it is notified that a failure has occurred by reading the microprogram from the CROM 42 by an instruction from the register 53.

All microprograms are held in the MMU 60. The microprogram in the MMU 60 includes a ROM 61 corresponding to the microprogram stored in the CROM 42 and a cache 62 read and executed by the CDA 41. Have. The ROM section 61
The cache unit is assigned to the lower part of the address of the MMU 60, and the cache unit is assigned to the upper part of the address. SVP
A service processor 100 monitors and controls the state of the system, and performs control such as writing a microprogram on an auxiliary storage (not shown) to the MMU 60 and writing the value of the access instruction bit 21. The selector 12 is a selector that selects the value of the access instruction bit 21 sent from the SVP 100 and the register 53.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIG. 1, FIG. 2, and FIG. 2 and 3 are time charts showing the operation of the embodiment of the present invention. Microprograms that require performance must reside in the microprocessor,
It is stored in the CROM 42 in advance. Other microprograms are read from the MMU 60 into the CDA 41 and executed. When starting the system, the SV
P100 stores the microprogram on the auxiliary storage in the MMU
At the same time, the entry corresponding to the microprogram accessing the CROM 42 is set to the value “0”, and the entry corresponding to the microprogram accessing the cache 4 is set to the value “1”. .

When the start-up of the system is completed and the program is executed, a macro instruction is set in IR10 (T0 in FIG. 2). O of the macro instruction set in IR10
With the P-code 11, the IDM 20 is indexed (T0 in FIG. 2),
The corresponding access instruction bit 21 and the head address 22 of the microprogram are read from the IDM 20 and set in the AIR 30 and the MARA 31, respectively (T1 in FIG. 2). The lower address of the head address of the microprogram corresponds to the read address of the CROM 42, and the read address of the CROM 42 is set in the CAR 34. Then, the CROM 42 is addressed by the read address set in the CAR 34, the microprogram on the corresponding entry is read, and supplied to the selector 46 (T1 in FIG. 2). The index address of the cache 4 is a lower part of the head address of the microprogram set in the MARA 31. The remaining upper address of the MARA 31 is used for comparison with the index address stored in the CAA 40. When the head address of the microprogram is set in the MARA 31, the CAA 40 and the CAD 41 are indexed, and the contents of the entry of the corresponding address are read (T1 in FIG. 2). C
The address index read from the AA 40 is
In COM43, it is compared with the upper address of MARA31 (T1 in FIG. 2). The desired microprogram is CDA41
, The value “0” is output from the COM 43; otherwise, the value “1” is output. The microprogram read from the CDA 41 is supplied to the selector 46. When the access instruction bit set in the AIR 30 indicates access to the CROM 42 (see FIG. 2).
T1), the selector 46 is controlled to select the microprogram read from the CROM 42 and set it in the MPD 52 (T2 in FIG. 2), and the microprogram is supplied to an instruction execution unit (not shown). If the access instruction bit set in the AIR 30 indicates access to the cache 4 and a cache hit occurs,
The microprogram read from the CDA 41 through the selector 46 is set in the MPD 52 (FIG. 2).
T3).

The determination of cache hit / miss is made by COM
The comparison result at 43 is sent to the AND gate 44, and the
When the logical product with the 30 access instruction bits is obtained and the value “0” is output (T2 in FIG. 2), the cache 4
Access is judged as cache hit and CDA4
The microprogram read from 1 becomes valid,
The instruction is supplied from the MPD 52 to the instruction execution unit (T3 in FIG. 2).
When the output of the AND gate 44 is “1” (see FIG. 2T
3) It is a cache miss, the output of the AND gate 44 is set in the register 51 through the OR gate 45 (T4 in FIG. 2), and the control circuit 54 is notified that a cache miss has occurred, and the control of the cache miss process is started. Is done. At the same time, the microprogram address in MARA 31 is set in MARB 50 (FIG. 2).
T4). Then, a data read instruction is transmitted from the register 51 to the MMU 60 (T4 in FIG. 2), and the MARB 50 is output.
From the microprogram read address is MMU60
(T4 in FIG. 2), and the block data including the desired microprogram is stored in the cache unit 62 of the MMU 60.
(Tm in FIG. 2) and the register (CDW) 3
Set to 3. The block data of the microprogram set in the CDW 33 is written to the corresponding address position of the CDA 41. At this time, the MARA 31 used for comparison with the index address of the CAA 40 is used.
The upper address of the microprogram in the new CA
A register (CA) is used as an index address of A40.
W) 32, and is written to the corresponding address position of the CAA 40 (Tm + 1 in FIG. 2). Then, the cache 4 is indexed again (Tm + 2 in FIG. 2), but this time hits (Tm + 2 in FIG. 2), so the desired microprogram is read from the CDA 41, set in the MPD 52, and supplied to the instruction execution unit (FIG. 2). 2Tm + 3).

The microprogram read from the CROM 42 is checked for a fault by the fault detector 48 (Tn + 1 in FIG. 3). When the failure detector 48 detects that a failure has occurred, a value “1” is output, and
It is supplied to an AND gate 49. The other input of the AND gate 49 is connected to the NAND gate 47 for inverting the value of the access instruction bit of the AIR 30. Therefore, when the value of the access instruction bit of the AIR 30 is “1” indicating the access to the cache 4, NAN
The value is inverted to "0" by the D gate 47, and the AND gate 49
Results in the value "0", and the result of the fault detector 48 is invalidated. When the value of the access instruction bit of the AIR 30 is “0” indicating the access of the CROM 42 (Tn + 1 in FIG. 3), the value is inverted to “1” by the NAND gate 47 and the result of the logical product by the AND gate 49 is “ 1 ", and the occurrence of a failure in the microprogram read from the CROM 42 becomes effective. AND gate 4
9 is set in the register 53 (see FIG. 3).
Tn + 2), and is set in the register 51 through the OR gate 45 (Tn + 2 in FIG. 3). The register 53 has a CR
The reading of the microprogram from the OM 42 notifies the control circuit 54 that a failure has occurred, and inputs the value “1” set in the register 53 to the access instruction bit 21 of the IDM 20 through the selector 12 (Tn + 2 in FIG. 3). ). Then, in response to an instruction from the control circuit 54, the value of the corresponding access instruction bit 21 of the IDM 20 is rewritten from a value "0" indicating access to the CROM 42 to a value "1" indicating access to the cache 4. The result of this rewriting is subsequently transmitted from IDM20 to AIR3.
0, and the value of the AIR 30 is changed from the value “0” to the value “1”.
(Tn + 3 in FIG. 3). The register 51 is
Since the output of the AND gate 49 has been forcibly rewritten to a value "1" equivalent to that when a cache miss has occurred,
A cache miss process is executed in the same manner as described above. Therefore, the block data including the microprogram whose failure is detected in the CROM 42 is stored in the ROM of the MMU 60.
It is read from the unit 61 (Tx in FIG. 3) and written to the CDA 41 (Tx + 1 in FIG. 3). Then, a normal microprogram is read from the CDA 41 (Tx + in FIG. 3).
2), is supplied to the instruction execution unit (Tx + 3 in FIG. 3). When the microprogram is used from the next time, the value of the access instruction bit 21 in the corresponding IDM 20 is rewritten to the value “1” indicating the cache 4 access, so that the cache 4 is accessed and the desired microprogram is accessed. Since the program is registered in CDA41, C
It is supplied from the DA 41 to the instruction execution unit at high speed.

The above description is an example in which a macro instruction is completed in one operation and only the microprogram at the start address of the microprogram is required. However, a macro instruction requires execution of a plurality of operations. In this case, the subsequent microphone addresses following the head address are not shown, but are not shown in MARA 31 and CAR 34.
Are generated by adding the word length of the microprogram (fixed to 4 bytes in this embodiment), and subsequent microprograms are sequentially read from the cache 4 or the CROM 42 until the operation is completed. During this time, the corresponding macroinstruction is kept in the IR 10, so that the same value of the access instruction bit of the AIR 30 is kept. Therefore, the control for the subsequent microprogram is performed in the same manner as the control for the first microprogram.

Next, when a bug or the like occurs, the CROM 4
The case where the microprogram in 2 is modified will be described.

The modified microprogram is stored in an auxiliary storage (not shown). When the system is started, the modified microprogram is written from the auxiliary storage to the MMU 60 by the SVP 100. Next, SVP
100 writes the value of the access instruction bit 21 through the selector 12 so that the access instruction bit 21 in the IDM 20 corresponding to the corrected microprogram becomes the value “1” indicating the cache 4 access. Therefore, when the modified microprogram is executed, the access instruction bit 21 indicates the access to the cache 4 instead of the CROM 42.
Via the DA41, the modified microprogram
The data can be read out through the MU 60 and supplied to the instruction execution unit.

[0030]

The first effect is that when a failure occurs in reading a microprogram from a ROM, a failure occurs by forcibly switching the contents of the access instruction bit from access to the ROM to access to the cache. Cached microprogram 4
, And the processing can be continued while avoiding the failure of the microprogram in the ROM.

The reason is that a normal microprogram can be read from the main memory through the cache.

The second effect is that when a bug occurs in the microprogram in the ROM, the content of the access instruction bit corresponding to the microprogram in which the bug occurs is set to R.
By rewriting the access from the OM to the access to the cache, it is possible to read out the corrected contents of the bugged microprogram through the cache, and to continue the processing without recreating the microprocessor. .

The reason is that the source of the microprogram in which the bug has occurred can be read from the main memory through the cache. If the corrected microprogram is stored in the main memory, the microprogram after the correction can be read. This is because reading can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of the embodiment of the present invention.

[Explanation of symbols]

4 Cache 10 Instruction register (IR) 11 Operation code (OP) 12, 46 Selector 20 Instruction decode memory (IDM) 21 Access instruction bit 22 Start address of microprogram 30 Access instruction bit register (AIR) 31 Microprogram address register (MAR)
A) 32 register (CAW) 33 register (CDW) 34 read address register (CAR) 40 cache memory address array (CAA) 41 cache memory data array (CDA) 42 control storage ROM (CROM) 43 comparator (COM) 44, 49 AND gate 45 OR gate 47 NAND gate 48 Failure detector 50 Micro program address register (MAR
B) 51, 53 register 52 microprogram data register (MPD) 54 control circuit 60 main storage unit (MMU) 61 ROM unit 62 cache unit 100 service processor (SVP)

Claims (5)

[Claims] (A) a control storage for storing a microprogram and having a read-only memory and a cache;
(B) an instruction decode memory for decoding an operation code of a macro instruction to a head address of a microprogram; and (c) corresponding to each entry of the instruction decode memory, accessing the read-only memory or accessing the cache memory. (D) when the access instruction bit indicates the read-only memory, selects and supplies the microinstruction read from the read-only memory; And (e) checking the micro-instruction read from the read-only memory and detecting a failure of the read-only memory. (F) the access instruction bit When the microinstruction read from the read-only memory is instructed to read the microinstruction read from the read-only memory, the access instruction bit Switching means for forcibly switching the access instruction to the cache access instruction,
(G) rewriting means for rewriting the contents of the access instruction bit from access to the read-only memory to access to the cache; and (h) switching from access to the read-only memory to access to the cache. An information processing apparatus having a control memory, comprising: supply means for reading and supplying a microinstruction from the cache. 2. The information processing apparatus having control storage according to claim 1, further comprising means for rewriting said access instruction bit when a change occurs in a microprogram stored in said read-only memory. 3. A selector circuit for selecting either a microinstruction from the read-only memory or a microinstruction from the cache, and an access for storing the access instruction bit for controlling the selector circuit. 3. An information processing apparatus having control storage according to claim 1, further comprising an instruction bit register. 4. An inverting circuit in which the switching means performs a logical inversion of an output of the access instruction bit register, a first AND circuit which outputs an AND of the output of the failure detecting means and the inverting circuit, A second AND circuit that outputs a logical product of the cache hit signal from the cache and the output of the access instruction bit register; and a logical sum of the output of the first logical product circuit and the second logical product circuit 4. The information processing device having control storage according to claim 3, further comprising: a logical sum circuit that outputs the data; and a first register that holds an output of the logical sum circuit. 5. A rewriting means comprising: a second register for holding an output of the first AND circuit; and a control circuit for controlling the read-only memory based on an output of the second register. 5. An information processing apparatus having a control storage according to claim 4, wherein