JPH10256189A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology by which the lowering of the operating speed of an MISFET(metal insulator semiconductor field effect transistor) associated with the refinement of the MISFET can be suppressed. SOLUTION: A method for manufacturing a semiconductor integrated circuit device having an MISFET includes a process for forming a silicon layer 14A by the selective growth method on the upper surface of a silicon film 8 worked in the form of a gate electrode pattern, a process for coating the surface of the silicon layer 14A with a metallic film 15 having a high melting point, and a process for forming a silicide layer 16A by causing a reaction between the silicon in the silicon layer 14A and the metal in the metallic film 15 through silicifying annealing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a semiconductor integrated circuit device, in particular, MISFET (M etal I nsulator F i
when applied to a semiconductor integrated circuit device having a eld E ffect T ransistor) a technique effectively.

[0002]

2. Description of the Related Art MIS mounted on a semiconductor integrated circuit device
FETs tend to be miniaturized for the purpose of increasing the degree of integration. However, the miniaturization of the MISFET causes an increase in gate resistance due to a reduction in gate length, which hinders an increase in operating speed. Therefore, the gate electrode is composed of a polycide structure in which a silicide layer having a lower sheet resistance than that of the polycrystalline silicon film is formed on the surface of the polycrystalline silicon film into which impurities are introduced, and the gate resistance increases due to a reduction in gate length. Has been suppressed. In a MISFET having a gate electrode of this polycide structure, salicide (Sa
Licide: formed in the manufacturing process using the S elf Ali gned Sili cide) technology. Hereinafter, a manufacturing process of the MISFET using the salicide technique will be described.

First, a gate insulating film is formed on a main surface of an element formation region of a semiconductor substrate made of a single crystal silicon substrate.

Next, a polycrystalline silicon film into which impurities are introduced is formed on the surface of the gate insulating film, and thereafter, the polycrystalline silicon film is processed into a predetermined gate electrode pattern shape.

Next, using the polycrystalline silicon film processed into the gate electrode pattern shape as an impurity introduction mask, an impurity is introduced into a main surface portion of an element formation region of the semiconductor substrate to form a source region and a drain region. A pair of semiconductor regions (impurity diffusion regions) are formed.

Next, a side wall surface of the polycrystalline silicon film in the gate length direction is covered with a side wall spacer made of an insulating film. The sidewall spacer is formed by forming an insulating film on the main surface of the semiconductor substrate and then performing anisotropic etching on the insulating film by an amount corresponding to the film thickness.

Next, a refractory metal film is formed on the entire main surface of the semiconductor substrate, and the upper surface of the polycrystalline silicon film and the respective surfaces of the pair of semiconductor regions are covered with the refractory metal film. . As the refractory metal film, for example, a titanium (Ti) film is used.

Next, a silicidation anneal is performed to cause the silicon of the polycrystalline silicon film to react with the metal of the high melting point metal film to form a silicide layer. The silicide layer is formed by reacting with the metal film. When the refractory metal film is a titanium film, a titanium silicide (TiSi ₂ ) layer is generated.

Next, by selectively removing the unreacted refractory metal film other than the region where the silicide layer is formed, a MISFE having a gate electrode of a polycide structure is formed.
T is formed.

A MISFET having a gate electrode having a polycide structure is described in, for example,
EDM, Technical Digest, 84
Pages 1 to 843 (1987, IEDM, TECHNI
CAL DIGEST, pp. 841-847).

[0011]

In the MISFET having the gate electrode of the polycide structure, the silicide layer of the gate electrode is formed by processing a polycrystalline silicon film into a predetermined gate electrode pattern shape and then forming the gate electrode pattern shape. Since it is formed by reacting the silicon of the polycrystalline silicon film with the metal of the refractory metal film,
The width of the silicide layer in the gate length direction is determined by the width of the polycrystalline silicon film in the gate length direction. On the other hand, the width of the polycrystalline silicon film having the gate electrode pattern shape in the gate length direction is reduced as the MISFET is miniaturized.
That is, as the width of the polycrystalline silicon film in the gate length direction decreases, the width of the silicide layer in the gate length direction also decreases. Therefore, the resistance of the gate electrode increases with miniaturization, and the operating speed of the MISFET decreases.

[0012] Among the silicide layers, a titanium silicide layer formed using a titanium film is a tungsten silicide (WSi ₂ ) formed using a tungsten film.
Since a lower sheet resistance can be obtained as compared with a molybdenum silicide (MoSi ₂ ) layer formed using a layer or a molybdenum film, it is most suitable as a silicide material for a gate electrode.
However, the titanium silicide layer has a sheet resistance of 0.5 [μ] when its width in the gate length direction is gradually reduced.
[m] rapidly increases. Therefore, when a gate electrode is formed using a titanium silicide layer, the resistance of the gate electrode increases with miniaturization, and the operating speed of the MISFET decreases.

The titanium silicide layer is described in, for example, 1992, Symposium on VLSI Technology.
Digest of Technical Papers (pages 66 to 67)
It is described in.

It is an object of the present invention to provide a MISFE with miniaturization.
An object of the present invention is to provide a technique capable of suppressing a decrease in the operation speed of T.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A method for manufacturing a semiconductor integrated circuit device having a MISFET, comprising the steps of: forming a silicon layer on the upper surface of a silicon film processed into a gate electrode pattern shape by a selective growth method; A step of coating with a melting point metal film and a step of performing silicidation annealing to form a silicide layer by reacting silicon of the silicon layer with a metal of the high melting point metal film.

According to the above-described means, the width of the silicon layer in the gate length direction is larger than the width of the silicon film in the gate length direction, so that the silicon of the silicon layer reacts with the metal of the refractory metal film. The width of the formed silicide layer in the gate length direction is also wider than the width of the silicon film in the gate length direction. Therefore, the width of the silicide layer in the gate length direction can be increased as compared with the width of the silicon film in the gate length direction. The increase in resistance can be suppressed. As a result, a decrease in the operation speed of the MISFET due to miniaturization can be suppressed.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments of the present invention, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 shows a schematic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

As shown in FIG. 1, the semiconductor integrated circuit device according to the present embodiment is mainly composed of a semiconductor substrate 1.
The semiconductor substrate 1 is formed of, for example, a p-type semiconductor substrate made of single crystal silicon.

An n-channel conductivity type MISFET Qn and a p-channel conductivity type MISFET Qp are formed on the surface of the element forming region of the semiconductor substrate 1. A p-type well region 3 is formed on the surface of the semiconductor substrate 1 on which the n-channel conductive MISFET Qn is formed, and an n-type well region 2 is formed on the surface of the semiconductor substrate 1 on which the p-channel conductive MISFET Qp is formed. Are formed. That is, the semiconductor integrated circuit device of the present embodiment is not limited to this structure, but has a twin-well structure.

The n-channel conductivity type MISFET Qn
Are formed on the surface of the p-type well region 3 surrounded by a field insulating film (element isolation insulating film) 4. n
The channel conductivity type MISFET Qn is not limited to this structure, but has a structure mainly composed of the threshold voltage control layer 6B, the gate insulating film 7, the gate electrode G, the source region and the drain region. Threshold voltage control layer 6B
Is formed on the surface of the p-type well region 3, the gate insulating film 7 is formed on the surface of the p-type well region 3, the gate electrode G is formed on the surface of the gate insulating film 7, and the source region and the drain region are formed. Are formed on the surface of the p-type well region 3.

The p-channel conductive type MISFET Qp
Are formed on the surface of the n-type well region 2 surrounded by the field insulating film 4. M of p-channel conductivity type
The ISFET Qp is not limited to this structure, but has a structure mainly composed of the threshold voltage control layer 6A, the gate insulating film 7, the gate electrode G, the source region and the drain region. The threshold voltage control layer 6A is formed on the surface of the n-type well region 2, and the gate insulating film 7 is formed on the n-type well region 2.
The gate electrode G is formed on the surface of the gate insulating film 7, and the source and drain regions are formed on the surface of the n-type well region 2.

The MISFET Qn, MISFET Qp
In each of the gate electrodes G, a titanium silicide layer (TiSix) 16A was formed as a silicide layer having a lower sheet resistance than that of the polycrystalline silicon film 8 on the surface of the polycrystalline silicon film 8 into which the impurity was introduced. It has a polycide structure. The titanium silicide layer 16A is
It is formed by a reaction between titanium (Ti) and silicon (Si). The titanium silicide layer 16A is made of tungsten (W).
Sheet resistance is lower than that of a tungsten silicide (WSix) layer formed by the reaction between silicon and silicon (Si) and a molybdenum silicide (MoSix) layer formed by the reaction of molybdenum (Mo) and silicon (Si). Therefore, it is most suitable as a silicide material for a gate electrode.

The MISFET Qn, MISFET Qp
In each of the gate electrodes G, the titanium silicide layer 1
The width of the gate electrode 6A in the gate length direction is wider than the width of the polycrystalline silicon film 8 in the gate length direction. As will be described later in detail, the titanium silicide layer 16A covers a side surface in the gate length direction of the polycrystalline silicon film 8 processed into a gate electrode pattern shape with a sidewall spacer 11 made of an insulating film. Crystalline silicon film 8
A silicon layer by selective growth on the top surface of
The silicon layer is formed by coating the surface of the silicon layer with a titanium film which is a high melting point metal film, and thereafter performing silicidation annealing to react silicon of the silicon layer with titanium of the tinta film.

In the MISFET Qn, each of the source region and the drain region includes a low impurity concentration n-type semiconductor region 9, a high impurity concentration n + type semiconductor region 12, and a titanium silicide layer 16B. Each of the n-type semiconductor region 9 and the n + -type semiconductor region 12 is formed on the surface of the p-type well region 3, and the titanium silicide layer 16B is formed on the surface of the n + -type semiconductor region 12. That, MISFET Qn of the present embodiment, LDD part of the channel forming region side of the drain region is set to a low impurity concentration than the impurity concentration of the other region (L ightly D oped D r
ain) It has a structure.

In the MISFET Qp, each of the source region and the drain region comprises a low impurity concentration p-type semiconductor region 10, a high impurity concentration p + type semiconductor region 13, and a titanium silicide layer 16B. Each of the p-type semiconductor region 10 and the p + -type semiconductor region 13 is an n-type well region 2
And the titanium silicide layer 16B is formed on the surface of the p + type semiconductor region 12. That is, the MISFET Qp of the present embodiment has the same LDD structure as the MISFET Qn.

The MISFET Qn, MISFET Qp
In each of the above, the width in the gate length direction of each silicide layer 16B is formed to be wider than the width in the gate length direction of each semiconductor region (the n + type semiconductor region 12 and the p + type semiconductor region 13). The titanium silicide layer 16B will be described in detail later, but a silicon layer is formed on the surface of each semiconductor region by a selective oxidation method, and then the silicon layer is covered with a titanium film which is a high melting point metal film. Thereafter, silicidation annealing is performed to form silicon by reacting silicon of the silicon layer with titanium of the tinta film.

The MISFET Qn, MISFET Qp
In each of the above, the side surface in the gate length direction of the polycrystalline silicon film 8 of the gate electrode G is covered with a sidewall spacer 11 made of an insulating film. The sidewall spacer 11 is formed in a shape exposing the upper surface of the polycrystalline silicon film 8 and exposing the upper portion of the side surface.

A wiring 18 is electrically connected to each of the one titanium silicide layer 16B and the other titanium silicide layer 16B of the MISFET Qn through a connection hole 17A formed in the interlayer insulating film 17. In addition, the M
A wiring 18 is electrically connected to one of the titanium silicide layers 16B and the other titanium silicide layer 16B of the ISFET Qp through connection holes 17B formed in the interlayer insulating film 17. These wirings 18 are formed of, for example, an aluminum alloy film.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS. 2 to 6 (a cross-sectional view of a main part for describing the manufacturing method).

First, a semiconductor substrate 1 formed of a p-type semiconductor substrate made of single crystal silicon is prepared.

Next, an n-type well region 2 and a p-type well region 3 are formed on the surface of the element forming region of the semiconductor substrate 1.

Next, a field insulating film 4 made of a silicon oxide film is formed on the surface of the element isolation region of the semiconductor substrate 1 by using a known selective oxidation method. Field insulating film 4
Is formed to a thickness of, for example, about 400 [nm].

Next, a p-type impurity is introduced into the surface of the n-type well region 2 by ion implantation to form a threshold voltage control layer 6A. The threshold voltage control layer 6B is formed by introducing an n-type impurity by the implantation method.

Next, a gate insulating film 7 made of a thermal silicon oxide film is formed on each surface of the n-type well region 2 and the p-type well region 3. The gate insulating film 7 is, for example, 6.5 [n].
m]. The steps so far are shown in FIG.

Next, a polycrystalline silicon film doped with an n-type impurity (for example, phosphorus) is formed on the entire surface of the semiconductor substrate 1 including the surface of the gate insulating film 7, and thereafter, the polycrystalline silicon film is formed. Process the film into a gate electrode pattern shape,
A polycrystalline silicon film 8 having a gate electrode pattern is formed on the surface of the gate insulating film 7. The width L of the polycrystalline silicon film 8 in the gate length direction defines the gate length of the MISFET. The width L of the polycrystalline silicon film 8 in the gate length direction is MIS
It is reduced with miniaturization of FET.

Next, using the polycrystalline silicon film 8 as a mask for introducing impurities, an n-type impurity (for example, phosphorus) is selectively introduced into the surface of the p-type well region 3 by ion implantation. A pair of n that is a source region and a drain region
A type semiconductor region 9 is formed.

Next, a p-type impurity (for example, boron) is selectively introduced into the surface of the n-type well region 2 by ion implantation using the polycrystalline silicon film 8 as a mask for introducing impurities. A pair of p-type semiconductor regions 10, which are a source region and a drain region, are formed. The process up to this point is shown in FIG.
Shown in The formation of the pair of p-type semiconductor regions 10 may be performed before the step of forming the pair of n-type semiconductor regions 9.

Next, the side surface of the polycrystalline silicon film 8 in the gate length direction is covered with a sidewall spacer 11 made of an insulating film. The side wall spacer 11
The silicon layer 8 is formed in such a shape that the upper surface is exposed and the upper part of the side surface is exposed. The sidewall spacers 11, an insulating film is formed consisting of the entire surface, for example, a silicon oxide film on the surface of the semiconductor substrate 1 including on the upper surface of the polycrystalline silicon film 8, then, the insulating film RIE (R eactive I o
formed by anisotropic etching of the n E tching) or the like.

Next, using the polycrystalline silicon film 8 and the sidewall spacers 11 as a mask for introducing impurities, an n-type impurity (for example, arsenic) is selectively implanted into the surface of the n-type semiconductor region 9 by ion implantation. To form a pair of n + -type semiconductor regions 12 that are a source region and a drain region.

Next, using the polycrystalline silicon film 8 and the sidewall spacers 11 as a mask for introducing impurities, a p-type impurity (for example, boron) is selectively implanted into the surface of the p-type semiconductor region 10 by ion implantation. And a pair of p + -type semiconductor regions 13 serving as a source region and a drain region.
To form

Next, a film such as a natural oxide film is removed to expose the surface (upper portion of the upper surface and side surface) of the polycrystalline silicon film 8 other than the region covered with the side wall spacers 11 and to remove the n + The respective surfaces of the type semiconductor region 12 and the p + type semiconductor region 13 are exposed. The steps so far are shown in FIG. The formation of the pair of p + -type semiconductor regions 13 may be performed before the step of forming the pair of n + -type semiconductor regions 12.

Next, using a selective growth method, a silicon layer 14A is selectively formed on the upper surface of the polycrystalline silicon film 8, and the pair of n + -type semiconductor regions 12 and the pair of p +
A silicon layer 14B is selectively formed on each surface of the mold semiconductor region 13. Each of these silicon layers 14A and 14B is made of dichlorosilane as a reaction gas.
LPCVD using _{(SiH 2 Cl 2) (L} ow P ressure C
formed by hemical V apor D eposition) process. Specifically, it is formed by flowing dichlorosilane in a hydrogen atmosphere of about 800 ° C. In this process,
The silicon layer 14A grows upward from the upper surface of the polycrystalline silicon film 8 and grows in the gate length direction, so that the width of the silicon layer 14A in the gate length direction is equal to the gate length of the polycrystalline silicon film 8. It is wider than the width in the direction. Further, since the upper portion of the side surface of the polysilicon layer 8 in the gate length direction is exposed from the sidewall spacer 11, the silicon layer 14A is formed from the upper portion of the side surface of the polysilicon film 8 in the gate length direction. grow up. That is, by exposing the upper portion of the side surface of the polycrystalline silicon film 8 in the gate length direction from the sidewall spacer 11, the silicon layer 14A grows from the upper portion of the side surface of the polycrystalline silicon film 8 in the gate length direction. Therefore, the width of the silicon layer 14A in the gate length direction is further increased. In this step, the silicon layer 1
4B grows from the surface of each semiconductor region (n + type semiconductor region 12, p + type semiconductor region 13) upward and in the gate length direction.
The width of 4B in the gate length direction is wider than the width of each semiconductor region in the gate length direction. The steps so far are shown in FIG.

Next, a titanium film 15 is formed as a refractory metal film on the entire surface of the semiconductor substrate 1, and the respective surfaces of the silicon layers 14A and 14B are covered with titanium 15.

Next, silicidation annealing is performed to cause the silicon of the silicon layer 14A to react with the metal of the titanium film 15 to form a silicide layer 16A, and the silicon of the silicon layer 14B and the metal of the titanium film 15 To form a silicide layer 16B. In this step, since the width of the silicon layer 14A in the gate length direction is larger than the width of the polycrystalline silicon film 8 in the gate length direction, the silicon layer 14A is formed by the reaction between the silicon of the silicon layer 14A and the titanium of the titanium film 15. The width of the titanium silicide layer 16A in the gate length direction becomes wider than the width of the polycrystalline silicon film 8 in the gate length direction. In this step, the width of the silicon layer 14B in the gate length direction is larger than the width of each semiconductor region (the n + type semiconductor region 12 and the p + type semiconductor region 13) in the gate length direction. The width in the gate length direction of the titanium silicide layer 16B formed by the reaction between the silicon and the titanium of the titanium film 15 is larger than the width in the gate length direction of each semiconductor region. The steps so far are shown in FIG.

Next, the unreacted titanium film 15 other than the regions where the titanium silicide layers 16A and 16B are formed is selectively removed. By this step, the MISF having the gate electrode G having the polycide structure is formed.
ETQn and MISFETQp are formed.

Next, as shown in FIG.
7, the connection hole 17A and the wiring 18 are sequentially formed. Thereafter, although not shown, a final protective film is formed, and a bonding opening is formed in the final protective film, whereby the semiconductor integrated circuit device of the present embodiment is almost completed.

As described above, according to the present embodiment, the following effects can be obtained.

(1) A method of manufacturing a semiconductor integrated circuit device having MISFETs Qn (or Qp), wherein a silicon layer 14A is formed by selective growth on the upper surface of a silicon film 8 processed into a gate electrode pattern shape. Covering the surface of the silicon layer 14A with a titanium film 15;
A step of performing silicidation annealing and reacting silicon of the silicon layer 14A with titanium of the titanium film 15 to form a silicide layer.

According to this configuration, the width of the silicon layer 14A in the gate length direction is larger than the width of the silicon film 8 in the gate length direction, so that the silicon layer 14A is formed by the reaction between the silicon of the silicon layer 14A and the metal of the titanium film 15. The width of the titanium silicide layer 16A to be formed in the gate length direction is also wider than the width of the silicon film 8 in the gate length direction. Therefore, the width of the titanium silicide layer 16A in the gate length direction can be increased as compared with the width of the silicon film 8 in the gate length direction. Therefore, even if the width of the silicon film 8 in the gate length direction is reduced with miniaturization. In addition, an increase in the resistance of the gate electrode G can be suppressed. As a result, a decrease in the operating speed of the MISFET Qn (or Qp) due to miniaturization can be suppressed.

Further, the width of the titanium silicide layer 16A in the gate length direction can be increased as compared with the width of the silicon film 8 in the gate length direction. μm] or less, and the width of the titanium silicide layer 16A in the gate length direction can be set to 0.5 μm or more. Therefore, the MSi is not affected by the increase in the sheet resistance of the titanium silicide layer 16A.
The size of the ISFET Qn can be reduced.

(2) Before the step of forming the silicon layer 14A on the upper surface of the silicon film 8 by the selective growth method, the side surface in the gate length direction of the silicon film 8 processed into the gate electrode pattern shape is formed as a sidewall spacer. 11 is provided. The sidewall spacer 11
Is formed so that the upper surface of the silicon film 8 is exposed and the upper part of the side surface is exposed.

According to this configuration, silicon layer 14A grows from the upper side of the side surface of polycrystalline silicon film 8 in the gate length direction, so that the width of silicon layer 14A in the gate length direction is further increased. Therefore, the titanium silicide layer 1
Since the width of the gate electrode 6A in the gate length direction can be further increased as compared with the width of the silicon film 8 in the gate length direction, a decrease in the operation speed of the MISFET Qn (or Qp) due to miniaturization can be further suppressed.

(3) A method of manufacturing a semiconductor integrated circuit device having MISFETs Qn (or Qp), wherein a silicon film 8 having a gate electrode pattern is formed on a surface of a semiconductor substrate 1 made of silicon with a gate insulating film 7 interposed. Forming a silicon substrate, covering a side surface of the silicon film 8 in the gate length direction with a side wall spacer 11, and using the polycrystalline silicon film 8 and the side wall spacer 11 as a mask for introducing impurities. Forming a pair of n + -type semiconductor regions 12 (or p-type semiconductor regions 13) as a source region and a drain region by introducing an impurity into the surface portion of the n + -type semiconductor region 1;
Forming a silicon layer 14B on each surface of the silicon layer 14B by a selective growth method, covering the surface of the silicon layer 14B with a titanium film 15, and performing silicidation annealing.
Forming a titanium silicide layer 16B by reacting silicon of the silicon layer 14B with titanium of the titanium film 15;

According to this structure, the width of the silicon layer 14B in the gate length direction is larger than the width of the n + type semiconductor region 12 in the gate length direction. The width of the titanium silicide layer 16B formed in the gate length direction is also larger than the width of the n + type semiconductor region 12 in the gate length direction. Therefore, the width of the titanium silicide layer 16B in the gate length direction is reduced.
Since the width of the n + type semiconductor region 12 in the gate length direction can be increased as compared with the width of the n + type semiconductor region 12, even if the width of the n + type semiconductor region 12 in the gate length direction is reduced with miniaturization, the resistance of the source region and the drain region is reduced. Increase can be suppressed. As a result, a decrease in the operating speed of the MISFET Qn (or Qp) due to miniaturization can be suppressed.

The titanium silicide layer 16 B is formed on the silicon layer 14 B formed on the surface of the n + type semiconductor region 12.
Is formed by the reaction between the n + -type semiconductor region 12 and the titanium film 15, so that the impurities in the n + -type semiconductor region 12 are not absorbed by the titanium silicide layer 16B. Therefore, a decrease in the sheet resistance of the n + type semiconductor region 12 can be suppressed.

In this embodiment, the silicon layer 14A,
The case where each of the titanium silicide layers 16A and 16B is formed by reacting each of the titanium silicide layers 15 with the respective titanium silicide layers 16A and 16B has been described, but a cobalt (Co) film, a tungsten (W) film,
Using any one of the high melting point metal films of the molybdenum (Mo) film, the metal of these high melting point metal films reacts with the silicon of the silicon layer to form a silicide layer (CoSix layer, WS
ix layer, MoSix layer).

In this embodiment, the MISFETs Qn,
Although a case has been described where each of Qp has an LDD structure, each of MISFETs Qn and Qp may have a single drain structure. In this case, after covering the side surface in the gate length direction of the polycrystalline silicon film 8 with the sidewall spacer, the n-type semiconductor region 9 and the p-type semiconductor region 1
A silicon layer 14B is formed on each of the surfaces 0 by a selective growth method.

In this embodiment, the case where a semiconductor substrate formed of a semiconductor substrate made of single-crystal silicon is used has been described. However, a semiconductor substrate having an epitaxial layer formed on the surface of the semiconductor substrate may be used. Good.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

[0064]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

In a semiconductor integrated circuit device having a MISFET, a reduction in the operating speed of the MISFET due to miniaturization can be suppressed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a principal part showing a schematic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 3 is a fragmentary cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 4 is a fragmentary cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 5 is a fragmentary cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 6 is a fragmentary cross-sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor base, 2 ... n-type well region, 3 ... p-type well region, 4 ... field insulating film, 6A, 6B ... threshold voltage control layer, 7 ... gate insulating film, 8 ... polycrystalline silicon film,
9 n-type semiconductor region, 10 p-type semiconductor region, 11 sidewall spacer, 12 n-type semiconductor region, 13
p + type semiconductor regions, 14A, 14B ... silicon layer, 15 ...
Refractory metal film, 16A, 16B ... silicide layer, 17 ...
Interlayer insulating film, 17A: connection hole, 18: wiring, Qn: MISFET of n-channel conductivity type, Qp: MISFET of p-channel conductivity type.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Masami Nakata 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd.

Claims (5)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device having a MISFET, comprising: forming a silicon layer on a top surface of a silicon film processed into a gate electrode pattern shape by a selective growth method; And a step of forming a silicide layer by performing silicidation annealing and reacting silicon of the silicon layer with a metal of the high melting point metal film. A method for manufacturing a circuit device. 2. A method for manufacturing a semiconductor integrated circuit device having a MISFET, comprising: a step of covering a side surface in a gate length direction of a silicon film processed into a gate electrode pattern shape with a sidewall spacer; Forming a silicon layer by a selective growth method thereon, and covering the surface of the silicon layer with a refractory metal film,
A method for manufacturing a semiconductor integrated circuit device, comprising a step of performing a silicidation anneal to react silicon of the silicon layer with a metal of a high melting point metal film to form a silicide layer. 3. A method for manufacturing a semiconductor integrated circuit device having a MISFET, comprising: forming a silicon film having a gate electrode pattern on a surface of a semiconductor substrate made of silicon with a gate insulating film interposed therebetween; A step of introducing an impurity into the main surface of the base in a self-aligned manner with respect to the silicon film to form a pair of semiconductor regions that are a source region and a drain region, and a side wall in the gate length direction of the silicon film with a sidewall spacer. Covering, and forming a silicon layer on the upper surface of the silicon film and the surface of the pair of semiconductor regions by a selective growth method,
A step of coating the surface of the silicon layer with a high-melting-point metal film, and a step of performing silicidation annealing to form a silicide layer by reacting silicon of the silicon layer with a metal of the high-melting-point metal film. A method for manufacturing a semiconductor integrated circuit device. 4. The semiconductor according to claim 2, wherein the sidewall spacer is formed in a shape exposing an upper surface of the silicon film and exposing an upper portion of a side surface thereof. A method for manufacturing an integrated circuit device. 5. The film according to claim 1, wherein the high melting point metal film is any one of a titanium film, a cobalt film, a tungsten film, and a molybdenum film. Of manufacturing a semiconductor integrated circuit device.