JPH09320993A - Semiconductor device and manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with a low-resistance gate electrode and a diffusion layer with small leak at a junction. SOLUTION: An n-type impurity ion is implanted with a mask of a gate electrode 4 and an insulating film 5, and an n-type diffusion layer 7 is formed by anneal treatment. After metal for forming a silicide layer is deposited, the titanium and the silicon are subjected to solid phase reaction in anneal treatment to form a titanium silicide layer 8 on the n-type diffusion layer 7 and the gate electrode 4. The titanium layer 9 in a non-silicide state is removed by etching and the silicide layer 8 is formed selectively on the gate electrode 4 and the diffusion layer 7. An oxide insulating film 10 is formed, and after the upper face and the side wall of the gate electrode 4 is exposed by etch back, the titanium film 9 is formed. In addition, the substrate is heated by anneal treatment, and a titanium silicide layer 8 is formed on the gate electrode 4. The non-silicide titanium film 9 is removed by etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for reducing the resistance of a gate electrode and reducing a junction leak current, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In order to speed up MOSFET,
It is necessary to reduce the resistance of the source / drain and gate electrodes. As a method of reducing the resistance, a process of forming a silicide layer on the surfaces of the source / drain and the gate electrode in a self-aligned manner has been developed.

A conventional MOSFET manufacturing method is applied to an n-type M
The OSFET will be described below with reference to FIG. After the element isolation 2 is formed on the silicon substrate 1, the gate electrode 4 made of polysilicon is formed through the gate insulating film 3.
Then, a sidewall insulating film 5 is formed on the sidewall of the gate electrode 4 (see FIG. 4- (a)). Next, using the gate electrode 4 and the sidewall insulating film 4 as a mask, the silicon substrate 1 is ion-implanted with an impurity 6 such as arsenic to form a diffusion layer 7 serving as a source / drain in a self-aligned manner (FIG. 4-). (See (b)).

Next, a metal film of titanium or the like is formed on the entire surface (see FIG. 4- (c)) and annealed to form a diffusion layer 7 between the polysilicon of the gate electrode 4 and the source / drain. The silicidation reaction is selectively promoted between the surface of the gate electrode 4 and the surface of the diffusion layer to form a silicide layer 8 in a self-aligned manner (FIG. 4-).
(D)).

[0005]

With the recent technological progress toward higher integration and higher speed in semiconductor devices, MO
The structure of the SFET is also miniaturized. When the channel length is shortened by miniaturization, it is necessary to form the source / drain shallowly in order to prevent the short channel effect.Therefore, the silicide layer formed on the source / drain diffusion layer also needs to be thinly formed. It was

However, as shown in FIG. 5, the resistance Rs of the silicide layer rapidly increases as the line width Lg decreases. Further, as also shown in FIG. 5, the thinner the deposited titanium film is, the more difficult it is to form silicide, and the resistance value increases even with the same line width.

When the titanium film thickness is thin, high temperature,
There is a method of performing heat treatment for a long time and sufficiently reacting to form a silicidation stably, but in this case, there is a problem that the silicide creeps up to the side wall and the gate and the diffusion layer are short-circuited. Occurs.

An object of the present invention is to eliminate these drawbacks, and by forming a silicide layer on the diffusion layer and then forming a silicide layer on the gate electrode, the diffusion layer and the gate electrode are silicided respectively. To provide a method for manufacturing a semiconductor device capable of optimizing the formation conditions of the semiconductor device and widening a process margin, and the method for manufacturing a semiconductor device described above, thereby providing a diffusion layer with low resistance and less junction leakage, and a gate with low resistance. It is to provide a semiconductor device provided with an electrode.

[0009]

[Means for Solving the Problems] To solve the above problems, the means for solving the problems of the present invention are a semiconductor device having the following features and a manufacturing method thereof.

(1) A step of forming a silicide layer on the gate electrode and the diffusion layer; a step of forming an interlayer film and then etching back the interlayer film to expose the gate electrode; and a step of silicide the gate electrode. And a step of converting the semiconductor device into a semiconductor device. As a result, the silicide formation conditions for the diffusion layer and the silicide formation conditions for the gate electrode can be optimized independently, so that the diffusion layer with low resistance and low junction leakage current and the gate electrode with low resistance are provided. It is possible to manufacture a semiconductor device having a high quality.

(2) A step of forming a silicide layer on the gate electrode and the diffusion layer, a step of forming an interlayer film and then etching back the interlayer film to expose the gate electrode, and a silicon film deposited on the entire surface. A method of manufacturing a semiconductor device comprising: a step of etching back the film to leave a silicon film on a side wall of the gate electrode; and a step of silicidizing the silicon film and the gate electrode. This makes it possible to increase the effective area of the gate electrode when performing silicidation. At the same time, since the optimization of the silicide formation conditions of the diffusion layer and the optimization of the silicide formation conditions of the gate electrode can be performed independently, a diffusion layer with low resistance and low junction leakage current and a low resistance gate electrode were provided. It is possible to manufacture a semiconductor device.

(3) A semiconductor device comprising a diffusion layer, a first silicide layer formed on the diffusion layer, a gate electrode, and a second silicide layer formed on the gate electrode, A semiconductor device is characterized in that the first silicide layer and the second silicide layer are made of different metal materials. With this, since a metal material suitable for each of the diffusion layer and the gate electrode can be used, it is possible to reduce the resistance of the diffusion layer, suppress the junction leakage current, and reduce the resistance of the gate electrode.

(4) A semiconductor device comprising a diffusion layer, a first silicide layer formed on the diffusion layer, a gate electrode, and a second silicide layer formed on the gate electrode, A semiconductor device is characterized in that the first silicide layer and the second silicide layer have different film thicknesses. As a result, for example, the silicide layer on the diffusion layer can be made thin and the silicide layer on the gate electrode can be made thick, so that the resistance of the diffusion layer can be reduced and the junction leakage current can be suppressed. The resistance of the electrode can be reduced.

(5) A semiconductor device characterized in that a silicide layer having a width larger than a gate length is formed by the method for manufacturing a semiconductor device according to claim 2. This allows
Since the effective area for forming the silicide is larger than the actual gate length, stable formation of the silicide is facilitated.
It is possible to reduce the resistance of the gate electrode.

(6) A step of forming a silicide layer on the gate electrode and the diffusion layer, a step of etching back the interlayer film formed after forming the gate electrode to expose the gate electrode, and a step of selectively forming the gate electrode. And a step of growing a low-resistance material. This makes it possible to optimize the conditions for forming the silicide in the diffusion layer and the conditions for forming the silicide in the gate electrode independently, so that the resistance of the diffusion layer and the junction leakage current can be suppressed and the resistance of the gate electrode can be reduced. Can be realized. Moreover, since the low-resistance silicide layer is formed after the gate electrode is formed, it is possible to suppress the mutual diffusion of gate impurities that occurs in the dual gate transistor.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments 1 to 3 of a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a process sectional view of an n-type MOS transistor showing a first embodiment of the present invention. For example, the element isolation 2 is formed on the p-type silicon substrate 1 by using a known method.

Next, a thin oxide film having a thickness of about 60 Å is formed on the silicon substrate 1, a polysilicon layer is deposited on the surface of the oxide film to a thickness of about 3000 Å, and then n of arsenic or the like is deposited.
Type impurities are ion-implanted.

Next, the polysilicon layer and the oxide film are patterned to form a gate electrode 4 and a gate oxide film 3 made of polysilicon.

Next, an insulating film is formed and anisotropically etched to form a sidewall insulating film 5 on the side wall of the gate electrode 4.

Next, using the gate electrode 4 and the sidewall insulating film 5 as a mask, an n-type impurity such as arsenic is added at 30 ke.
After ion implantation with an implantation energy of about V, annealing treatment is performed to activate the n-type diffusion layer 7 serving as a source / drain (see FIG. 1- (a) above).

A metal for forming a silicide layer, for example, titanium is deposited to a thickness of about 30 to 40 nm by using a sputtering method to form a titanium film 9 (FIG. 1- (b)).
reference).

Lamp annealing is performed in a nitrogen atmosphere, and heating is performed at a temperature of 650 to 800 ° C. for 30 to 60 seconds to cause titanium and silicon to undergo a solid phase reaction to form a source / drain on the n-type diffusion layer 7. A titanium silicide layer 8 is formed on the gate electrode 4 in a self-aligned manner. The titanium film 9 that is not silicidized is removed by wet etching using a mixed solution of hydrogen peroxide water and ammonia water (see FIG. 1- (c)).

Next, in a nitrogen atmosphere, a lamp annealing treatment is performed to a temperature of 800 to 900 ° C. for 1 to 20 seconds. This annealing treatment is effective for reducing the resistance of the silicide layer 8.

As a result, the silicide layer 7 having an average film thickness of 30 to 80 nm is selectively formed on the gate electrode 4 and the diffusion layer 7 forming the source / drain.

An insulating film 10 made of an oxide film is formed to a thickness of 400 to 600 nm by using the CVD method. This insulating film 10
Is etched back to expose the upper surface and side wall of the gate electrode 43 by 30 to 50 nm (see FIG. 1- (d)). At this time, the silicide layer 8 on the gate electrode 4 may be removed. By exposing not only the upper surface of the gate electrode 4 but also the side wall, the effective area in the subsequent silicidation of the gate electrode 4 can be increased, which is effective for stable formation of the silicide.

Next, a titanium film 9 having a thickness of 10 to 60 nm is formed on the entire surface by using the sputtering method (see FIG. 1- (e)).

In a nitrogen atmosphere, heating is performed at a temperature of 650 to 800 ° C. for 30 to 60 seconds by a lamp annealing treatment, and the second titanium silicide is self-aligned on the exposed upper surface and side wall of the gate electrode 4 on the gate electrode 4. Form the layer 14. The titanium film 9 that is not silicidized is removed by wet etching using a mixed solution of hydrogen peroxide water and ammonia water (see FIG. 1- (f)).

By the above method, the first silicide layer 8 on the diffusion layer 7 and the second silicide layer 1 on the gate electrode are formed.
By forming 4 in different steps, for example,
It is possible to form the silicide layer 8 on the diffusion layer 7 to be thin and to form the second silicide layer 14 on the gate electrode to be thick. In addition, the silicide layer 8 and the second silicide layer 14 can be formed thicker. Since the heat treatment conditions for formation can be changed, a process margin can be widened, and a semiconductor device including a diffusion layer having low resistance and low junction leakage current and a gate electrode having low resistance can be obtained. .

Even if only the upper surface of the gate electrode 4 is exposed, it is not necessary to consider the problem of junction leak in the diffusion layer. Therefore, the thickness of the titanium film 9 to be deposited thereafter should be sufficiently thick. Since it can be formed, the silicide layer can be stably formed, and the effect of lowering the resistance of the gate electrode can be obtained.

Needless to say, even if the silicide is not formed on the diffusion layer 7, the effect of reducing the resistance of the gate electrode can be obtained.

Although titanium is used for the metal film for forming the silicide layer 7 in the above example, it is possible to obtain the same effect by using cobalt, nickel, tungsten or the like in addition to titanium. There is no end.

(Embodiment 2) FIG. 2 is a process sectional view of an n-type MOS transistor showing a second embodiment of the present invention. For example, the element isolation 2 is formed on the p-type silicon substrate 1 by using a known method.

Next, a thin oxide film having a thickness of about 60Å is formed on the silicon substrate 1, a polysilicon layer 11 is deposited on the surface of the oxide film to a thickness of about 3000Å, and then an n-type impurity such as arsenic is deposited. Is ion-implanted.

After that, the silicon nitride film 1 used as an etching stopper in a later step is formed on the polysilicon layer 11.
2 is deposited to a thickness of about 100 nm (see FIG. 2- (a)).

Next, the polysilicon layer 11 and the oxide film are patterned to form a gate electrode 4 and a gate oxide film 3 made of polysilicon. At this time, the silicon nitride film 12 remains on the polysilicon layer 11 without being removed.

Next, an insulating film is formed and anisotropically etched to form a sidewall insulating film 5 on the side wall of the gate electrode 4.

Next, using the gate electrode 4 and the sidewall insulating film 5 as a mask, an n-type impurity such as arsenic is added at 30 ke.
After ion implantation with an implantation energy of about V, annealing treatment is performed to activate the n-type diffusion layer 7 to be the source / drain (see FIG. 2 (b) above).

A metal for forming a silicide layer, for example, titanium is deposited to a thickness of about 30 to 40 nm by a sputtering method to form a titanium film 9 (FIG. 2- (c)).
reference).

Lamp annealing is performed in a nitrogen atmosphere and heating is performed at a temperature of 650 to 800 ° C. for 30 to 60 seconds to cause a solid phase reaction between titanium and silicon, and on the n-type diffusion layer 7 forming the source / drain. The titanium silicide layer 7 is formed in a self-aligned manner. The titanium film 9 that is not silicidized is removed by wet etching using a mixed solution of hydrogen peroxide water and ammonia water (see FIG. 2- (d)).

Next, in a nitrogen atmosphere, a lamp annealing treatment is performed to a temperature of 800 to 900 ° C. for 1 to 20 seconds. This annealing treatment is effective for reducing the resistance of the silicide layer 8.

As a result, the silicide layer 8 having an average film thickness of 30 to 80 nm is selectively formed on the diffusion layer 7 forming the source / drain.

An insulating film 10 made of an oxide film is formed to a thickness of 400 to 600 nm by using the CVD method. This insulating film 10
Is etched back using a mixed gas of CHF3 gas and ClF3 gas, and the upper surface and the side wall of the gate electrode 4 are exposed to 30 to 30 nm.
It is exposed to 50 nm (see FIG. 2- (e)).

Next, the silicon film 1 is formed by using the CVD method.
3 is formed to have a thickness of 00 to 00 nm. The silicon film 13 is etched back to leave the silicon film 13 on the exposed sidewalls of the gate electrode 3 (see FIGS. 2F and 2G).

After that, the silicon nitride film 12 remaining on the gate electrode 4 is removed by wet etching using hot phosphoric acid.

Next, a titanium film 9 having a thickness of 10 to 60 nm is formed on the entire surface by using the sputtering method (see FIG. 2- (h)).

In a nitrogen atmosphere, the silicon film 1 left on the exposed upper surface and side walls of the gate electrode was heated by lamp annealing to a temperature of 650 to 800 ° C. for 30 to 60 seconds.
3 and the titanium film 9 are reacted to form a titanium silicide layer 8 on the gate electrode 4 in a self-aligned manner. The titanium film 9 that is not silicidized is removed by wet etching using a mixed solution of hydrogen peroxide water and ammonia water (see FIG. 2- (i)).

By the above method, the width of exposed silicon consumed during the silicidation reaction is wider than the gate length due to the silicon film 13 left on the side wall of the gate electrode 4. The silicide layer can be stably formed, and it is effective for lowering the resistance of the gate electrode. Further, by forming the silicide layer 8 on the diffusion layer 7 and the second silicide layer 14 on the gate electrode in separate steps, for example, the silicide layer 8 on the diffusion layer 7 is formed.
Of the second silicide layer 14 on the gate electrode
Can be formed thicker, and the heat treatment conditions for forming the silicide layer 8 and the second silicide layer 14 can be changed, so that the process margin is widened and the resistance is reduced. It is possible to obtain a semiconductor device including a diffusion layer having a small junction leak current and a gate electrode having a low resistance.

Even if the exposed portion of the gate electrode 4 is only the upper surface, it is not necessary to consider the problem of junction leak in the diffusion layer. Therefore, the thickness of the titanium film 9 to be deposited thereafter should be sufficiently thick. Since it can be formed, the effect of lowering the resistance of the gate electrode can be obtained.

Needless to say, even if the silicide is not formed on the diffusion layer 7, the effect of reducing the resistance of the gate electrode can be obtained.

Although titanium is used for the metal film for forming the silicide layer 7 in the above example, it is possible to obtain the same effect by using cobalt, nickel, tungsten or the like in addition to titanium. There is no end.

(Third Embodiment) A third embodiment according to the sixth aspect will be described. In the semiconductor device and the manufacturing method according to the first embodiment,
As shown in FIG. 3, the tungsten layer 15 may be selectively grown on the exposed gate electrode 4.

In this case, in the process of the n-type MOS transistor described in the first embodiment, after the process of exposing the gate electrode 4 shown in FIG. 1- (d), the pressure is 45 to 55 nm and the temperature is 220 to 300 ° C. in an atmosphere. , SiH4 gas 6
-10 sccm, WF6 gas is caused to flow at 8-12 sccm for reaction, and a tungsten layer 15 is formed on the upper part of the gate electrode 4.
About 100 nm is selectively grown.

By this method, a structure similar to that of a polycide gate can be obtained. However, in the method of manufacturing a semiconductor according to the present invention, since the tungsten layer 15 is formed after the gate electrode is formed, the polycide gate is applied to the dual gate transistor. In this case, it is possible to suppress the deterioration of the characteristics caused by the interdiffusion of the gate impurities through the metal due to the heat treatment after the metal formation.

[0055]

As described above, by using the semiconductor device and the manufacturing method thereof according to the present invention, the interlayer film formed after the gate electrode is formed is etched back to expose the gate electrode,
By siliciding the gate electrode, the silicide forming condition of the diffusion layer and the silicide forming condition of the gate electrode can be optimized independently, so that the diffusion layer having a low resistance and a small junction leak current, It is possible to manufacture a semiconductor device having a low resistance gate electrode.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a MISFET according to the present invention (Example 1).

FIG. 2 is a manufacturing process diagram of a MISFET according to the present invention (Example 2).

FIG. 3 is a manufacturing process diagram of a MISFET according to the present invention (Example 3).

FIG. 4 is a manufacturing process diagram of a MISFET according to a conventional technique.

FIG. 5 is a diagram showing thin wire resistance and titanium film thickness dependence of thin wire resistance of a gate electrode.

[Explanation of symbols]

 1 Silicon Substrate 2 Element Isolation 3 Gate Insulation Film 4 Gate Electrode 5 Sidewall Insulation Film 6 Impurity 7 Diffusion Layer 8 Silicide Layer 9 Titanium Film 10 Insulation Film 11 Polysilicon Layer 12 Silicon Nitride Film 13 Silicon Film 14 Second Silicide Layer 15 Tungsten layer

Claims (6)

[Claims] 1. A step of forming a silicide layer on a gate electrode and a diffusion layer; a step of forming an interlayer film and then etching back the interlayer film to expose the gate electrode; and a step of siliciding the gate electrode. A method of manufacturing a semiconductor device, comprising: 2. A step of forming a silicide layer on the gate electrode and the diffusion layer, a step of forming an interlayer film and then etching back the interlayer film to expose the gate electrode, and a silicon film deposited on the entire surface. And a step of etching back the silicon film to leave a silicon film on the side wall of the gate electrode, and a step of silicidizing the silicon film and the gate electrode. 3. A diffusion layer and a first layer formed on the diffusion layer.
In the semiconductor device including the silicide layer, the gate electrode, and the second silicide layer formed on the gate electrode, the first silicide layer and the second silicide layer are made of different metal materials. Characteristic semiconductor device. 4. A diffusion layer and a first layer formed on the diffusion layer.
In the semiconductor device including the silicide layer, the gate electrode, and the second silicide layer formed on the gate electrode, the first silicide layer and the second silicide layer have different thicknesses, respectively. Semiconductor device. 5. The semiconductor device according to claim 2, wherein a silicide layer having a width larger than a gate length is formed by the method for manufacturing a semiconductor device. 6. A step of forming a silicide layer on the gate electrode and the diffusion layer, a step of etching back an interlayer film formed after forming the gate electrode to expose the gate electrode, and a step of selectively forming the gate electrode on the gate electrode. And a step of growing a low resistance material.