JPH10254764A - Inter-memory data transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inter-memory data transfer device which can efficiently transfer a part of a unit structure as the object of transfer even if data structure differs before and after transfer in data transfer between memories. SOLUTION: Structured transfer DMA 1 respectively sets the size of one data group related to structuring, a processing object data position in the data group, a processing data size, start addresses in a data group memory space being a processing object and the number of addresses in a memory react circuit 1A and a memory write circuit 1B. A transfer processing is executed based on the setting condition. Data structured by repeating the taking-in and writing of data with prescribed width from the data group having a prescribed interval is speedily transferred.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-memory data transfer device using a digital circuit, and more particularly, it is used to write data selectively obtained by an external data reading circuit or the like to a specified address at a specified interval. Related to the device.

[0002]

2. Description of the Related Art Conventional data transfer between memories uses a DMA.
(Direct Memory Access) is used, but data to be processed by DMA when reading and writing data is transferred from data that has been continuously present in a continuous memory space to a different continuous memory space. (As shown in FIG. 5A, continuous data at the source R1 'address is transferred as continuous data at the destination W1' address),
Even if the data is discontinuous, it is assumed that data existing at a specific address is transferred to a different continuous memory space. Also, the start address of the next data group is stored at the end of the data group to be transferred called a daisy chain, and after the transfer of the data group currently being transferred is completed, the data from the start address of the next data group at the end is stored. There is also a method of instructing the next new transfer source data or transfer destination data by a method of transferring data.

[0003]

When such processing by DMA is performed, the data is present in a continuous memory space, and a group of data having a plurality of different memory sizes and a plurality of semantically different data, a so-called data group. It is necessary for the structured data to be continuously arranged in a group, and a part of this structured data group existing in the memory space is selectively processed, and the continuous data in the form of stepping stones is processed. It was impossible to perform such a process. SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems in the related art, and in a data transfer between memories, even when the data structure has a different data structure before and after the transfer, a part of the unit structure can be efficiently transferred. It is an object of the present invention to provide a data transfer device between memories capable of performing such transfer.

[0004]

According to the first aspect of the present invention, a unit memory element having a predetermined data capacity is assembled to form a memory space, and is stored by designating an address for each unit memory element. The unit memory elements constituting the memory space in the memory that can access the stored data are structured using a structuring rule, and the memory forming the structured memory space is used as at least one memory for data transfer between the memories. In a memory-to-memory data transfer device, a unit expressing a structure by a continuous unit structure is used as the structuring rule, and a unit memory element specified based on the expressed unit structure is subjected to transfer processing and data is transferred between the units. Is performed.

According to a second aspect of the present invention, in the first aspect of the present invention, the unit memory element in the memory for transferring data between the memories is structured according to different structuring rules at a transfer source and a transfer destination. The transfer control of each of the memories at the transfer source and the transfer destination performs a control operation based on conditions set in accordance with the different structuring rules.

According to a third aspect of the present invention, in the second aspect of the present invention, as a structuring setting condition corresponding to the structuring rule,
The size of the unit structure, the position and the size of the unit memory element to be transferred in the unit structure are prepared.

According to a fourth aspect of the present invention, in any one of the first to third aspects of the present invention, designation of an object to be subjected to data transfer processing is performed by setting an arrangement of the continuous unit structure in the memory space. It is something to do.

According to a fifth aspect of the present invention, in any one of the first to fourth aspects of the present invention, as the arrangement of the continuous unit structures in the memory space, a head address and a structural unit of the unit structure to be transferred are processed. Is prepared.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present embodiment, a structured transfer DMA using a DMA as an example of a data transfer device between memories according to the present invention will be described. FIG. 1 shows a computer system configured using the structured transfer DMA of the present embodiment. As shown in FIG. 1, the structured transfer DMA1 according to the present invention is mounted on a circuit capable of accessing a target memory (main memory 2 shown) in a computer system via a system bus. FIG.
FIG. 2 is a block diagram showing a circuit configuration of the structured transfer DMA in the system of FIG. 1 in more detail. In FIG. 1, a memory read circuit 1A is provided on the input side and a memory write circuit 1B is provided on the output side. The side and output circuits can be structured transfer DMA according to the present invention, and either one of the inputs and outputs can be a conventional DMA.

FIG. 3 is a block diagram showing a basic configuration of an embodiment of the structured transfer DMA according to the present invention. Both the input and output circuits in FIG. 2 have the structure shown in FIG.
In accordance with the setting of the address setting circuit 11, a part of the data at a given interval in an arbitrary address space is extracted by the operation of the read / write circuit 13 using the address generated by the address generation circuit 12, and the data of the data group in the different address space is extracted. It is possible to write as some data. In setting the target address, the address setting circuit 11 determines the size of one data group as the group size, and sets the target data position and size in the group from the continuous data as the target data position and the target data size. Only the designated data can be read and written in a group unit, and further, the read and write start addresses and the entire data to be transferred as a read and write processing circuit can be designated and set.

FIG. 4 shows the structured transfer D according to the invention of FIG.
It is a figure showing the flow chart of the operation about MA. The procedure of the operation will be described with reference to FIG. 4. First, an initialization process is performed. This is the main processor (not shown)
, The "start address", "group size", "target data position", "target data size", and "number of processings" are set in the address setting circuit 11 of the structured transfer DMA (step S1). Next, the main processor instructs the structured transfer DMA to start transfer (step S2), and processing is started in the structured transfer DMA.

In the structured transfer DMA processing, the transfer processing (step S3-1) and the transfer end processing (step S3-2)
Consisting of In the transfer process, “start address + target data position” is obtained from the value that has already been set, data corresponding to “target data size” is specified from the obtained position, and the data is obtained by the reading circuit 1A. The data is output to the designated “start address” of the write destination set similarly (step S3-1-1).

After that, the respective "group size" values, which are set values, are added to the read address and the write address in the previous step, respectively, and read / write (transfer) is performed in the same manner as in the previous step (step S3-1). −
2) In order to sequentially repeat this step until the set “process count” value is reached, the set process count value is subtracted, and the transfer process ends when the process count is “0” (step S).
3-1-3).

In the end processing (step S3-2) performed as the next step following the data transfer, the cache is purged in the cache structure attached to improve the performance of the transfer processing (step S3-2). −
1) Initialize circuits such as a counter set for performing a transfer operation (step S3-2-2). This end processing step is a step performed when the number of times of processing is set to “0” in the transfer processing step in step S3-1, omitting each step in step S3-1.

Here, this embodiment will be described below by taking a more specific example. In general terms, for example,
The structure of the original data read from the memory reading circuit and before being written is, respectively, structure {int a, b, c, d; {s [100]; structure} int a, b, c, d, e, f; Δt [100]; And, as the transfer process, It is about the case where it is going to perform.

The setting conditions in each circuit of the structured transfer DMA according to the embodiment of the present invention are determined from the above conditions.
It is the "group size" of the memory reading circuit 1A.
For four int, “target data position” for 0, and “target data size” for two int. Then, in the memory writing circuit 1B, the "group size" is set to six int, the "target data position" is set to the third int, and the "target data size" is set to two int.

FIGS. 5A and 5B show an example of data transfer by DMA, wherein FIG. 5A shows a conventional data transfer and FIG. 5B shows a data transfer according to the present invention.
In the structured transfer DMA according to the present invention, taking the above-mentioned setting conditions as an example, first, counting from the designated start address of the reading circuit 1A, the data at the position of the target data (the head of the four groups) is targeted. A certain number (for two) is read (address R1). Next, the read data is counted from the designated start address of the writing circuit to an address serving as a target data position (third from the top of the six groups),
Data is written for the designated number (two) (address W1). Thereafter, the structured transfer DMA adds values (for four and six) for each group size set for the user to the respective address counters for reading and writing. Then, transfer is performed for the next group (FIG. 5).
Address R2 → address W2). As in this example, the group size (4 pieces) to be read in a series of processing and the group size (6 pieces) to be written may be different. At this time, the value to be added can be a negative number.

At this time, it is possible to buffer some data to be written and to continuously write the data. In addition, in the case of the present embodiment, since the memory space for reading and writing is overlapped, a general The performance can be improved by attaching a cache structure used in the processor. Further, in the present embodiment, there is only one kind of the data group. However, based on a method of providing a plurality of data groups in one memory transfer circuit or data read from a certain memory reading circuit. By setting another memory reading circuit and setting a structure such as indirect reference and data read from the outside in a register in the DMA, it is possible to construct a structure in which the interval of data to be operated is changed as needed.

[0019]

【The invention's effect】

According to the first aspect of the present invention, reading and writing are designated in units of continuous data at a constant interval, and data is transferred between memories. Only a part of variables in a structure such as C language is processed and structured. In the data group, both the transfer source and the transfer destination can process a part of the data, reducing the load on the main processor to prepare the data, increasing the processing speed, and improving the work efficiency. improves.

According to the second aspect of the invention, in addition to the first aspect, even when different data structures are used at the transfer destination and the transfer source, a part of the data in the unit structure can be subjected to the transfer processing. .

According to the third aspect of the present invention, in addition to the first and second aspects, the present invention provides a means for setting a condition for giving a transfer processing target as a part of a unit structure of a data structure. Enables realization.

According to a fourth aspect of the present invention, in addition to the first to third aspects, a memory having a fixed memory space is provided by further providing a condition for setting an object of data transfer processing by an arrangement in the memory space. Can correspond to

Effect of Claim 5: In addition to the effects of Claims 1 to 4, the present invention provides means for embodying the processing target in the memory of Claim 4 and enables practical use.

[Brief description of the drawings]

FIG. 1 illustrates a computer system configured using a structured transfer DMA according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a more detailed circuit configuration of a structured transfer DMA in the system of FIG. 1;

FIG. 3 is a block diagram showing a basic configuration of an embodiment of a structured transfer DMA according to the present invention.

4 is a diagram showing a flowchart of an operation relating to the structured transfer DMA according to the present invention of FIG. 3;

5A and 5B show an example of data transfer by DMA, wherein FIG. 5A shows a conventional data transfer and FIG. 5B shows a data transfer according to the present invention.

[Explanation of symbols]

1: structured transfer DMA, 1A: memory reading circuit, 1
B: memory writing circuit, 2: main memory, 3: circuit device such as another processor, 11: address setting circuit, 1
2 ... Address generation circuit, 13 ... Read / write circuit.

Claims (5)

[Claims] 1. A memory space in a memory which can access data stored by designating an address for each unit memory element, wherein a unit memory element having a predetermined data capacity is assembled. The memory unit that constitutes a structured memory space is used as at least one of the memory-to-memory data transfers. A rule is used in which a structure is expressed by a continuous unit structure, and a unit memory element specified based on the expressed unit structure is subjected to transfer processing and data is transferred between them. Data transfer device between memories. 2. The method according to claim 1, wherein the unit memory element in the memory in which data is transferred between the memories is structured according to different structuring rules at a transfer source and a transfer destination, and the transfer of the memories at the transfer source and the transfer destination is performed. 2. The data transfer device between memories according to claim 1, wherein the control is performed based on conditions set in accordance with the different structuring rules. 3. A structure setting condition corresponding to the structuring rule, wherein a size of the unit structure, a position and a size of a unit memory element to be transferred in the unit structure are prepared. The data transfer device between memories according to claim 2. 4. The apparatus according to claim 1, wherein an object to be subjected to a data transfer process is designated by setting an arrangement of said continuous unit structures in said memory space. Data transfer device between memories. 5. The method according to claim 1, wherein a start address of the unit structure to be transferred and the number of processed structural units are prepared as the arrangement of the continuous unit structures in the memory space. 5. The data transfer device between memories according to any one of claims 4 to 4.