JPH10247452A - Cold-electron emitting element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a tip sharp via reactive ion etching(RIE), use an inexpensive substrate easily having a large area, and maintain the homogeneity of the characteristic of an element regardless of the large area by using non-monocrystalline silicone as the emitter material of the cold-electron emitting element. SOLUTION: This cold-electron emitting element is laminated with an insulating substrate 1, a conductive layer 2, an insulating layer 4, and a gate electrode 5 in sequence. An opening section A reaching the conductive layer 2 is provided on the gate electrode 5 and insulating layer 4, and an emitter layer 3 made of non-monocrystalline silicone is formed on the conductive layer 2 in the opening section A in no contact with the gate electrode 5. The emitter layer 3 functions as a member directly emitting electrons from its surface, and it is preferably formed into a conical shape. Polysilicone or amorphous silicone with about 0.1-10<10> Ω.cm is used for the material of the emitter layer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission type cold electron emitting device that emits electrons by a strong electric field and a method of manufacturing the same, and more particularly, to an electron generation device such as an optical printer, an electron microscope, and an electron beam exposure device. As an electron source or as an electron gun, or as a micro-illumination source for an illumination lamp, and in particular, an array of F
This technology is useful as an electron source of an EA (Field Emi-tter Array).

[0002]

2. Description of the Related Art Conventionally, a cathode ray tube has been widely used as an electronic display device. However, the cathode ray tube consumes a large amount of energy to emit thermoelectrons from a cathode of an electron gun, and is structurally large. There were problems such as requiring a volume.

[0003] For this reason, there has been a demand for a flat display in which cold electrons can be used instead of thermoelectrons, thereby reducing the energy consumption as a whole and further reducing the size of the device itself. There is also a strong demand for such a flat display to realize high-speed response and high resolution.

As a structure of such a flat display utilizing cold electrons, a structure in which minute cold electron-emitting devices are arranged in an array in a flat plate cell in a high vacuum is considered to be promising. As a cold electron-emitting device used therefor, a field-emission cold electron-emitting device utilizing a field emission phenomenon has been receiving attention. In this field emission type cold electron-emitting device, when the intensity of an electric field applied to a substance is increased, the width of an energy barrier on the surface of the substance is gradually reduced according to the intensity,
When the electric field intensity becomes a strong electric field of 10 ⁷ V / cm or more, electrons in a substance can break through the energy barrier by a tunnel effect, and the phenomenon that electrons are emitted from the substance is used. In this case, since the electric field complies with Poisson's equation, if a portion where the electric field is concentrated is formed on a member (emitter) that emits electrons, cold electrons can be efficiently emitted with a relatively low extraction voltage.

As a general example of such a field emission type cold electron emitting element, a cone type cold electron emitting element having a sharp tip as shown in FIG. 4 can be exemplified.
In this device, an insulating layer 43 and a gate electrode 44 are sequentially laminated on a conductive layer 42 on an insulating substrate 41, and the insulating layer 43 and the gate electrode 44
2 is formed. At least the gate electrode 4 is provided on the conductive layer 42 in the opening A.
A conical (cone-shaped) emitter 45 having a point-like projection Po is formed so as not to come into contact with 4.

[0006] Such cone type emitters are different from each other in their manufacturing method, and are different from Spindt type emitters (J. Vac. Sci. An.
d Tech. Bll. 468 (1993)) and a Si cone type emitter (Tec.
h.Dig.IVMC., (1991) p26).

First, an example of manufacturing a cold electron-emitting device having a Spindt-type emitter will be described with reference to FIGS. 5 (a) to 5 (d).

First, as shown in FIG. 5A, an insulating layer 53 and a gate electrode 54 are sequentially formed on an insulating substrate 51 on which a conductive layer 52 has been formed by a sputtering method or a vacuum evaporation method. . Subsequently, a photolithography method and reactive ion etching (in general, RIE,
It is simply called RIE. ) And the insulating layer 5
3 and a part of the gate electrode 54 are etched such that a circular hole (gate hole) is opened until the conductive layer 52 is exposed.

Next, as shown in FIG. 5B, a lift-off material 55 is formed only on the gate electrode 54 by oblique evaporation. The material of the lift-off material 55 is Al, MgO
And so on.

Subsequently, as shown in FIG. 5C, a metal material for the emitter 56 is deposited on the insulating substrate 51 by normal anisotropic deposition from a direction perpendicular to the insulating substrate 51. At this time, as the vapor deposition progresses, the cone-shaped emitter 55 is formed on the emitter wiring 52 in a self-aligned manner at the same time as the opening diameter of the gate hole is reduced. The vapor deposition is performed until the gate hole is finally closed. The material of the emitter 56 is M
o, Ni, etc. are used.

Finally, as shown in FIG. 5D, the lift-off material 55 is peeled off by etching, and the gate electrode 54 is patterned if necessary. Thus, a cold electron emitting device having a Spindt-type emitter is obtained.

In such a Spindt-type emitter, a cone-shaped emitter can be easily formed in a self-aligned manner by anisotropic vapor deposition, so that a wide range of emitter materials can be selected. This has the advantage that any type of substrate, in particular, a glass substrate that can have a large area can be used.

Next, an example of manufacturing a cold electron-emitting device having a Si cone-type emitter will be described with reference to FIGS.

First, as shown in FIG.
The i-substrate 61 is thermally oxidized to form a silicon oxide layer on the surface, and the silicon oxide layer is patterned into a circular shape using a photolithography method, thereby forming a circular silicon oxide layer 62 for an etching mask. This silicon oxide layer 62 also functions as a lift-off material as described later. Note that the diameter of the silicon oxide layer 62 corresponds to the gate diameter.

Next, as shown in FIG. 6B, the Si substrate 61 is etched by RIE under a condition of a high side etch rate to form an emitter 63.

Subsequently, as shown in FIG. 6C, a silicon oxide layer 64 for sharpening the tip of the emitter is formed on the surfaces of the Si substrate 61 and the emitter 63 by thermal oxidation. Due to the stress generated when the silicon oxide layer 64 is formed, the tip of the emitter 63 inside the silicon oxide layer 64 is easily sharpened.

Then, as shown in FIG. 6D, an insulating film 65 and a gate electrode 66 are laminated by a vapor deposition method.

Finally, as shown in FIG. 6E, the silicon oxide layer 62 for the etching mask, which also functions as a lift-off material, is lifted off by etching, and the silicon oxide layer 64 on the surface of the emitter 63 is removed by etching. . Then, the gate electrode 66 is patterned as necessary. As a result, a cold electron-emitting device having a Si cone-type emitter is obtained.

Such a Si-cone type emitter has an advantage that it can form a very sharp tip shape which is hardly attainable by ordinary physical methods considered conventionally.

[0020]

However, in the case of the above-mentioned Spindt-type emitter, the anisotropic vapor deposition method is used, but since there are no vapor-deposited particles that are diffused during vapor deposition, the substrate is not made. It is difficult to perform uniform vapor deposition on the whole, so that the state of the plurality of cold electron emitting devices on the same substrate varies individually, and it is difficult to keep the characteristics of each cold electron emitting device uniform. There was a problem that it was technically difficult. Since the tendency of the variation of the cold electron-emitting devices becomes particularly remarkable particularly when the substrate is made large in area and a large number of emitters are formed, it is extremely difficult to keep the characteristics uniform. It can be said that.

On the other hand, in the case of the Si cone type emitter, the RIE which can uniformly etch over the entire substrate is used without using an anisotropic deposition method at the time of forming the Si cone type emitter. It is possible to maintain the uniformity of the characteristics of the plurality of cold electron-emitting devices. However, since thermal oxidation treatment of single crystal Si is indispensable at the time of formation, there is a problem that a substrate to be used is limited to an expensive single crystal Si substrate. Further, since single crystal Si having a large area such as a glass substrate is not available, there has been a problem that it is practically impossible to increase the area of the cold electron-emitting device.

From the viewpoint of concentrating an electric field on the emitter, it is desired that the tip shape of these cone-shaped emitters has a radius of curvature as small as possible. It can be said that forming an ideal shape uniformly over a large area is extremely difficult, if not impossible.

The present invention has been made to solve the above-mentioned problems of the prior art, and does not use anisotropic deposition when forming an emitter of a field emission type cold electron emission element.
By using a technique such as RIE, the tip can be sharpened, and a substrate other than a single-crystal Si substrate, which can be easily enlarged, for example, a glass substrate that can be obtained at a lower cost than a single-crystal Si substrate Can be used,
Further, it is an object of the present invention to provide a technique capable of maintaining uniform characteristics of a plurality of cold electron emitting elements in a substrate even when the substrate has a large area.

[0024]

The present inventors have found that the above object can be achieved by using a non-single crystal, for example, amorphous silicon, instead of metal or single crystal Si, as the emitter material of the cold electron emission element. Thus, the present invention has been completed. That is, amorphous silicon has 35
It is a material capable of forming a film uniformly over a large area at a low temperature of 0 ° C. or less, and thus can be formed on a substrate that is inexpensive and has a large area, for example, a glass substrate. Furthermore, when a specific metal such as Al or Au is laminated on the surface of the amorphous silicon, if a low-temperature annealing treatment at 350 ° C. or less is performed, a low-temperature solid-state reaction occurs at the interface between the two layers, and the amorphous silicon layer is selectively etched. A layer is created on the surface that allows for Therefore, when amorphous silicon is applied to the emitter material, the chemical reaction can be used to sharpen the emitter.

That is, the means provided by the present invention in order to solve the above-mentioned problems is that, as set forth in claim 1, an insulating substrate, a conductive layer, an insulating layer and a gate electrode are sequentially laminated,
An opening reaching the conductive layer is provided in the gate electrode and the insulating layer, and the emitter is formed on the conductive layer in the opening so as not to contact the gate electrode.
A cold electron emission device characterized in that the emitter material is non-single-crystal silicon.

More preferably, as described in claim 2, the cold electron-emitting device according to claim 1 is a basic structure, wherein the non-single-crystal silicon is amorphous silicon.

Preferably, as set forth in claim 3,
The non-single-crystal silicon is a cold electron-emitting device, wherein the non-single-crystal silicon is hydrogenated amorphous silicon.

Preferably, as set forth in claim 4,
A cold electron-emitting device according to claim 1, wherein the non-single-crystal silicon is hydrogenated amorphous silicon doped with impurities.

More preferably, according to a fifth aspect of the present invention, the cold electron emission element according to any one of the first to fourth aspects has a basic structure, wherein the insulating substrate is a glass substrate. is there.

Preferably, as set forth in claim 6,
An insulating substrate, a conductive layer, an insulating layer, and a gate electrode are sequentially stacked, an opening reaching the conductive layer is provided in the gate electrode and the insulating layer, and an emitter is provided on the conductive layer in the opening. A method for manufacturing a field emission type cold electron emission element formed so as not to contact a gate electrode, comprising: (a) forming a conductive layer on an insulating substrate; (b) forming a non-conductive layer on the conductive layer. Forming an emitter layer made of single crystal silicon; (c) forming a circular etching mask layer on the emitter layer; (d) processing the emitter layer into a truncated cone by reactive ion etching. Exposing the conductive layer; (e) forming an emitter sharpening material layer on the processed emitter layer and annealing the resulting material to form an emitter sharpening reaction layer on the emitter surface; Emi An insulating material and a gate electrode material are sequentially laminated on the surface on the side of the sharpening reaction layer to form an insulating layer and a gate electrode on the conductive layer, and an insulating material layer on the etching mask layer. Forming a gate electrode material layer; and (g) removing the etching mask layer as a lift-off material using the etching solution for the etching mask layer, and further stacking thereon an insulating material layer and a gate electrode. Removing the material layer and removing a part of the emitter sharpening reaction layer and part of the emitter layer;
A method for manufacturing a cold electron-emitting device, comprising all the steps of (g).

More preferably, according to a seventh aspect of the present invention, based on the method of manufacturing a cold electron emitting device according to the sixth aspect, the step (e) includes the step of (e) wherein the material of the emitter sharpening material layer is aluminum. This is a method for manufacturing a cold electron-emitting device.

Preferably, as set forth in claim 8,
A method for manufacturing a cold electron-emitting device according to claim 6, wherein the annealing in the step (e) is performed in air and at a temperature of 300 ° C. or less.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to the drawings. FIG. 1 is a cross-sectional perspective view of a cold electron emitting device of the present invention. As shown in the figure, this cold electron emission element has a structure in which an insulating substrate 1, a conductive layer 2, an insulating layer 4, and a gate electrode 5 are sequentially stacked. An opening A reaching the conductive layer 2 is formed between the gate electrode 5 and the insulating layer 4.
Is provided on the conductive layer 2 in the opening A.
The conical emitter 3 made of non-single-crystal silicon is formed so as not to contact the gate electrode 5.

In the present invention, the insulating substrate 1 is used as a supporting insulating substrate for a cold electron emission element, and an insulating substrate that can be easily enlarged can be preferably used. As such an insulating substrate, a glass substrate, a ceramic substrate, a quartz substrate, or the like can be used.
Note that a substrate in which an insulating film is formed over the surface of single crystal silicon can also be used.

The conductive layer 2 is formed of a material having low electric resistance and good adhesion to the insulating substrate 1. Further, it is formed of a material having resistance to an etching gas used for RIE used for forming an emitter 5 described later or an etching solution used for lift-off. This is to make the conductive layer 2 function as an etching stopper when forming the emitter. A particularly preferred example of such a material is a Cr film, or an Al layer and a Cr film.
One of the laminated films composed of layers can be given.

The thickness of the conductive layer 2 is not particularly limited as long as sufficient electric resistance and adhesion can be obtained.
The thickness is 5 to 0.5 μm, preferably 0.1 to 0.3 μm.

The emitter 3 functions as a member that directly emits electrons from its surface. In the present invention,
The shape of the emitter 3 is preferably a conical shape.

As the material of such an emitter 3, non-single-crystal silicon is used in the present invention. As the non-single-crystal silicon, for example, polysilicon or amorphous silicon having a resistivity of about 0.1 to 10 ¹⁰ Ω · cm is used.
In this case, it also functions as a resistance layer at the time of driving the element, and the emission current can be stabilized. The amorphous silicon used here means silicon in which a peak showing crystallinity is not observed by analysis by a thin film X-ray diffraction method.
Therefore, amorphous silicon includes silicon that is partially microcrystalline. Note that the control of the resistivity of amorphous silicon can be easily performed by adjusting the type and dose of the dopant of the silicon sputtering target used at the time of film formation.

Further, particularly when hydrogenated amorphous silicon is used as the emitter material, it is possible to obtain a cold electron-emitting device having good structure controllability and electric characteristics. First, with regard to structure controllability, hydrogenated amorphous silicon has an amorphous state with particularly few microcrystals, so that more uniform etching can be performed when forming a cone by RIE, thereby increasing the process tolerance and increasing the area. Becomes easier. Regarding the electrical characteristics, in the hydrogenated amorphous silicon, as is well known, the doping of impurities is further facilitated, and impurity control close to that of single crystal silicon can be performed. Therefore, a wide range of resistance value control is possible.

In particular, a hydrogenated amorphous silicon film doped with phosphorus at a high concentration exhibits n-type electric conduction, and the specific resistance can be reduced to several Ω · cm or more. As a result, it is possible to increase the emission current of the cold electron emission element and lower the emission voltage. On the other hand, a hydrogenated amorphous silicon film doped with boron at a high concentration exhibits p-type electric conduction, and has a relatively high specific resistance but a limited current is dominant, so that a very stable cold electron-emitting device can be obtained.

The thickness (height) of the emitter 3 can be appropriately determined as necessary, but is usually 0.3 to 2 μm.
It is preferable that

The insulating layer 4 is a layer for electrically insulating the conductive layer 2 from the gate electrode 5. Such an insulating layer 4
Can be formed from a known material used as an insulating layer of a cold electron emission element, and examples thereof include silicon oxide which exhibits good insulating properties and can be formed by an anisotropic vapor deposition method.

The thickness of the insulating layer 4 depends on the emitter wiring 2
It is sufficient that sufficient insulation is maintained between the gate electrode 5 and the gate electrode 5, for example, 0.2 to 2 μm, preferably 0.3 to 0.
7 μm.

The gate electrode 5 is an electrode for concentrating a strong electric field on the emitter 3. As a material of the gate electrode 5, a material having a high melting point from the viewpoint of withstand voltage and having a resistance to an etching solution used at the time of forming an emitter can be used. Preferred examples thereof include Cr, W, Ta and Nb can be mentioned, for example, any of them may be appropriately selected and used. Considering the merit that the cold electron emitting device according to the present invention is easy to manufacture, it is particularly preferable to use Nb among these.

The thickness of the gate electrode 5 can be appropriately determined as needed, and is set to 0.1 to 0.5 μm.

Next, a method of manufacturing the cold electron emitting device of the present invention using amorphous silicon as the material of the emitter 3 will be described in detail with reference to FIG.

Step (a) First, a conductive layer 2 is formed on an insulating substrate 1 by a sputtering method or the like (FIG. 2A). Also in this case, the conductive layer 2
For example, a Cr film or an Al / Cr laminated film can be preferably used.

Step (b) Next, an amorphous silicon layer is formed as the emitter layer 3 on the conductive layer 2 (FIG. 2B). In this case, the amorphous silicon layer is formed by a sputtering method capable of forming a film in a temperature range from room temperature to about 350 ° C.
It is preferable to form a film thereon. When the film is formed at such a temperature, the thermal expansion of the insulating substrate 1 can be kept in a small range, so that a glass substrate can be used.

In the case where the amorphous silicon layer is a hydrogenated amorphous silicon layer, a conductive film is formed by a plasma CVD method (CVD indicates chemical vapor deposition) instead of the sputtering method. A film is formed on the layer 2. An example of conditions for forming a phosphorus-doped amorphous silicon film having a specific resistance of several to several tens Ω · cm is as follows: substrate temperature 250 ° C. introduced gas SiH ₄ (10% hydrogen dilution): 300 scc
m, H ₂ : 150 sccm and PH ₃ (1000p
pm hydrogen dilution): a mixed gas power of 90 sccm, a power of 60 W, and a gas pressure of 1 Torr.

Step (c) Next, an etching mask material is formed on the emitter layer 3 by a vapor deposition method, a sputtering method, or the like, and is patterned into a circular shape using a photolithography method to form the etching mask layer 6. It is formed (FIG. 2C).

The etching mask layer 6 is formed from a material having resistance to RIE described later. As such a material, SiO ₂ can be preferably mentioned.

The diameter of the circular pattern is about 1.0 to 2.0 μm in consideration of the characteristics of the cold electron emitting element, the difficulty of operation according to the design rule of the photolithography method, the yield of the etching step, and the like. Is preferred.

Step (d) Next, the emitter layer 3 is etched by RIE under conditions of a high side etch rate until the conductive layer 2 is exposed. Thereby, the emitter layer 3 is processed into a truncated cone shape (FIG. 2D). This is because the entire emitter layer 3 is isotropically etched. As such RIE conditions, for example, the introduced gas SF ₆ , O _{2, and the} like can be set to 30 to 70 sccm, power 80 to 120 W, and gas pressure 4 to 5 Pa. In particular, SF ₆ : O ₂ = 3: 1
By using the mixed gas (flow rate ratio), the etched surface of the amorphous silicon layer becomes flat and the emitter layer 3 having a substantially trapezoidal cross section can be processed.

Step (e) Subsequently, an emitter sharpening material layer 7a is formed on the side surface of the emitter layer 3 and the surface of the conductive layer 2 by a sputtering method or an oblique rotation evaporation method (FIG. 2E). Examples of the material for sharpening the emitter include Al, Au, and the like as materials that cause a solid-phase reaction at the interface with Si. However, it is particularly preferable to use Al from the viewpoint of etching selectivity. The thickness of the film is determined by the remaining amount of the sharpened emitter layer 3 on the side of the etching mask layer 6, that is, the size of the upper surface of the truncated cone, but is usually preferably in the range of 0.1 μm to 0.5 μm.

Further, an annealing treatment for sharpening is performed. As the annealing conditions, the atmosphere is air or oxygen, the temperature is 350 ° C. or less, and the time is 10 minutes or more. As a result, a solid phase reaction occurs at the interface between the emitter layer 3 and the emitter sharpening material layer 7a, and an emitter sharpening reaction layer 7b is generated on the surface of the emitter layer 3 (FIG. 2 (e ')).

Step (f) Next, a SiOx film is formed on the surface of the insulating substrate 1 on the conductive layer 2 side.
By stacking an insulating material such as Nb and a gate electrode material such as Nb by an evaporation method or the like, the insulating layer 4 is formed on the conductive layer 2.
And the gate electrode 5, and an insulating material layer 4a and a gate electrode material layer 5a are formed on the etching mask layer 6 (FIG. 2F). Here, when the insulating layer 4 is formed by a vapor deposition method, ozone is used as a reaction gas at 10%.
Oxygen gas containing a certain amount of gas is introduced, and SiO
It is preferable to form a film using a chimney-type resistance heating method in which is filled. The insulating layer 4 formed by such a method shows good insulating properties.

Step (g) Next, the etching mask layer 6 as a lift-off material is removed by etching using a buffered hydrofluoric acid solution. As a result, the stacked body composed of the insulating material layer 4a and the gate electrode material layer 5a stacked thereon is peeled off. As a result, a cold electron-emitting device having the conical emitter layer 3 is obtained (FIG. 2G).

As described above, in the present invention, when forming the emitter of the field emission type cold electron-emitting device, the tip is sharpened by utilizing RIE or the like without using anisotropic vapor deposition. And single crystal Si
It is possible to use a substrate other than the substrate, which can be easily increased in area, for example, a glass substrate, and to maintain uniformity of characteristics of a plurality of cold electron emission elements in the substrate even when the substrate is enlarged. .

[0059]

EXAMPLES The production examples of the cold electron-emitting device of the present invention will be specifically described in the following examples.

Step (a) First, Cr was formed as a material for the conductive layer 2 by sputtering to a thickness of about 0.2 μm on a glass substrate as the insulating substrate 1 (FIG. 2A).

Step (b) Next, as the emitter layer 3 on the conductive layer 2, the following conditions: substrate temperature 250 ° C. introduced gas SiH ₄ (10% hydrogen dilution): 300 scc
m, H ₂ : 150 sccm and PH ₃ (1000p
(pm hydrogen dilution): A 90-cm mixed gas power of 60 W, a gas pressure of 1 Torr, and a phosphorus-doped hydrogenated amorphous silicon layer having a thickness of 1 μm was formed by a plasma CVD method (FIG. 2).
(B)).

Step (c) Next, silicon oxide is deposited to a thickness of about 0.2 μm by a reactive evaporation method.
Thick film, and then by photolithography,
An etching mask layer 6 was formed by patterning into a circular mask shape having a diameter of 1.2 μm for forming an emitter (FIG. 2C).

Step (d) Next, the phosphorus-doped hydrogenated amorphous silicon layer 3c was etched for 3 minutes by RIE under the following conditions; introduced gas SF ₆ : ₆₀ sccm, power 100 W, and gas pressure 4.5 Pa (FIG. 2).
(D)). As a result, the phosphorus-doped hydrogenated amorphous silicon layer serving as the emitter layer 3 was processed into a truncated cone shape.

Step (e) Subsequently, Al was sputtered to a thickness of 0.3 μm to form an emitter sharpening material layer 7a (FIG. 2 (e)). At this time, Al was uniformly deposited on the side surfaces of the emitter layer 3 having a truncated cone shape.

Further, an annealing treatment was performed to sharpen the emitter layer 3. Annealing conditions are 200 ° C, 3
0 minutes (in air). As a result, an emitter sharpening reaction layer 7b is formed on the surface of the emitter layer 3, and the emitter layer 3
Was sharpened (FIG. 2 (e ')).

Step (f) Next, a silicon oxide film having a thickness of about 0.8 μm is formed as the insulating layer 4 under the following conditions: evaporation source SiO reactive gas oxygen + 10% ozone evaporation under a vacuum degree of 5 × 10 ^-6 Torr Then, N on the gate electrode material
b was deposited to a thickness of about 0.3 μm (FIG. 2 (f)). As a result, the insulating layer 4 and the gate electrode 5 located around the emitter layer 3 could be formed in a self-aligned manner with a certain gap from the emitter layer 3 without contacting the emitter layer 3. .

Step (g) The etching mask layer 6 is lifted off by immersing the material obtained in the step (f) in a buffered hydrofluoric acid solution at room temperature for 2 minutes, and the insulating material layer 4a And the laminated body of the gate electrode material layer 5b peeled off. Thus, the cold electron-emitting device shown in FIG. 2 (g) was obtained.

An array in which 100 cold electron-emitting devices described above were integrated was prototyped, tested and evaluated as follows. That is,
For an element having a structure in which the distance between the emitter electrode and the gate electrode of each element is about 0.6 μm, a glass plate member having a transparent electrode (anode) coated with a fluorescent material has a thickness of 500 μm.
V is applied and the electrodes are opposed to each other at a distance of 30 mm.
When an extraction voltage was applied between the gate electrodes with a polarity where the gate electrode side was positive, good emission characteristics were exhibited.

Here, the low-temperature solid-state reaction occurring at the interface between silicon and a specific metal used in the present invention will be described with reference to FIGS. 3 (a) and 3 (b).

First, as shown in FIG. 3A, for example, a 0.1 μm Al32 film is formed on a single crystal silicon 31.
When heated to about 200 ° C in air, it takes about 10 minutes.
As shown in (b), a 0.1 μm silicon oxide 33 grows on the surface. At this time, Al32 is silicon oxide 3
The Al-Si layer 34 diffuses into the three underlying silicon layers 31.
Is formed. This reaction is called a low-temperature solid-state reaction or a low-temperature interfacial reaction, and it is known that a similar reaction is also observed in Au. However, the mechanism by which such a reaction occurs at a low temperature has not yet been established.
Further, it is clear from the experience of the inventor that amorphous silicon has higher reactivity in such a low-temperature solid-state reaction than single-crystal silicon. Here, silicon oxide 33 generated on the surface of silicon 31 and Al-
The Si layer 34 can be etched with hydrofluoric acid, and can be used for sharpening the emitter, as described in detail above, from the selectivity of etching with silicon.

[0071]

According to the present invention, non-single crystal, not metal or single crystal Si, is used as the emitter material of the cold electron emission device.
For example, by using amorphous silicon, the tip can be sharpened by using RIE or the like without using anisotropic deposition.
It is possible to use a substrate other than the substrate, which can be easily increased in area, for example, a glass substrate, and to maintain uniformity of characteristics of a plurality of cold electron emission elements in the substrate even when the substrate is enlarged. It became so.

Therefore, a cold electron emitting device operable at a low voltage can be obtained over a large area. Further, even when applied to a flat panel display, it is possible to obtain a high-quality image on a large screen.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional perspective view of a cold electron emission element of the present invention.

FIG. 2 is a manufacturing process diagram of the cold electron emission device of the present invention.

FIG. 3 is an explanatory view of one step of a method for manufacturing a cold electron emission device of the present invention.

FIG. 4 is a schematic sectional perspective view of a conventional cold electron emission element.

FIG. 5 is a manufacturing process diagram of a conventional cold electron emission element.

FIG. 6 is another manufacturing process diagram of the conventional cold electron-emitting device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Conductive layer 3 ... Emitter layer 4 ... Insulating layer 4a ... Insulating material layer 5 ... Gate electrode 5a ... Gate electrode layer 6 Etching mask layer 31 Silicon 32 Al 33 Silicon oxide 34 Al-Si layer 41 Insulating substrate 42 Conductive layer 43 Insulation Layer 44 Gate electrode 45 Emitter 51 Insulating substrate 52 Conductive layer 53 Insulating layer 54 Gate electrode 55 Lift-off material 56 Emitter 61 ..Si substrate 62 ... Silicon oxide layer 63 ... Emitter 64 ... Silicon oxide layer 65 ... Insulating film 66 ... Gate electrode A ... Opening Po ... Point projection

Claims (8)

[Claims] An insulating substrate, a conductive layer, an insulating layer, and a gate electrode are sequentially laminated, an opening reaching the conductive layer is provided in the gate electrode and the insulating layer, and the opening in the opening is provided on the conductive layer. A field emission type cold electron-emitting device, wherein the emitter is formed so as not to contact the gate electrode, wherein the emitter material is non-single-crystal silicon. 2. The cold electron-emitting device according to claim 1, wherein said non-single-crystal silicon is amorphous silicon. 3. The cold electron-emitting device according to claim 1, wherein said non-single-crystal silicon is hydrogenated amorphous silicon. 4. The cold electron emitting device according to claim 1, wherein said non-single-crystal silicon is hydrogenated amorphous silicon doped with impurities. 5. The cold electron-emitting device according to claim 1, wherein said insulating substrate is a glass substrate. 6. An insulating substrate, a conductive layer, an insulating layer and a gate electrode are sequentially laminated, an opening reaching the conductive layer is provided between the gate electrode and the insulating layer, and an opening is formed on the conductive layer in the opening. A method for manufacturing a field emission type cold electron emitting element, wherein an emitter is formed so as not to contact the gate electrode; (a) forming a conductive layer on an insulating substrate; (b) forming the conductive layer (C) forming a circular etching mask layer on the emitter layer; (d) forming the emitter layer into a truncated cone by reactive ion etching. Exposing the conductive layer while processing; (e) forming an emitter sharpening material layer on the processed emitter layer and then annealing to form an emitter sharpening reaction layer on the emitter surface; (f) insulating By sequentially laminating an insulating material and a gate electrode material on the surface of the substrate on the side of the emitter sharpening reaction layer, an insulating layer and a gate electrode are formed on the conductive layer, and an insulating material is formed on the etching mask layer. Forming a layer and a gate electrode material layer; and (g) using the etchant for the etching mask layer to remove the etching mask layer as a lift-off material, and further form an insulating material layer laminated thereon. Removing the gate electrode material layer and removing a part of the emitter sharpening reaction layer and the emitter layer;
A method for manufacturing a cold electron-emitting device, comprising all the steps of (g). 7. The method according to claim 6, wherein in the step (e), the material of the emitter sharpening material layer is aluminum. 8. The method according to claim 6, wherein in the step (e), annealing is performed in air and at a temperature of 300 ° C. or lower.