JPH10247172A - バス・ブリッジ・システムのためのバッファ・リザベーション方法 - Google Patents

バス・ブリッジ・システムのためのバッファ・リザベーション方法

Info

Publication number
JPH10247172A
JPH10247172A JP10031923A JP3192398A JPH10247172A JP H10247172 A JPH10247172 A JP H10247172A JP 10031923 A JP10031923 A JP 10031923A JP 3192398 A JP3192398 A JP 3192398A JP H10247172 A JPH10247172 A JP H10247172A
Authority
JP
Japan
Prior art keywords
bus
bridge
command
data
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10031923A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10247172A5 (enExample
Inventor
Alan L Goodrum
アラン・エル・グッドラム
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Publication of JPH10247172A publication Critical patent/JPH10247172A/ja
Publication of JPH10247172A5 publication Critical patent/JPH10247172A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP10031923A 1996-12-31 1998-01-05 バス・ブリッジ・システムのためのバッファ・リザベーション方法 Pending JPH10247172A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/774,746 US5815677A (en) 1996-12-31 1996-12-31 Buffer reservation method for a bus bridge system
US774746 1996-12-31

Publications (2)

Publication Number Publication Date
JPH10247172A true JPH10247172A (ja) 1998-09-14
JPH10247172A5 JPH10247172A5 (enExample) 2005-08-04

Family

ID=25102158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10031923A Pending JPH10247172A (ja) 1996-12-31 1998-01-05 バス・ブリッジ・システムのためのバッファ・リザベーション方法

Country Status (4)

Country Link
US (2) US5815677A (enExample)
EP (1) EP0851362B1 (enExample)
JP (1) JPH10247172A (enExample)
DE (1) DE69721209T2 (enExample)

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* Cited by examiner, † Cited by third party
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US6820161B1 (en) 2000-09-28 2004-11-16 International Business Machines Corporation Mechanism for allowing PCI-PCI bridges to cache data without any coherency side effects
JP2011018358A (ja) * 2010-09-13 2011-01-27 Tao Logic Systems Llc リンクブリッジ
JP2015154260A (ja) * 2014-02-14 2015-08-24 富士通株式会社 情報処理装置および情報処理装置の制御方法

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US6092141A (en) * 1996-09-26 2000-07-18 Vlsi Technology, Inc. Selective data read-ahead in bus-to-bus bridge architecture
US5815677A (en) * 1996-12-31 1998-09-29 Compaq Computer Corporation Buffer reservation method for a bus bridge system
US5961606A (en) * 1997-06-30 1999-10-05 Sun Microsystems, Inc. System and method for remote buffer allocation in exported memory segments and message passing between network nodes
US5938777A (en) * 1997-07-31 1999-08-17 Advanced Micro Devices, Inc. Cycle list based bus cycle resolution checking in a bus bridge verification system
US6047339A (en) * 1997-10-27 2000-04-04 Emulex Corporation Buffering data that flows between buses operating at different frequencies
US5964859A (en) * 1997-10-30 1999-10-12 Advanced Micro Devices, Inc. Allocatable post and prefetch buffers for bus bridges
US6199131B1 (en) * 1997-12-22 2001-03-06 Compaq Computer Corporation Computer system employing optimized delayed transaction arbitration technique
US6212590B1 (en) * 1997-12-22 2001-04-03 Compaq Computer Corporation Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base
JP4111472B2 (ja) * 1998-05-15 2008-07-02 キヤノン株式会社 通信制御方法及び装置及び通信システム
US6216182B1 (en) * 1998-07-30 2001-04-10 Fore Systems, Inc. Method and apparatus for serving data with adaptable interrupts
US7734852B1 (en) 1998-08-06 2010-06-08 Ahern Frank W Modular computer system
US6405276B1 (en) * 1998-12-10 2002-06-11 International Business Machines Corporation Selectively flushing buffered transactions in a bus bridge
US6286074B1 (en) * 1999-03-24 2001-09-04 International Business Machines Corporation Method and system for reading prefetched data across a bridge system
US6442641B1 (en) * 1999-06-08 2002-08-27 Intel Corporation Handling multiple delayed write transactions simultaneously through a bridge
US6510494B1 (en) 1999-06-30 2003-01-21 International Business Machines Corporation Time based mechanism for cached speculative data deallocation
US6496921B1 (en) 1999-06-30 2002-12-17 International Business Machines Corporation Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions
US6532521B1 (en) * 1999-06-30 2003-03-11 International Business Machines Corporation Mechanism for high performance transfer of speculative request data between levels of cache hierarchy
US6708244B2 (en) * 1999-07-22 2004-03-16 Cypress Semiconductor Corp. Optimized I2O messaging unit
US6418503B1 (en) * 1999-08-19 2002-07-09 International Business Machines Corporation Buffer re-ordering system
US7457896B1 (en) * 1999-08-25 2008-11-25 Seagate Technology Llc Automated register data transfer to reduce processing burden on a processing device
TW449698B (en) * 1999-12-15 2001-08-11 Via Tech Inc Control chipsets and data exchange method among them
US6490644B1 (en) * 2000-03-08 2002-12-03 International Business Machines Corporation Limiting write data fracturing in PCI bus systems
US6708240B1 (en) * 2000-03-31 2004-03-16 Intel Corporation Managing resources in a bus bridge
US6490647B1 (en) 2000-04-04 2002-12-03 International Business Machines Corporation Flushing stale data from a PCI bus system read prefetch buffer
US6578102B1 (en) * 2000-04-18 2003-06-10 International Business Machines Corporation Tracking and control of prefetch data in a PCI bus system
US6594719B1 (en) 2000-04-19 2003-07-15 Mobility Electronics Inc. Extended cardbus/pc card controller with split-bridge ™technology
US6757767B1 (en) * 2000-05-31 2004-06-29 Advanced Digital Information Corporation Method for acceleration of storage devices by returning slightly early write status
US6691200B1 (en) 2001-05-01 2004-02-10 Pericom Semiconductor Corp. Multi-port PCI-to-PCI bridge with combined address FIFOs but separate data FIFOs for concurrent transactions
US6877060B2 (en) * 2001-08-20 2005-04-05 Intel Corporation Dynamic delayed transaction buffer configuration based on bus frequency
US6748497B1 (en) * 2001-11-20 2004-06-08 Cirrus Logic, Inc. Systems and methods for buffering memory transactions
US6957293B2 (en) * 2002-04-15 2005-10-18 International Business Machines Corporation Split completion performance of PCI-X bridges based on data transfer amount
FR2846764B1 (fr) * 2002-11-04 2005-01-14 St Microelectronics Sa Perfectionnement aux systemes electroniques comprenant un bus systeme
US7900017B2 (en) * 2002-12-27 2011-03-01 Intel Corporation Mechanism for remapping post virtual machine memory pages
US6950905B2 (en) * 2003-02-20 2005-09-27 Sun Microsystems, Inc. Write posting memory interface with block-based read-ahead mechanism
US7039747B1 (en) * 2003-12-18 2006-05-02 Cisco Technology, Inc. Selective smart discards with prefetchable and controlled-prefetchable address space
DE10360679B4 (de) * 2003-12-19 2007-04-19 Infineon Technologies Ag Programmgesteuerte Einheit
US7657690B1 (en) * 2005-06-14 2010-02-02 Globalfoundries Inc. Control of PCI memory read behavior using memory read alias and memory command reissue bits
JP2007200169A (ja) 2006-01-30 2007-08-09 Hitachi Ltd ストレージシステム及び記憶制御方法
JP4304676B2 (ja) * 2006-10-31 2009-07-29 日本電気株式会社 データ転送装置、データ転送方法、及びコンピュータ装置
US8935707B2 (en) * 2011-05-16 2015-01-13 Oracle International Corporation System and method for providing a messaging application program interface
CN103562882B (zh) 2011-05-16 2016-10-12 甲骨文国际公司 用于提供消息传送应用程序接口的系统和方法
US9465763B2 (en) * 2013-06-17 2016-10-11 Altera Corporation Bridge circuitry for communications with dynamically reconfigurable circuits
GB2525577A (en) * 2014-01-31 2015-11-04 Ibm Bridge and method for coupling a requesting interconnect and a serving interconnect in a computer system

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US4860193A (en) * 1986-05-22 1989-08-22 International Business Machines Corporation System for efficiently transferring data between a high speed channel and a low speed I/O device
US5586294A (en) * 1993-03-26 1996-12-17 Digital Equipment Corporation Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer
US5542055A (en) * 1993-05-28 1996-07-30 International Business Machines Corp. System for counting the number of peripheral buses in each hierarch connected to primary bus for creating map of peripheral buses to locate peripheral devices
JPH0784807A (ja) * 1993-09-14 1995-03-31 Fujitsu Ltd バッファ管理装置および方法
JPH07175698A (ja) * 1993-12-17 1995-07-14 Fujitsu Ltd ファイルシステム
US5797042A (en) * 1995-03-16 1998-08-18 Intel Corporation Method and apparatus for adjusting the buffering characteristic in the pipeline of a data transfer system
US5615392A (en) * 1995-05-05 1997-03-25 Apple Computer, Inc. Method and apparatus for consolidated buffer handling for computer device input/output
JP3078204B2 (ja) * 1995-06-01 2000-08-21 株式会社東芝 磁気ディスク装置及び磁気ディスク装置におけるバッファ管理方法
US5694556A (en) * 1995-06-07 1997-12-02 International Business Machines Corporation Data processing system including buffering mechanism for inbound and outbound reads and posted writes
US5859988A (en) * 1995-09-29 1999-01-12 Intel Corporation Triple-port bus bridge
US5893926A (en) * 1995-12-08 1999-04-13 International Business Machines Corporation Data buffering technique in computer system
US5815677A (en) * 1996-12-31 1998-09-29 Compaq Computer Corporation Buffer reservation method for a bus bridge system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6820161B1 (en) 2000-09-28 2004-11-16 International Business Machines Corporation Mechanism for allowing PCI-PCI bridges to cache data without any coherency side effects
JP2011018358A (ja) * 2010-09-13 2011-01-27 Tao Logic Systems Llc リンクブリッジ
JP2015154260A (ja) * 2014-02-14 2015-08-24 富士通株式会社 情報処理装置および情報処理装置の制御方法

Also Published As

Publication number Publication date
DE69721209D1 (de) 2003-05-28
US6260095B1 (en) 2001-07-10
EP0851362A1 (en) 1998-07-01
EP0851362B1 (en) 2003-04-23
DE69721209T2 (de) 2003-11-13
US5815677A (en) 1998-09-29

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