FR2846764B1 - Perfectionnement aux systemes electroniques comprenant un bus systeme - Google Patents
Perfectionnement aux systemes electroniques comprenant un bus systemeInfo
- Publication number
- FR2846764B1 FR2846764B1 FR0213753A FR0213753A FR2846764B1 FR 2846764 B1 FR2846764 B1 FR 2846764B1 FR 0213753 A FR0213753 A FR 0213753A FR 0213753 A FR0213753 A FR 0213753A FR 2846764 B1 FR2846764 B1 FR 2846764B1
- Authority
- FR
- France
- Prior art keywords
- improvement
- system bus
- electronic systems
- electronic
- systems
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0213753A FR2846764B1 (fr) | 2002-11-04 | 2002-11-04 | Perfectionnement aux systemes electroniques comprenant un bus systeme |
US10/701,384 US20040193836A1 (en) | 2002-11-04 | 2003-11-04 | Electronic systems comprising a system bus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0213753A FR2846764B1 (fr) | 2002-11-04 | 2002-11-04 | Perfectionnement aux systemes electroniques comprenant un bus systeme |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2846764A1 FR2846764A1 (fr) | 2004-05-07 |
FR2846764B1 true FR2846764B1 (fr) | 2005-01-14 |
Family
ID=32104407
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0213753A Expired - Fee Related FR2846764B1 (fr) | 2002-11-04 | 2002-11-04 | Perfectionnement aux systemes electroniques comprenant un bus systeme |
Country Status (2)
Country | Link |
---|---|
US (1) | US20040193836A1 (fr) |
FR (1) | FR2846764B1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2418036B (en) * | 2004-09-08 | 2007-10-31 | Advanced Risc Mach Ltd | Communication transaction control between independent domains of an integrated circuit |
US7353311B2 (en) * | 2005-06-01 | 2008-04-01 | Freescale Semiconductor, Inc. | Method of accessing information and system therefor |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5960215A (en) * | 1996-09-12 | 1999-09-28 | Digital Equipment Corporation | Transmit data FIFO for flow controlled data |
US5815677A (en) * | 1996-12-31 | 1998-09-29 | Compaq Computer Corporation | Buffer reservation method for a bus bridge system |
US5978868A (en) * | 1997-08-28 | 1999-11-02 | Cypress Semiconductor Corp. | System for generating buffer status flags by comparing read and write pointers and determining direction of progression of read pointer with respect to write pointer |
US6252600B1 (en) * | 1998-10-02 | 2001-06-26 | International Business Machines Corporation | Computer graphics system with dual FIFO interface |
US6732223B1 (en) * | 2000-04-03 | 2004-05-04 | Micron Technology, Inc. | Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system |
US6671747B1 (en) * | 2000-08-03 | 2003-12-30 | Apple Computer, Inc. | System, apparatus, method, and computer program for execution-order preserving uncached write combine operation |
US6907479B2 (en) * | 2001-07-18 | 2005-06-14 | Integrated Device Technology, Inc. | Integrated circuit FIFO memory devices that are divisible into independent FIFO queues, and systems and methods for controlling same |
-
2002
- 2002-11-04 FR FR0213753A patent/FR2846764B1/fr not_active Expired - Fee Related
-
2003
- 2003-11-04 US US10/701,384 patent/US20040193836A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
FR2846764A1 (fr) | 2004-05-07 |
US20040193836A1 (en) | 2004-09-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20070731 |