JPH10242815A - Pulse generating circuit and power circuit for sense amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize a sense amplifier source voltage at the time of activation by a common circuit for a different external source voltage by combining delay circuits which have different correlations between a delay time and the external source voltage and generating a pulse which has a shorter width following the external source voltage becoming higher, and applying the external source voltage to a power source terminal for a sense amplifier by using the pulse. SOLUTION: A Vcc delay circuit 10 is constituted by cascading the substrate of a p channel transistor 101 and a Vcc delay element 100 whose source is biased to the external source voltage Vcc, and has such dependency that the delay time becomes shorter as the external source voltage Vcc rises. A VINT delay circuit 11 is composed of a p channel transistor 111 which has its substrate connected to the external source voltage Vcc and its source connected to an internal voltage VINT and has such reverse dependency that the delay time becomes longer as the external source voltage Vcc is higher. A pulse D is generated by a logical operation circuit consisting of inverters 12 and 14 and a NAND gate 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generating circuit used in a semiconductor device, and more particularly to a power supply circuit for a sense amplifier incorporated in a DRAM, and more particularly to a pulse generating a pulse having a pulse width depending on an external power supply voltage. The present invention relates to a generation circuit and a stabilized internal power supply circuit for a sense amplifier using the pulse generation circuit.

[0002]

2. Description of the Related Art With the advance of the miniaturization technology of semiconductor devices, the withstand voltage of circuits in the semiconductor devices has been reduced.
Such a semiconductor device has a built-in internal power supply circuit,
3.3 V external power supply voltage Vcc to an appropriate internal voltage V
_The voltage is reduced to _INT (for example, 2.5 V) and supplied to a circuit in the semiconductor device. In particular, a dynamic RAM (hereinafter, referred to as a DRAM) among the semiconductor devices described above includes a sense amplifier that amplifies storage information stored in a memory cell and a sense amplifier for refreshing the storage information at predetermined time intervals. A sense amplifier power supply circuit for supplying power is provided separately from the internal power supply circuit. This power supply circuit for the sense amplifier converts the external power supply voltage Vcc to the internal voltage _VINT.
And supplies it to the sense amplifier.

FIG. 6 is a diagram illustrating a sense amplifier and a power supply circuit for a sense amplifier of a DRAM as described above. Here, the sense amplifier power supply circuit 61 is connected to an external power supply voltage Vcc.
Is divided by an output transistor 612 and an output resistor 613 to output VOUT. The output voltage VOUT is compared with the reference voltage VREF in the comparator 611, and the output of the comparator 611 is input to the gate of the output transistor 612 so that the output voltage VOUT becomes equal to the predetermined internal voltage VREF.
It is controlled to be _INT . On the other hand, the sense amplifier 62 includes switching transistors 63 and 64 and flip-flops (F / F) 651 to 65n. Here, when a sense amplifier activation signal φSE is input to the switching transistors 63 and 64 from a sense amplifier driver not shown in FIG.
VOUT is supplied to n from the sense amplifier power supply circuit 61, and the information stored in each memory cell of the corresponding memory cell matrix 661 to 66n is refreshed.

However, power supply to the sense amplifier 62 becomes a heavy load on the power supply circuit 61 for the sense amplifier. As a result, every time the sense amplifier activation signal φSE is input, the output voltage VOU of the sense amplifier power supply circuit 61 is
T may decrease. FIG. 7 shows the fluctuation of the output voltage VOUT during such a refresh. FIG. 7 shows the time on the horizontal axis and the output voltage V of the power supply circuit 61 for the sense amplifier on the vertical axis.
OUT is taken. Assuming that the sense amplifier activating signal φSE is input to the sense amplifier 62 at time t0 for refreshing, the output voltage VOUT of the internal voltage 61 for the sense amplifier is represented by a solid line a in FIG. Thus, the voltage temporarily drops below the predetermined internal voltage _VINT . Such a decrease in the voltage VOUT is caused by D
It is not preferable to guarantee the normal operation of the RAM.

As a conventional technique, for example, Japanese Patent Application Laid-Open No. Hei 8-1
In order to solve such a problem, the power supply circuit disclosed in Japanese Patent No. 53388 supplies an external power supply voltage Vcc to an output terminal for a predetermined time by using a pulse generation circuit when the output voltage VOUT decreases. Is to suppress the fluctuation of FIG. 8 shows such a power supply circuit. The power supply circuit 81 for a sense amplifier includes a power supply circuit 811, an external power supply terminal (Vcc) and a p-channel transistor 81 having a source and a drain connected to the output terminal of the power supply circuit 811 respectively.
2. a pulse generating circuit 814 for inputting a pulse to the gate of the p-channel transistor 812 via an inverter 813, and an input signal generating circuit 815 for inputting an input signal to the pulse generating circuit 814 with the sense amplifier activation signal φSE as an input. Have. Note that the power supply circuit 811
Has the same configuration as that of the sense amplifier power supply circuit 61 shown in FIG. 6 and outputs the internal potential _VINT .
The configuration of the sense amplifier 82 is the same as that of the sense amplifier 62 shown in FIG.

The operation of the power supply circuit for a sense amplifier as described above is as follows. 8, the sense amplifier activation signal φSE is also input to the input signal generation circuit 815 together with the sense amplifier 82. Input signal generation circuit 815
Inputs an input signal to the pulse generation circuit 814 and outputs a pulse having a predetermined pulse width. The pulse is input to the gate of the p-channel transistor 812 via the inverter 813. p-channel transistor 812
Is set to O by the pulse output from the pulse generation circuit 814.
N acts as a switching element. An output voltage (VOUT) terminal of the sense amplifier power supply circuit 81 is connected to a p-channel transistor 81 acting as a switching element.
4, the output voltage (VOUT) of the sense amplifier power supply circuit 81 is supplied to the output voltage (VOUT) terminal of the sense amplifier power supply circuit 81 and the pulse output from the pulse generation circuit 814 after the input of the sense amplifier activation signal φSE. External power supply voltage Vcc is forcibly supplied for a time corresponding to the pulse width of.

At this time, by appropriately selecting the pulse width with respect to the external power supply voltage Vcc, a decrease in the output voltage VOUT when supplying power to the sense amplifier is suppressed as small as shown by a broken line b in FIG. Can be. However, if the pulse width is too long or if the external power supply voltage Vcc is high, overshoot occurs as shown by the one-dot chain line c in FIG. 7 to achieve the purpose of supplying a predetermined _VINT to the sense amplifier. Can not be done. On the other hand, when the pulse width is too short or when the external power supply voltage Vcc is low, the output voltage VOUT cannot be sufficiently precharged by the external power supply voltage Vcc. Therefore, the broken line b in FIG.
In order to keep the output voltage VOUT from decreasing as much as possible when supplying power to the sense amplifier as shown in the above, a pulse having an appropriate width corresponding to the external power supply voltage Vcc is synchronized with the sense amplifier activation signal φSE. Then, the signal is input to the gate of the p-channel transistor 812 via the inverter 813, and the p-channel transistor 812 is turned on to supply the external power supply voltage Vcc to the output terminal for an appropriate time to appropriately precharge the output voltage VOUT. This is very important.

[0008]

However, a general-purpose DRA
M is required to operate normally within a range of 5 ± 0.5V for 5V and 3.3 ± 0.3V for 3.3V. The precharge function of the amplifier power supply circuit must also be able to cope with fluctuations in the external power supply voltage Vcc. Therefore, external power supply voltage Vcc
It is important to appropriately control the time for supplying the external power supply voltage Vcc, in other words, the pulse width of the pulse generation circuit 814 according to the external power supply voltage Vcc in order to suppress the fluctuation of the output voltage VOUT by supplying the power supply voltage VOUT. Become. That is, more specifically, it is necessary to obtain a short pulse when the external power supply voltage Vcc is high, and to obtain a pulse having a long pulse width when the external power supply voltage Vcc is low.

However, the conventional pulse generation circuit has
As shown in FIG. 9, the input pulse A is input to the delay circuit 91, and the input pulse A and the delay
The pulse is generated by taking the logic with the output of the pulse. Here, the delay circuit 91 is a circuit in which a plurality of delay elements (hereinafter, referred to as Vcc delay elements) each composed of a CMOS inverter having a source and a substrate of a p-channel transistor connected to an external power supply voltage Vcc are connected in cascade. . The delay time of the Vcc delay element is Vcc
Because of the dependence, the delay circuit 91 of the pulse generation circuit shown in FIG. 9 is constituted by a plurality of Vcc delay elements connected in cascade (such a delay circuit is referred to as a Vcc delay circuit). The pulse width also has a Vcc dependency. However, the Vcc dependence of the pulse width in such a pulse generation circuit is not sufficiently large for controlling the above-described precharge function. On the other hand, the delay circuit 91 is composed of a C-channel transistor whose substrate is connected to the external power supply voltage Vcc and whose source is connected to the internal voltage _VINT lower than Vcc.
A delay element (hereinafter referred to as V
_In this case, the delay time of the _VINT delay element has an inverse dependence on Vcc. Therefore, a delay circuit ( _VINT delay circuit) configured by connecting a plurality of _VINT delay elements in _cascade is used. The pulse generating circuit serving as the delay circuit 91 cannot be used for controlling the precharge function of the sense amplifier described above.

As described above, in the conventional pulse generating circuit, it is not possible to generate a pulse having a width dependent on the external power supply voltage Vcc that can control the precharge of the sense amplifier in accordance with the external power supply voltage Vcc. Therefore, even though the power supply circuit for a sense amplifier as shown in FIG. 8 can appropriately suppress the fluctuation of VOUT under a specific external power supply voltage Vcc, it can be said that it does not always operate properly at another Vcc. Therefore, the versatility of the DRAM could not be provided.

In view of the above, an object of the present invention is to provide a pulse generating circuit whose pulse width largely depends on the external power supply voltage Vcc in order to solve the above-mentioned problem. The present invention is
Further, the time for supplying the external power supply voltage Vcc to the output terminal of the internal power supply circuit is appropriately set using a pulse generation circuit that generates a pulse having a width dependent on the external power supply voltage Vcc,
It is an object of the present invention to provide a versatile sense amplifier power supply circuit that can compensate for a decrease in output voltage of an internal power supply circuit even under a different external power supply voltage Vcc.

[0012]

In order to achieve the above object, a pulse generating circuit according to the present invention utilizes the fact that a Vcc delay element and a _VINT delay element have different external power supply voltage Vcc dependencies. Delay circuit and V _INT
A pulse having a larger pulse width and a higher Vcc dependency is obtained by using a delay circuit. That is, a pulse generating circuit according to the present invention comprises a Vcc delay circuit comprising a plurality of cascade-connected Vcc delay elements whose sources and substrates of a p-channel transistor of a CMOS inverter are connected to an external power supply voltage Vcc; A V _INT delay circuit having a plurality of V _INT delay elements whose sources are connected to the internal voltage V _INT and whose substrate is connected to the external power supply voltage V cc, and An arithmetic unit for generating a pulse by performing a logical operation on the output and the output of the _VINT delay circuit is provided.

Here, the delay time of the Vcc delay element has a dependency on the external power supply voltage Vcc, whereas the delay time of the _VINT delay element has an inverse dependency. A Vcc delay circuit constituted by connecting a plurality of these delay elements in cascade and a Vcc
_{Since the INT} delay circuit has dependence and inverse dependence on Vcc, a difference between the delay time of these two delay circuits and the external power supply voltage Vcc can be correlated. Then, if a step or a pulse input signal having a predetermined pulse width is input to these two delay circuits and a logical operation of the output signals is performed, a pulse width corresponding to the difference between the delay times of the two delay circuits is obtained. A pulse having a pulse width depending on the external power supply voltage Vcc can be generated. Here, as a power supply circuit that supplies the internal voltage V _INT to the source of the p-channel transistor of the V _INT delay element, for example, an internal power supply circuit that is built in a semiconductor device and reduces the external power supply voltage Vcc to the internal voltage V _INT is used. be able to.

The pulse generation circuit according to the present invention takes the logic of the output of the Vcc delay circuit and the output of the _VINT delay circuit. The circuit is characterized in that a plurality of Vcc delay elements are connected in cascade so that the delay time is longer than the delay time of the _VINT delay circuit. The pulse width of the pulse obtained by such a pulse generation circuit is obtained by subtracting the delay time of the V _INT delay circuit having the inverse Vcc dependency from the delay time of the Vcc delay circuit having the Vcc dependency. Therefore, the pulse width has a Vcc dependency that becomes shorter as Vcc becomes higher.

Furthermore the pulse generator circuit of claim 3, especially the Vcc delay circuit includes an even number of Vcc delay elements which are cascaded, the V _INT delay circuit,
It consists of an even number of V _INT delay elements connected in cascade,
The arithmetic means comprises an inverter for inverting the output of the Vcc delay circuit, and a logic gate for outputting a pulse by taking the logical product of the output of the inverter and the output of the _VINT delay circuit. It is. Here, the Vcc delay circuit and the _VINT delay circuit delay and output the input signal by a predetermined delay time. A pulse is generated by calculating the logical product of the output of the _VINT delay circuit and the inverted output of the Vcc delay circuit among the two delayed input signals.

Further, the present invention is a power supply circuit for a sense amplifier, characterized by using the above-described pulse generating circuit having Vcc dependency. Specifically, the sense amplifier power supply circuit according to the present invention, as described in claim 4, an output transistor having a source connected to an external power supply voltage and a drain grounded through an output resistor, Comparing means for comparing the output voltage divided by the output resistance with the reference power supply voltage and inputting a signal corresponding to the difference to the gate of the output transistor, and outputting the internal power supply voltage obtained by reducing the external power supply voltage to the sense amplifier. A sense amplifier power supply circuit for supplying a sense amplifier activation signal for activating the sense amplifier and outputting a first pulse having a predetermined pulse width; and an external power supply receiving the first pulse as an input. A pulse generation circuit for generating a second pulse having a pulse width depending on a voltage, and an input of a second pulse output from the pulse generation circuit And turned on, it is the time the external power supply voltage corresponding to the pulse width of the second pulse that a switch means for supplying to an output terminal of the power supply circuit.

Here, the means for generating the first pulse generates the input signal of the pulse generating circuit based on the sense amplifier activating signal. Therefore, the means for generating the first pulse is a means for generating a predetermined input signal based on the sense amplifier activation signal, such as a pulse generating circuit for outputting a pulse signal having a predetermined width by using a certain signal as a trigger. Means. However, at this time, the pulse width of the first pulse needs to be longer than the second pulse width output from the pulse generation circuit. When the sense amplifier activation signal is input periodically, it is necessary that the period be shorter than the period. By receiving such a first pulse as an input, the pulse generation circuit generates a second pulse having a pulse width dependent on the external power supply voltage Vcc in synchronization with the sense amplifier activation signal. Based on the second pulse thus obtained, the switch outputs the external power supply voltage Vcc to the output terminal. This switch means connects, for example, a source and a drain to an external power supply terminal (Vcc) and an output terminal of a power supply circuit, and inputs the second pulse to a gate via an inverter, and serves as a switching element. It includes a transistor and the like. With such a configuration, when the sense amplifier is activated, the output terminal of the power supply circuit for the sense amplifier is output based on the output of the pulse generation circuit, that is, the second pulse having a predetermined pulse width dependent on Vcc. External power supply voltage Vcc
Is supplied. Thus, a voltage drop during the operation of the sense amplifier (during refresh) can be suppressed. Moreover, since the pulse width of the second pulse depends on the external power supply voltage Vcc, the same effect can be obtained for a different external power supply voltage Vcc.

The switching means of the power supply circuit for a sense amplifier according to the present invention using the above-mentioned pulse generating circuit includes all means for outputting the external power supply voltage Vcc to the output terminal based on the second pulse. 6. The pulse generation circuit according to claim 5, wherein the output transistor comprises a p-channel transistor, and the switch means connects a source to a gate of the output transistor of the power supply circuit, a drain to ground, and the pulse generation circuit. Is input to the gate of the n-channel transistor. In such a configuration, the n-channel transistor turns on every time the second pulse is input from the pulse generation circuit. When the n-channel transistor is turned on, the gate of the output transistor of the power supply circuit is grounded, so that the output transistor constituted by the p-channel transistor is turned on, and the external power supply voltage Vcc is supplied to the output terminal of the power supply circuit. At this time, the pulse input from the pulse generating circuit to the gate of the n-channel transistor is synchronized with the sense amplifier activation signal, and the pulse width depends on the external power supply voltage Vcc. Therefore, the output of the power supply circuit for a sense amplifier according to the present invention is supplied for a time period in which the external power supply voltage Vcc depends on the voltage in synchronization with the sense amplifier activation signal. Therefore, by configuring the pulse generating circuit so that the pulse width of the second pulse is appropriate, a power supply circuit for a sense amplifier that supplies a stable voltage even when the load increases due to activation of the sense amplifier Can be configured.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating an embodiment of a pulse generation circuit according to the present invention. Here, FIG. 1A shows that the external power supply voltage Vcc is changed to the internal voltage _VINT.
1 shows a pulse generation circuit used in a semiconductor device that operates with a reduced voltage. This pulse generation circuit
Delay circuit 10, V _INT delay circuit 11, Vcc delay circuit 10
12 and NAND gate 1 for inverting the output of
3. An inverter 14 for inverting the output of the NAND gate 13. Here, inverters 12 and 14
And the NAND gate 13 constitute a logical operation means.

FIGS. 1B and 1C show the configurations of the Vcc delay circuit 10 and the _VINT delay circuit 11, respectively. V
Both the cc delay circuit 10 and the V _INT delay circuit 11 are configured by cascade-connecting a plurality of CMOS inverters. Here, as shown in FIG. 1B, the CMOS inverter forming the Vcc delay circuit is a p-channel transistor 10.
One substrate is biased to the same external power supply voltage Vcc as its source. Such a CMOS inverter will be called a Vcc delay element. On the other hand, in the V _INT delay circuit 11, as shown in FIG. 1C, the source of the p-channel transistor 111 constituting the CMOS inverter is connected to the internal voltage V _INT and the substrate thereof is connected to the external power supply voltage Vcc. It is configured by cascade-connecting V _INT delay elements. The internal voltage V _INT is supplied from an internal power supply circuit not shown in FIG.

Of the two types of delay elements, the Vcc delay element has a Vcc dependency that the delay time is shortened as the external power supply voltage Vcc increases. On the other hand, V
_{The INT} delay element has an inverse dependency that the delay time increases as the external power supply voltage Vcc increases.
As described above, when different voltages are applied to the source of the p-channel transistor and the substrate, the delay time of the _VINT delay element increases with an increase in the external power supply voltage Vcc. This is because the absolute value of the voltage increases and the current driving capability decreases. This phenomenon is called the back gate effect, and its quantitative description is given in, for example, Japanese Patent Application Laid-Open No. 6-169240.

By utilizing the difference in characteristics of the two types of delay elements with respect to the external power supply voltage Vcc as described above, the number of delay elements connected in cascade when configuring the delay elements can be appropriately selected. Vcc delay circuit 10 and V _INT
The difference in delay time of the delay circuit 11 can be made dependent on the external power supply voltage Vcc. 2, the delay of each delay circuit when a Vcc delay circuit 10 to Vcc delay element constituted by 6 Dantate genus connected to the V _INT delay circuit 11 constituted by 2 Dantate genus connecting V _INT delay element Time and external power supply voltage Vcc
FIG. According to FIG. 2, while the delay time of the Vcc delay circuit 10 decreases as the external power supply voltage Vcc increases, the delay time of the _VINT delay circuit 11 having the internal voltage _VINT of 2.5 V increases. ing. Therefore, it can be seen that the difference between the delay times of these two delay circuits decreases as the external power supply voltage Vcc increases.

In the pulse generation circuit shown in FIG. 1A, a Vcc delay circuit 10 and a _VINT delay circuit 11 output output signals B and C obtained by delaying an input signal A by respective delay times. Output signal B of Vcc delay circuit 10 is inverted by inverter 12. The inverted signal B and the output signal C of the _VINT delay circuit 11 are input to the NAND gate 13. The output of the NAND gate 13 is inverted by the inverter 14, in other words, the AND of the inverted B and C is the pulse output from the pulse generation circuit.

Each signal in the above-described pulse generation circuit is shown in a timing chart of FIG. FIG. 3A shows a case where the external power supply voltage Vcc is high (for example, VccMAX = 3.6 V in a DRAM operating at Vcc = 3.3 ± 0.3 V), and FIG.
Is low (for example, VccMIN = 3.0 V). The delay time of the Vcc delay circuit 10 decreases when the external power supply voltage Vcc is high, and increases when the external power supply voltage Vcc is low. In FIG. 3, the delay time appears as a difference in the falling time of the inverted B. On the other hand, the rising time of the signal C obtained by delaying the input signal A by the V _INT delay circuit 11 is
When Vcc is high (FIG. 3A), when Vcc is low (FIG.
(B)) Although it is slower, the difference is slight because the number of stages of the V _INT delay elements constituting the V _INT delay circuit 11 is small. As a result, the pulse width of the output pulse D obtained as the logical product of the inverted B and the signal C is short when the external power supply voltage Vcc is high and long when the external power supply voltage Vcc is low.
By appropriately selecting the number of delay elements connected in cascade in this manner, a pulse having a pulse width depending on the external power supply voltage Vcc can be obtained.

FIG. 4 shows, as a second embodiment of the present invention, a configuration in which a pulse generating circuit according to the present invention is provided in a semiconductor device. Vcc delay circuit 10, V
_{The INT} delay circuit 11 is the same as that described in FIG. The arithmetic circuit 15 for generating a pulse from the outputs of the two delay circuits is also composed of the two inverters 12 and 14 and the NAND gate 13 as described in the first embodiment. Power circuit 16 is incorporated in the semiconductor device steps down the external supply voltage Vcc to the internal voltage V _INT, which not only V _INT delay circuit 11, and supplied to the memory circuit, not shown here ing.

Next, as a third embodiment, a power supply circuit for a sense amplifier according to the present invention will be described with reference to FIG. The power supply circuit for the sense amplifier that supplies the internal voltage V _INT to the sense amplifier 55 includes a power supply circuit 51 including a comparator 511, a p-channel transistor 512, and an output resistor 513, an n-channel transistor 52, a pulse generation circuit 53, And an input signal generation circuit 54. Here, the comparator 511 inputs a signal corresponding to the difference between the output voltage VOUT and the reference voltage VREF to the gate of the p-channel transistor 512 acting as an output transistor. Thus, the p-channel transistor 512 divides the external power supply voltage Vcc together with the output resistance 513, and controls so that VOUT becomes a predetermined internal voltage ( _VINT ).

The source of the n-channel transistor 52 is connected to the gate of the p-channel transistor 512, and the drain is grounded. The pulse D generated by the pulse generation circuit 53 is input to the gate of the n-channel transistor 52. Therefore, the n-channel transistor 52 is turned on when the pulse D is input, and functions as a switching element that grounds the gate of the p-channel transistor 512, that is, the output transistor of the power supply circuit 51. Thus, the gate of the p-channel transistor 512 is
2, the p-channel transistor 512 is rendered conductive. As a result, the external power supply voltage Vcc is supplied to the output terminal of the power supply circuit 51. That is, the external power supply voltage Vcc is output as VOUT for a time corresponding to the pulse width generated by the pulse generation circuit 53.

The sense amplifier 55 is activated by a sense amplifier activation signal φSE. At this time, the sense amplifier 5
5 is a heavy load on the power supply circuit for the sense amplifier. However, at this time, since the input signal A synchronized with the sense amplifier activation signal φSE is input to the pulse generation circuit 53 by the input signal generation circuit 54, the gate of the n-channel transistor 52 depends on the external power supply voltage Vcc. A one-shot pulse having a pulse width is input in synchronization with the sense amplifier activation signal φSE. Therefore, when the sense amplifier 55 is activated and the load increases, by supplying the external power supply voltage Vcc via the p-channel transistor 512, the output voltage VOUT of the power supply circuit for the sense amplifier can be stabilized. The sense amplifier 55 shown in FIG. 5 has the same configuration as the sense amplifier 62 shown in FIG.

As a result, the output voltage VOUT obtained by using a pulse having an appropriate pulse width decreases as the load increases when the sense amplifier is activated as shown by the broken line (b) in FIG. Is suppressed. At this time, the pulse generation circuit 53 inputs a pulse having a pulse width dependent on the external power supply voltage Vcc to the gate of the n-channel transistor 52 in synchronization with the sense amplifier activation signal φSE. Therefore, even when the external power supply voltage Vcc fluctuates, it is possible to control the supply time in accordance with the external power supply voltage Vcc at that time, and the output voltage VOU
The fluctuation of T can be suppressed. As a result, a versatile sense amplifier power supply circuit that can be used for different external power supply voltages Vcc can be obtained.

[0030]

According to the pulse generating circuit of the present invention, a delay circuit having a delay time having a different correlation with respect to an external voltage Vcc is constituted by using a Vcc delay element and a _VINT delay element. A pulse having a pulse width dependent on the voltage Vcc can be generated.

In particular, according to the pulse generating circuit of the present invention, a plurality of Vcc delay elements are connected in cascade so that the delay time of the Vcc delay circuit is longer than the delay time of the _VINT delay circuit. The external power supply voltage V
As cc increases, a pulse having a short pulse width can be obtained.

According to the power supply circuit for a sense amplifier according to the fourth or fifth aspect, a pulse having a Vcc-dependent pulse width is generated in synchronization with the sense amplifier activation signal. Since the switch is turned on based on the pulse, the external power supply voltage Vcc can be supplied to the output terminal of the power supply circuit for the sense amplifier for a time corresponding to the external power supply voltage Vcc. This makes it possible to stabilize the output voltage when the sense amplifier is activated by a common circuit with respect to different external power supply voltages Vcc, and incorporates the power supply circuit for the sense amplifier and, consequently, the power supply circuit for the sense amplifier. The versatility can be given to the DRAM.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a pulse generation circuit according to the present invention and a configuration of a delay circuit used in the pulse generation circuit.

FIG. 2 shows an external power supply voltage Vcc, a Vcc delay circuit, and V
FIG. 4 is a diagram illustrating a relationship between delay times of an _INT delay circuit.

FIG. 3 is a timing chart illustrating an operation of the pulse generation circuit.

FIG. 4 is a diagram showing another embodiment of the pulse generation circuit according to the present invention.

FIG. 5 is a diagram showing an embodiment of a power supply circuit according to the present invention using the pulse generation circuit.

FIG. 6 shows a DRA including a conventional sense amplifier power supply circuit.
FIG. 3 is a diagram illustrating an example of the configuration of M.

FIG. 7 is a diagram showing a change in an output voltage of a power supply circuit for a sense amplifier in the DRAM.

FIG. 8 shows a DR using a power supply circuit for a conventional sense amplifier.
It is a figure showing other examples of composition of AM.

FIG. 9 is a diagram showing a configuration of a conventional pulse generation circuit.

[Explanation of symbols]

10 Vcc delay circuit, 100 Vcc delay element, 10
1 ... p-channel transistor, 11 ... V _INT delay circuit, 110 ... V _INT delay element, 111 ... p-channel transistor, 12, 14 ... inverter, 13 ... NA
ND gate, 15 arithmetic circuit, 16 internal power supply circuit, 5
DESCRIPTION OF SYMBOLS 1 ... Power supply circuit, 511 ... Comparator, 512 ... P-channel transistor, 513 ... Output transistor, 52 ... N-channel transistor, 53 ... Pulse generation circuit, 54 ...
Input signal generation circuit, 55 ... sense amplifier.

Claims (5)

[Claims] 1. A Vcc comprising a plurality of Vcc delay elements whose source and substrate of a p-channel transistor of a CMOS inverter are connected in cascade to an external power supply voltage.
A delay circuit, a V _INT delay circuit source of p-channel transistors of the CMOS inverters whose substrate is connected to the internal voltage is constituted by the V _INT delay element connected to the external power supply voltage plural cascaded, the Vcc A pulse generation circuit comprising: an operation unit that generates a pulse by performing a logical operation on an output of the delay circuit and an output of the _VINT delay circuit. 2. The pulse generating circuit according to claim 1, wherein said Vcc delay circuit includes a plurality of Vcc delay elements connected in cascade such that a delay time thereof is longer than a delay time of said _VINT delay circuit. A pulse generation circuit characterized by being configured by: 3. The pulse generating circuit according to claim 1, wherein said Vcc delay circuit comprises an even number of said Vcc delay elements connected in cascade, and said _VINT delay circuit comprises: consists genus connected even number of the V _INT delay elements, said calculating means takes an inverter for inverting the output of the Vcc delay circuit, a logical product of the output of the output of the inverter V _INT delay circuit A pulse generation circuit comprising a logic gate for outputting a pulse. 4. An output transistor having a source connected to an external power supply voltage and a drain grounded via an output resistor, and an output voltage divided by the output transistor and the output resistor being compared with a reference voltage and responding to a difference therebetween. And a comparison means for inputting the output signal to the gate of the output transistor, and supplying a sense amplifier with an internal voltage obtained by stepping down an external power supply voltage. 3. A means for outputting a first pulse having a predetermined pulse width as an input, and generating a second pulse having a pulse width dependent on an external power supply voltage by receiving the first pulse as an input. 3. The pulse generation circuit according to any one of claims 3 to 3, wherein the second pulse output from the pulse generation circuit is turned on as an input, and the second pulse Switch means for supplying an external power supply voltage to an output terminal of the power supply circuit for a time corresponding to a pulse width of the power supply circuit. 5. The power supply circuit for a sense amplifier according to claim 4, wherein the output transistor uses a p-channel transistor, and the switch unit connects a source to a gate of the output transistor and grounds a drain. A power supply circuit for a sense amplifier, comprising an n-channel transistor whose gate receives the output of the pulse generation circuit.