JP2003272390A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which increment of instantaneous current consumption at the time of read-out of pages. <P>SOLUTION: A semiconductor memory device is provided with a plurality of sense amplifiers (3) divided into each group being a unit of red-out of pages, a sense amplifier control signal generating circuit (4) which generates a sense amplifier control signal (SAENi) enabling the sense amplifiers for each group and disabling the sense amplifiers for each group, and which output it, in which the sense amplifier control signal enables a sense amplifier of one part of a group out of groups of the plurality of sense amplifiers with timing being different from sense amplifiers of the other group, and disables with different timing, and a plurality of memory cells (1) connected to the plurality of sense amplifiers through data lines (2). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high-speed page reading used in a semiconductor memory device, and more particularly to a semiconductor memory device performing divided reading.

[0002]

2. Description of the Related Art In a conventional semiconductor memory device such as a flash memory, a page in which several words of data are collectively read and latched by a sense amplifier and data at a desired address is output at high speed only by controlling output side Readout has been used. That is, for example, a plurality of data are collectively latched during the first access, which is the first access. Then, the latched data is output at high speed by switching the output side. Thus, in the conventional semiconductor memory device, data for several words, for example, 8 words (1 word 161
/ O) data was read simultaneously by 8 × 16 = 128 sense amplifiers.

Since the page is read, the current consumed by the cell decoding does not increase much even if the number of data increases. In other words, the current increases extra to open multiple bit lines, but the word line and predecode do not increase, so
Does not significantly affect the overall current consumption. On the other hand, the current consumed by the sense amplifier increases in proportion to the number of data. That is, one bit line is connected to one sense amplifier. As a result, when the loads of all the sense amplifiers charge the data lines at once, the current consumption instantaneously increases, causing voltage drop and power supply noise. FIG. 8 shows a schematic configuration of a conventional semiconductor memory device.
The plurality of memory cells 30 provided are grouped in a plurality of units. A plurality of data lines 31 are connected to the memory cell 30, respectively. The data line 31 is grouped and connected to a plurality of grouped sense amplifiers 32. For example, 16 sense amplifiers 32 are provided in each group.
The number of 16 is 16 I / s as one word.
It corresponds to O minutes. In the configuration shown in FIG. 8, eight sense amplifiers 32, that is, 128 sense amplifiers 32, which is the product of 16 and 8, are provided. The sense amplifier 32 is provided in a peripheral circuit area different from the memory cell area of the semiconductor memory device. Here, the sense amplifier to be divided is 1
It can be set in appropriate units such as words or 2 words. Here, it is set every 8 words.

A sense amplifier enable signal having the same timing is input to each sense amplifier 32. The sense amplifier enable signal is output from the single sense amplifier enable signal generation circuit 33.

Next, the operation of the conventional semiconductor memory device shown in FIG. 8 will be described with reference to FIG. 9 showing the timing of signals input to and output from each component in FIG. An address signal designating a memory cell to be accessed is input, and then the sense amplifier enable signals input to each sense amplifier 32 simultaneously rise from L level to H level, and all sense amplifiers 32 are activated. With the activation of the sense amplifier 32, the initial current is consumed in each sense amplifier 32. When the sense amplifier 32 is activated, the memory cell 30 connected to this sense amplifier 32 is accessed. In this way, the sense amplifier is activated, and the data read from the memory cell is
It is output from an I / O (not shown).

As shown in the bottom column of FIG. 9, the consumption current increases suddenly immediately after all the sense amplifiers are activated, and then becomes a steady state. Return to. That is, the maximum instantaneous current consumption is the sum of the initial current consumptions of the activated sense amplifiers, and the activation start time of each sense amplifier is the same, so the instantaneous current consumption becomes extremely large.

In addition, the amount of data to be read (the number of words) will increase in the future for higher speed access. In this page read, since the read operation is performed by the number of sense amplifiers corresponding to the amount of data (the number of words) to be read collectively, the current consumption increases as the amount of data increases.

[0008]

The conventional semiconductor memory device as described above has the following problems.

When the power supply capability of the system using the semiconductor memory device is weak, a power supply voltage drop occurs at this moment, and power noise occurs due to abrupt current consumption. There is a risk of malfunction and other malfunctions of devices installed in the system. Further, in the flash memory, if the power supply to the system drops, writing and erasing operations may stop. Particularly in portable electronic devices and the like, since the battery is used, the power supply capacity for the semiconductor memory device incorporated in the portable electronic devices tends to decrease, so this increase in instantaneous current consumption has a great influence. Exert. Also, as the data length increases from 16 to 32, for example, as the data reading speed increases, the current consumption increases.

In the prior art, in the case of 8 words, if the instantaneous current consumption is several hundred mA and the wiring resistance is 1 ohm, the voltage drop around the circuit is 10.
It becomes several V, and the characteristics are deteriorated.

An object of the present invention is to solve the above problems of the prior art.

A particular object of the present invention is to provide a semiconductor memory device that suppresses the current consumption when reading a page.

[0013]

In order to solve the above problems, a semiconductor memory device according to the present invention has a plurality of sense amplifiers divided into groups which are units for page reading, and a sense amplifier for each group. A sense amplifier control signal generation circuit for enabling an amplifier and disabling a sense amplifier for each group, generating and outputting a sense amplifier control signal, wherein the sense amplifier control signal is the plurality of A sense amplifier control signal generation circuit for enabling sense amplifiers of some of the sense amplifier groups at different timings and disabling them at different timings of the sense amplifiers of other groups; A plurality of memory cells connected to the sense amplifier through the data line. To.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) The structure of a semiconductor memory device according to the present embodiment will be described with reference to the structure block diagram shown in FIG. A plurality of memory cells 1 provided
Are grouped in a plurality of units. A plurality of data lines 2 are connected to the memory cell 1, respectively. The data lines 2 are grouped and connected to a plurality of grouped sense amplifiers 3. For example, 16 sense amplifiers 3 are provided in each group. The number of 16 is 1 as one word.
This corresponds to 6 I / Os. In the configuration shown in FIG. 1, the sense amplifiers 3 are arranged in 8 groups, that is, 16 groups.
128 products, which is the product of 8 and Sense amplifier 3
Are provided in a peripheral circuit area different from the memory cell area of the semiconductor memory device. Here, the sense amplifier to be divided can be set in an appropriate unit such as 1 word or 2 words. Here, it is set every 8 words.

A sense amplifier enable (sense amplifier activation) signal is input to each sense amplifier 3 for each sense amplifier group. Sense amplifier enable signals of the same timing are input to the respective sense amplifiers 3 in the same group. Further, sense amplifier enable signals of different timings are input to the sense amplifiers of different groups. In the example of FIG. 1, eight sense amplifier enable signals SAEN (1) to SAEN (8) are used.
However, each of the groups (1) to (3) of the sense amplifier 3
Input to (8).

The plurality of types of sense amplifier enable signals are output from different sense amplifier enable signal generation circuits 4. That is, the plurality of sense amplifier enable signal generation circuits 4 output the sense amplifier enable signals SAEN (1) to SAEN (8) so as to have different timing waveforms for each signal group output to the sense amplifiers 3 to which they are connected. To do. Sense amplifier enable signals SAEN (1) to SAEN (8)
Causes the sense amplifier to be a unit group and start reading every word.

Next, the operation of the semiconductor memory device shown in FIG. 1 will be described with reference to FIG. 2 which shows timings of signals input to and output from each component in FIG. After the address signal ADDRESS designating the memory cell to be accessed is input and the desired memory cell is selected, the sense amplifier enable signal SAEN (1) rises from the L level to the H level, and the sense amplifier 3 of the group (1) is turned on. Activated. With the activation of the sense amplifier 3 of the group (1), in the sense amplifier 3 of the group (1),
Initial current is consumed. When the sense amplifier 3 of the group (1) is activated, the data of the memory cell (1) connected to the sense amplifier 3 of the group (1) is read.

Next, the sense amplifier enable signal SAE
N (2) rises from the L level to the H level, and the sense amplifier 3 of the group (2) is activated. With the activation of the sense amplifier 3 of the group (2), current is consumed in the sense amplifier 3 of the group (2).
When the sense amplifier 3 of the group (2) is activated, the data of the memory cell (2) connected to the sense amplifier 3 of the group (2) is read. In this way, the sense amplifier enable signals sequentially rise from the L level to the H level, and the sense amplifiers are sequentially activated. In this way, while the sense amplifiers are being activated in sequence,
The data read from the memory cell is output from the I / O (not shown).

As shown in the bottom column of FIG. 2, the consumption current maintains an average value after the address is input, and returns to the initial value after the activation of all the sense amplifiers is completed. In this way, the sense amplifier enable signal for controlling the read operation is provided for each word of the sense amplifier,
Instantaneous current consumption can be smoothed by providing timing for each signal while keeping a constant period until the data line is charged, the data is read, and the data is latched. That is, the instantaneous current consumption is
This is the sum of the consumption currents of the activated sense amplifiers, and the instantaneous consumption currents are smoothed because the activation start times of the sense amplifiers are different. In this way, in the read operation, the address is first detected during the decoding period, and then the charging is started. After that, the memory cells are sequentially accessed, the amplification operation is performed, and the output is performed from the sense amplifier. After that, the latch operation is performed.

Sense amplifier enable signal SAENi
The operation timing (i is a number that identifies the group of sense amplifiers specified by the input address signal) is generated by the internal clock. The sense amplifier enable signal SAENi has a peak of about several nanoseconds,
At the time of first access, it is shifted by, for example, about 5 nanoseconds. Then, all the sense amplifier enable signals SAENi are activated within the period L before the data of the first accessed memory cell (first access data) is output, and all the data are latched. The timing at which the peak of the sense amplifier enable signal SAENi deviates is changed depending on the number of sense amplifiers to be divided. That is, when the number of divisions is large, the shift timing becomes small, and when the number of divisions is small, the shift timing becomes large.

The read operation has three operation timings of data line charging, sensing and latching, and these three timings are made independent to be executed by the sense amplifier control circuit. That is, the sense amplifier control circuit executes an operation in which the sense amplifier load charges the data line, determines the data, and holds the data for the optimized time.

Next, a circuit diagram of a portion of the sense amplifier 3 and the memory cell 1 shown in FIG. 1 is shown in FIG. 3A. In the sense amplifier 3, the data line connection switch 6 is connected to the memory cell transistor 5 in the memory cell 1 via the data line 2. In addition, the reference memory cell transistor 7
A reference data line connection switch 9 is connected to the reference data line 8 via the reference data line 8. This data line connection switch 6
Is connected to the first load 1 via the bias transistor B1.
0 is connected, and the second load 11 is connected to the reference data line connection switch 9 via the bias transistor B2. The cell drain voltage BIAS is applied as a bias voltage to the gate terminals of the bias transistors B1 and B2. A current mirror unit 12 is connected between the bias transistor B1 and the bias transistor B2. The same sense amplifier enable signal SAEN is input to the current mirror unit 12, the first load 10 and the second load 11. Further, the current mirror unit 12 includes a data determination unit 24.
And the data latch unit 13 are connected to each other. The data in the semiconductor memory device is output from the data latch unit 13 via the I / O unit. Here, the data latch unit 13
Is composed of, for example, two inverters.

The first load 10 is a circuit that supplies a current to the data line 2, and is a P-type MOS transistor 50, 52.
And an inverter 54. Therefore, the high level sense amplifier enable signal SAEN
Is input to the inverter 54, a current is supplied from the voltage VDD to the data line 2. On the other hand, the second load 11 is a circuit that supplies a current to the reference data line 8 and is a P-type MO.
It is configured to include S transistors 60 and 62 and an inverter 64. Therefore, when the high level sense amplifier enable signal SAEN is input to the inverter 64, a current is supplied from the voltage VDD to the reference data line 8.

The current mirror section 12 is a circuit for reading the data of the memory cell transistor 5 by comparing the voltages of the node N1 and the node N2. That is, the memory cell transistor 5 has 0 data or 1
Data is stored and therefore set to a threshold of 0 data or a threshold of 1 data. The reference memory cell transistor 7 is set to a threshold value intermediate between 0 data and 1 data.

The current mirror section 12 includes an inverter 70.
And P-type MOS transistors 72, 74 and 76, and N
Type MOS flow charts 78 and 80. Therefore, when the high-level sense amplifier enable signal SAEN is input to the inverter 70, the current mirror unit 12 is driven and the voltage of the node N3 is input to the data determination unit 24. The voltage of this node N3 is
The data determined by the data determination unit 24 and the data determined by the data latch unit 13 are held.

FIG. 3B is a diagram showing an example of the circuit configuration of the sense amplifier enable signal generation circuit 4 according to this embodiment, and FIG. 3C is a delay circuit 90 used in this sense amplifier enable signal generation circuit 4. , 92, 94
3D is a diagram showing an example of the circuit configuration of FIG. 3D, and FIG. 3D is a diagram showing operation waveforms at various points in the sense amplifier enable signal generation circuit 4.

As shown in FIGS. 3B and 3D, the sense amplifier enable signal generation circuit 4 according to the present embodiment has three
Two delay circuits 90, 92, 94 and a NOR circuit 96
And an inverter 98. The trigger pulse signal TRIGGERi is input to the delay circuit 90 at an arbitrary timing. That is, as shown in FIG. 2, each sense amplifier enable signal generation circuit 4
Trigger pulse signal TRI at different timings
GGERi is input.

The delay circuits 90, 92 and 94 are circuits for delaying the input pulse and adjusting the pulse width thereof. Therefore, the delay circuit 90 outputs the data line charging pulse signal PREi with a delay of a predetermined time from the input of the trigger pulse signal TRIGGERi. Specifically, the trigger pulse signal TRIGGER
When i becomes low level, the data line charging pulse signal PREi becomes high level, and after a predetermined time delay,
Become low level. This data line charging pulse signal PRE
While i is at the high level, the data line 2 is charged.

The data line charging pulse signal PREi is
It is input to the delay circuit 92. The delay circuit 92 outputs the sense pulse signal SENi with a delay of a predetermined time from the input of the data line charging pulse signal PREi. Specifically, when the data line charging pulse signal PREi becomes low level, the sense pulse signal SENi becomes high level and becomes low level after a predetermined time delay. While the sense pulse signal SENi is at the high level, the data is read from the memory cell via the data line 2 and the data determination unit 24 determines the data.

The sense pulse signal SENi is input to the delay circuit 94. The data latch pulse signal LATCHi is output from the delay circuit 94 after a predetermined time from the input of the sense pulse signal SENi. Specifically, when the sense pulse signal SENi goes low, the data latch pulse signal LATCH
i becomes high level, and after a predetermined time delay, i becomes low level. This data latch pulse signal LATCHi
, The data latch unit 13 performs the data latch operation while the signal is at the high level.

These data line charging pulse signals PREi
The sense pulse signal SENi and the data latch pulse signal LATCHi are input to the NOR circuit 96.
Therefore, the high level sense amplifier enable signal SA is passed through the NOR circuit 96 and the inverter 98 for a period in which the high level periods of these three signals are combined.
ENi is output. This charges the data line 2 connected to the memory cell 3, determines the data of the memory cell read through the data line 2, and determines the sense amplifier enable signal for the time required to latch the data. SAENi can be enabled.

As shown in FIG. 3C, the delay circuit 90
(The delay circuits 92 and 94 have the same configuration)
OR circuits 100 and 102 and an even number of inverters 104
And is configured. Then, the delay circuit 90
Then, as the input signal IN, the trigger pulse signal TRIG
GERi is input, and the data line charging pulse signal PREi is output as the output signal OUT. The pulse width is adjusted by the number of inverters 104.

As described above, the sense amplifier enable signals SAENi, which are independent of each other, hold the time optimized for the load in the sense amplifier to charge the data line, judge the data, and latch the data. By using the semiconductor memory device having the function of enabling the timings independently of each other, current consumption is reduced. In this way, the temporary maximum current consumption is prevented from flowing at the moment when the sense amplifier is activated, and the current consumption is averaged during the activation period of the sense amplifier.
The maximum current consumption can be reduced.

In the prior art, in the case of 8 words, the voltage drop around the sense amplifier circuit is −0. Although it becomes several V and the characteristics are deteriorated, in the semiconductor memory device of the present embodiment,
A voltage drop occurs only for one word, and the voltage drop is one-tenth of the division number of the prior art, for example, one-eighth-0.0 several V.

In this embodiment, when a plurality of sense amplifiers start a read operation and charge a data line, a read operation start timing / read operation period is provided for each unit word to smooth the instantaneous current consumption. It is possible to provide a semiconductor memory device that reduces voltage drop and power supply noise that occur when the maximum current consumption is large.

In this embodiment, the semiconductor memory device for changing the operation related to the divided read is provided, and the other operations are not changed from the conventional semiconductor memory device.

The present embodiment relates to page reading for collectively reading several words of data. By providing the reading timing for each word, the peak current consumption at the time of page reading is suppressed to reduce voltage drop and power supply noise. It is possible to provide a semiconductor memory device that enables reduction in read performance and prevents read performance deterioration and read malfunction.

(Second Embodiment) In the present embodiment,
The semiconductor memory device of the first embodiment shown in FIG. 1 is provided with a trigger signal generation circuit TGG as shown in FIG. 4, and the other configuration is the same as that of the first embodiment. Further, FIG. 5 shows the trigger signal generation circuit TGG of FIG.
FIG. 6 is a diagram showing operation waveforms generated at various points in FIG.

Here, the trigger signal generation circuit TGG is
Address decode circuit 15 to which address signal ADDRESS is input, internal clock signal generation circuit 17 to which clock enable signal CLKEN output from this address decode circuit 15 is input, and page selection signal output from address decode circuit 15 Increment circuit 1 to which PAGEi and the internal clock signal CLK1 output from the internal clock signal generation circuit 17 are input
6 and 6.

The address decoding circuit 15 decodes the address signal ADDRESS to generate the page selection signal PAGEi so that the sense amplifier enable signal SAENi corresponding to the input address signal ADDRESS is activated first. Is a number that identifies the group of sense amplifiers specified by the input address signal). In this way, the address decoding circuit 1
By having 5, the first access is made as fast as possible. In order not to delay the fast access, the sense amplifier to be enabled first is decoded. The example of FIG. 5 shows the case where the fifth page PAGE5 is selected, and the page selection signal PAGE5 is at the high level.

Further, the address decoding circuit 15 uses the internal clock signal CL from the internal clock signal generating circuit 17.
It outputs a clock enable signal CLKEN that enables the output of K1. Internal clock signal generation circuit 17
Increments the internal clock signal CLK1 based on the clock enable signal CLKEN.
Output to 6.

The increment circuit 16 first sets the sense amplifier enable signal to be enabled to the enable state, and then sequentially sets the remaining sense amplifier enable signals to the enable state. Therefore, in the example of FIG. 5, the increment circuit 16 first outputs the pulse of the trigger pulse signal TRIGGER5 of the group 5 of the sense amplifiers to be enabled first, and then sequentially outputs the groups 3, 4, 6, 7, 8 ,. 1, 2 trigger pulse signal T
RIGGER3, TRIGGER4, TRIGGER
6, TRIGGER7, TRIGGER8, TRIGG
Outputs ER1 and TRIGGER2 pulses.

FIG. 6 is a diagram showing an example of the circuit configuration of the address decoding circuit 15 according to the present embodiment. This Figure 6
As shown in, the address decoding circuit 15 according to the present embodiment includes eight NAND circuits 200, eight inverters 202, a NOR circuit 204, and an inverter 206.

That is, in this embodiment, since the sense amplifier 3 is divided into 8 pages (8 groups), the address signal ADDRESS is 3 bits.
Therefore, eight sets of decoders each including the NAND circuit 200 and the inverter 202 are provided. From these inverters 202, the page selection signal PAGE1
~ PAGE8 is output. That is, any one of the page selection signals PAGEi becomes high level. The page selection signals PAGE1 to PAGE8 are the NOR circuit 2
It is input to 04. Therefore, the page selection signal PAG
When any one of E1 to PAGE8 becomes high level, the output of the inverter 206 also becomes high level and the high level clock enable signal CLKEN is output.

7A and 7B are diagrams showing an example of the circuit configuration of the increment circuit 16 according to the present embodiment. As shown in FIG. 7A, the increment circuit 16 according to the present embodiment includes inverters 210, 212, 214.
And binary counters 216, 218, 220, 22
2, an inverter 224, a NAND circuit 230, an inverter 232, an inverter 240, a NAND circuit 242, and an inverter 244. Further, as shown in FIG. 7B, the increment circuit 16 includes NOR circuits 250 and 252 and an inverter 25.
4, 256, a resistor 258, a P-type MOS transistor 260, and an N-type MOS transistor 262, 264.
And an inverter 270, and eight sets of these are provided. That is, one set of the circuit of FIG. 7B is provided for one page.

As shown in FIG. 7A, the internal clock signal CLK1 output from the internal clock signal generation circuit 17 is output.
Is input to the binary counter 216 and
The internal clock signal CL is inverted by the inverter 210.
It is input to the binary counter 220 as K2.
That is, the internal clock signal CLK1 and the internal clock signal CLK2 are clock signals that are shifted from each other by a half cycle, as shown in FIG.

Binary counters 216, 218, 22
Reference numerals 0 and 222 are circuits that count up by one in two cycles. Therefore, the internal clock signal CUT2, which is the output of the binary counter 216, is
The clock cycle is twice that of K1, and the internal clock signal CUT4, which is the output of the binary counter 218, has twice the clock cycle of the internal clock signal CUT2. Similarly, the internal clock signal CUT1 that is the output of the binary counter 220 has a clock cycle that is twice that of the internal clock signal CLK2, and the internal clock signal CUT3 that is the output of the binary counter 222 has twice the clock cycle of the internal clock signal CUT1. It becomes a cycle.

The internal clock signals CUT2 and CUT4 are
It is input to the NAND circuit 230. This NAND circuit 2
30 is a low-level clock cover signal CLK1C
OVER is inverted and input by the inverter 224. Therefore, the sense amplifier 3 of pages 1, 3, 5, and 7
Page selection signal CPA for sequentially enabling the
GEi is output from the inverter 232.

Similarly, the internal clock signals CUT1 and CU
T3 is input to the NAND circuit 242. This NAN
The D circuit 242 has a low level clock cover signal C.
LK2COVER is inverted by the inverter 240 and input. Therefore, the page selection signal CPAGEi for enabling the sense amplifiers 3 of pages 2, 4, 6, and 8 in order is output from the inverter 244.

The page selection signal PAGEi and the page selection signal CPAGEi are provided in N corresponding pages.
It is input to the OR circuit 250. For example, the page selection signal PAGE1 and the page selection signal CPAGE1 are
Input to the NOR circuit 250.

When the page selection signal PAGEi or the page selection signal CPAGEi goes high, the NOR circuit 2
The output of 50 goes low, and the inverter 270 outputs one pulse of the trigger pulse signal TRIGGERi. For example, as shown in FIG. 5, page selection signal PAG
When E5 becomes high level, trigger pulse signal TRI
One pulse of GGER5 is output. And after this,
In order, the trigger pulse signal TRIGGER3, TRI
GGER4, TRIGGER6, TRIGGER7, T
RIGGER8, TRIGGER1, TRIGGER2
From this, one pulse is output. In the example of FIG. 7B, the inverters 254, 256, 270, the resistor 258, and the MO
The S transistors 260, 262 and 264 form a pulse generation circuit.

Before the read operation, all eight NO
The reset signal RST is input to the R circuit 252, and the increment circuit 16 is reset.

According to the present embodiment, it is possible to obtain the same effect as that of the first embodiment. Further, since it is unknown which address is designated as the first address, the first address is designated. The read address can be read, and then the address can be sequentially read by incrementing it. The above-mentioned respective embodiments can be implemented in combination.

(Third Embodiment) In the third embodiment, the shift time ΔtSA of the sense amplifier enable signal SAENi in the page read mode and the burst read mode in each of the above-described embodiments.
Consider EN.

FIG. 10 shows the address signal ADDRE in the page read mode in each of the above-described embodiments.
SS, trigger pulse signal TRIGGERi, data latch pulse signal LATCHi, and data read signal DA
FIG. 12 is a diagram showing operation waveforms with TA, and FIG. 11 is a diagram showing operation waveforms of these signals in the burst read mode. The page read mode and the burst read mode are selected by external setting.

As shown in FIG. 10, in the page read mode, the shift time ΔtSAEN of the sense amplifier enable signal SAENi is the time t from the completion of the latch of the first page to the actual output as t.
It is set to a value obtained by dividing P by the number of pages n. That is, the shift time ΔtS of the sense amplifier enable signal SAENi
AEN = tP / n.

This is because it is not decided which page will be accessed next after the data of the first access is output, and therefore, when the first access is output, it is necessary to read the data of another page. Because there is.

On the other hand, in the burst read mode, as shown in FIG. 11, the shift time ΔtSAEN of the sense amplifier enable signal SAENi is actually output as an output after the first access page is latched. It takes only tB to reach the end. That is, the shift time ΔtSAE of the sense amplifier enable signal SAENi
N = tB.

This is because after the first access data is output, which page is to be accessed next is determined. Therefore, when the first access data is output, the next page data should be read. Because it is good.

Here, the different values of the time tP and the time tB are the output speed in the page read mode and
The output speed in the burst read mode is not always the same, and normally, the time t in the burst read mode is
This is because B is shorter.

Then, time tB / n <time tP / n
And the shift time ΔtSA in the burst read mode
EN becomes short. In order to avoid this, for example, the internal clock frequency may be made variable, and the shift time ΔtSAEN may be set to the time tB in the burst read mode. As a result, it is possible to further suppress noise and voltage drop in the burst read mode.

The present invention is not limited to the above embodiment, but can be variously modified. For example, in each of the above-described embodiments, the sense amplifier enable signal SAENi is enabled at different timing for each group, and the sense amplifier enable signal SAENi is disabled at different timing for each group.
For some groups, the sense amplifier enable signal SAENi may be enabled and disabled at the same time. In other words, the sense amplifier enable signal SAENi may be enabled and disabled at different timings for some of the plurality of groups.

[0063]

According to the present invention, it is possible to provide a semiconductor memory device that prevents an instantaneous increase in current consumption during page reading.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor memory device according to a first embodiment.

FIG. 2 is a timing chart showing a page read operation of the semiconductor memory device according to the first embodiment.

FIG. 3A is a circuit diagram illustrating a sense amplifier and a memory cell of the semiconductor memory device according to the first embodiment.

FIG. 3B is a diagram showing an example of a circuit configuration of a sense amplifier enable signal generation circuit in the first embodiment.

3C is a diagram showing an example of a circuit configuration of a delay circuit in the sense amplifier enable signal generation circuit of FIG. 3B.

FIG. 3D is a diagram showing operation waveforms at various points in the sense amplifier enable signal generation circuit of FIG. 3B.

FIG. 4 is a block diagram showing an example of a configuration of a sense amplifier enable signal generation circuit and a trigger signal generation circuit of the semiconductor memory device of the second embodiment.

FIG. 5 is a timing chart showing a page read operation of the semiconductor memory device according to the second embodiment.

FIG. 6 is a diagram showing an example of a circuit configuration of an address decoding circuit in the trigger signal generating circuit according to the second embodiment.

FIG. 7A is a diagram showing an example of a circuit configuration of an increment circuit in the trigger signal generation circuit according to the second embodiment.

FIG. 7B is a diagram showing an example of a circuit configuration of an increment circuit in the trigger signal generation circuit according to the second embodiment.

FIG. 8 is a schematic configuration diagram of a conventional semiconductor memory device.

FIG. 9 is a timing chart showing a page read operation of a conventional semiconductor memory device.

FIG. 10 is a diagram showing operation waveforms in a page read mode of the semiconductor memory device according to the third embodiment.

FIG. 11 is a diagram showing operation waveforms in the burst read mode of the semiconductor memory device according to the third embodiment.

[Explanation of symbols]

1 memory cell 2 data lines 3 sense amplifier 4 Sense amplifier enable signal generation circuit 5 memory cell transistors 6 Data line connection switch 7 Reference memory cell transistor 8 standard data lines 9 Standard data line connection switch 10 First load 11 Second load 12 Current mirror section 13 Data latch section 15 Address decode circuit 16 increment circuit 20 First inverter 21a First PMOS transistor 21b First NMOS transistor 22 Second inverter 23a Second PMOS transistor 23b Second PMOS transistor 24 Data judgment section

Claims (10)

[Claims] 1. A plurality of sense amplifiers, which are divided for each group that is a unit for page reading, a sense amplifier that is enabled for each group, and a sense amplifier that is disabled for each group. A sense amplifier control signal generation circuit for generating and outputting an amplifier control signal, wherein the sense amplifier control signal is configured to output sense amplifiers of a part of the plurality of sense amplifier groups to those of other groups. Enable at a different timing than the sense amplifier, and
A semiconductor memory device comprising: a sense amplifier control signal generation circuit that is disabled at different timings; and a plurality of memory cells that are connected to the plurality of sense amplifiers via data lines. 2. The sense amplifier control signal generation circuit enables the sense amplifiers at different timings and disables them at different timings for each group of the plurality of sense amplifiers. The semiconductor memory device according to claim 1, wherein the semiconductor memory device outputs. 3. The sense amplifier control signal generation circuit first enables a group of sense amplifiers corresponding to an input address signal, and subsequently sequentially enables another group of sense amplifiers. The semiconductor memory device according to claim 2, which is characterized in that. 4. A data line connected to a memory cell is charged during the time from when the sense amplifier is enabled to when it is disabled based on the sense amplifier control signal, and the data is read through this data line. 3. The semiconductor memory device according to claim 2, wherein the time is set to the time required to judge the data in the memory cell and latch the data. 5. The semiconductor according to claim 4, wherein the sense amplifier control signal generation circuit includes a sense amplifier enable signal generation circuit that outputs the sense amplifier control signal for each group. Storage device. 6. Each of the sense amplifier enable signal generation circuits generates a data line charge signal which is a signal for charging a data line based on an input trigger signal.
A generation circuit; a second generation circuit which, based on the data line charge signal, reads data from a memory cell through a data line and generates a sense signal which is a signal for determining the data; A third generation circuit for generating a data latch signal for latching the determined data based on the above, and a time obtained by combining the times when the data line charge signal, the sense signal and the data latch signal are output. Only
The semiconductor memory device according to claim 5, further comprising: a fourth generation circuit that enables the sense amplifier control signal. 7. A first group selection signal for decoding the input address signal and first setting a sense amplifier of a group corresponding to the decoded address signal to an enable state. And outputs the trigger signal to the sense amplifier enable signal generation circuit of the group corresponding to the decoded address signal based on the first group selection signal, and sequentially outputs the trigger signal. 7. The semiconductor memory device according to claim 6, further comprising: an increment circuit that outputs the trigger signal to the sense amplifier enable signal generation circuit of another group. 8. The semiconductor device according to claim 7, wherein the increment circuit sequentially outputs the trigger signal by performing an increment operation in synchronization with the internally generated first clock signal. Storage device. 9. The increment circuit includes a first clock signal and a second clock signal that is half a cycle off from the first clock signal.
9. The semiconductor memory device according to claim 8, wherein the trigger signal is sequentially output in a half cycle of the first clock signal by performing an increment operation in synchronization with a clock signal. 10. The semiconductor memory device according to claim 9, wherein a clock frequency of the first clock signal is changed according to a read mode set by an input from the outside.