JPH04212782A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a voltage control circuit which decreases a fluctuation in internal voltage arising from a fluctuation in load current and the current consumption at the time of standing by. CONSTITUTION:The on chip voltage control circuit which generates the chip internal voltage (VINT) by dropping an external supply voltage (VEXT) by a series control transistor (Q1) is constituted so as to have the control means (100, 100A) which changes the internal resistance of the series control TR according to the state of a prescribed clock (*CLK) and generates the chip internal voltage nearly the same in the low current consumption state in the standby state of the chip and the large current consumption state in the active state of the chip.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an on-chip voltage control circuit for creating an internal power supply voltage on a chip that is lower than an external supply voltage to a semiconductor integrated circuit.

As LSIs become smaller, the transistors used inside them are also becoming smaller. For this reason, the withstand voltage is also lower than that of conventional ones, so it is necessary to lower the power supply voltage. Also, in terms of performance, the gate length is shorter (0.5 microns) at a lower voltage (eg, 3.3 V) than a circuit made with a 0.8 micron transistor, which has no problem with voltage resistance at a high voltage (eg, 5 V). Compared to the latter case, the circuit operation is faster in the latter case. For this reason, as miniaturization progresses, the power supply voltage should be lowered to an optimal value, but if the voltage supplied to the chip varies, it is inconvenient when using many types of ICs at the same time, so it is standardized to a value such as 5V. There is. For this reason, it is necessary to provide a circuit within the chip that generates an optimal voltage value.

0003

2. Description of the Related Art FIG. 10(a) is a typical example of a circuit (on-chip voltage regulator) conventionally used for this purpose. Transistor Q1 acts as a series control regulator for an external supply voltage VEXT, for example 5V, and creates an internal voltage VINT, for example 3.3V. The gate of transistor Q1 is connected to the ring oscillator O
Transistor Q3 with diode-connected AC signal of SC
The battery is charged with a rectified voltage. This gate voltage VG1
is clamped to a constant potential by transistor Q4. This is because transistor Q4 is connected to the reference voltage VREF created within the chip. Reference voltage V
There are several known methods for generating REF, such as creating it from the threshold value of a MOS transistor. Transistor Q2
is for charging the gate of transistor Q1 when the power is turned on. The reference voltage VREF is also applied to the gate of this transistor Q2 and the oscillator OSC,
The latter stabilizes the oscillation voltage. C is a capacitor, which has the effect of increasing the charging voltage. For example, when the output voltage of the oscillator OSC is negative, the capacitor C passes through the Q2
When the side is charged positively and the output voltage of the oscillator OSC becomes positive, the sum of this positive voltage and the capacitor voltage becomes the charging voltage of VG1 and increases it. Since the gate voltage VG1 is comparable to the externally supplied voltage VEXT, a high voltage is required to create VG1. Increasing the voltage is also achieved by oscillating and rectifying (to obtain a peak voltage).

The problem with this circuit is that, as shown in FIG. 10(b), the drain current ID is ID = k (VG - Vth
)2, and Q1 of the regulator transistor
Since the turn-on characteristic of is proportional to the square of the gate-source voltage VGS, when the current consumption within the chip fluctuates by ΔI, the internal voltage also fluctuates by ΔV. Taking a DRAM as an example, the current of about 0.1 mA in a standby state increases to more than 100 mA at the peak of activation, a change of 1000 times. Variations can be reduced by increasing the gate width of the transistor and making the value of k sufficiently large, but it is difficult to create a transistor with an extremely large gate width due to chip area constraints. In other words, in the circuit of Fig. 10(a), when the current consumption within the chip is not constant, the internal voltage VI
The drawback was that it was difficult to suppress fluctuations in NT. Furthermore, if the dimensions of transistor Q1 are made too large, the subthreshold current becomes noticeable and the threshold value at minute currents drops dramatically, which can cause VINT to fluctuate when current consumption changes by a factor of 1000. Become.

A circuit designed to suppress fluctuations in the internal voltage VINT has also been developed, one example of which is shown in FIG. In FIG. 11, the gate voltage of regulator transistor Q1 is controlled by the output of a current mirror type analog differential amplifier circuit composed of transistors Q11 to Q14.
Negative feedback is applied from the drain of transistor Q1, that is, the terminal that outputs VINT, to the gate of transistor Q12 of the differential amplifier circuit. Therefore, the internal voltage VIN
Since T is automatically controlled to match the reference voltage VREF applied to the other input terminal of the differential amplifier circuit, the internal voltage VINT changes with changes in the load current, that is, the drain current of transistor Q1. It becomes difficult to do.

Therefore, although the voltage stability is good, in order for the analog differential amplifier circuit to obtain the necessary amplification factor, it is necessary to flow a bias current of 100 μA or more through the transistors Q11 and Q12, resulting in unnecessary consumption during standby. The drawback is that it draws a lot of current. Another drawback is that consideration must be given to the stability of the negative feedback circuit, and if it is made easily, the output voltage VIN
T may cause ringing, or in the worst case, the feedback system may become unstable and oscillate.

[0007]

As described above, the conventional method has problems such as fluctuations in the output (internal) voltage due to fluctuations in the load current and large current consumption during standby.

SUMMARY OF THE INVENTION It is an object of the present invention to improve the above-mentioned problems and provide a voltage control circuit with less internal voltage fluctuations due to load current fluctuations and less standby current consumption, and a semiconductor memory device using the same. be.

[0009]

Means for Solving the Problems As shown in FIG. 1(a), in the present invention, a control means 100 is provided for a series control transistor Q1. The control means 100 receives a predetermined clock *CLK (* indicates a low active signal) and changes the resistance of the transistor Q1 according to the state of this clock (active period or its frequency (activation/inactivation frequency)). The internal voltage VINT is changed so that the internal voltage VINT does not change between when the chip is in a standby state with low current consumption and when the chip is in an active state with high current consumption.

0010

[Operation] If the internal resistance of the series control transistor Q1 is changed between large current and small current so that the voltage drop is the same between large current and small current, internal voltage VINT is equal to external supply voltage VEXT - Q1 above. Since the voltage drop is V
If EXT = 1, VINT will also be constant.

Both the low current value in the standby state and the large current value in the active state may be set to known, approximately constant values, and therefore the internal voltage drop of Q1 is maintained so that the voltage drop remains unchanged between the standby state and the active state. It is possible to adjust and connect the resistance.

The load L usually includes a capacitor or parasitic capacitance as a circuit element, and therefore the internal voltage VI
Fluctuations in NT cause these capacitances to charge and discharge, and the fluctuations occur relatively slowly. In addition, activation and standby of the chip may be repeated over a short period of time. Therefore, the control means 100 is also provided with a time constant so that the change in the internal resistance of the series control transistor Q1 due to its output is commensurate with the above-mentioned charging/discharging and, ultimately, the degree of internal voltage fluctuation, so that VINT remains constant without excess or deficiency. Allow adjustments to be made.

The control means 100 does not include an amplifier to perform negative feedback control, but merely applies different gate voltages to the transistor Q1 during standby and activation, so current consumption is minimal. .

[0014]

EXAMPLE The present invention will be explained in more detail with reference to FIG. 1(a). Series control transistor (series control regulator) Q1
is an nMOS transistor, and the gate voltage is generated by the control means CM. Node N1 is its output terminal. As shown in the figure, the control means 100 includes a constant current source I, diode-connected MOS transistors Q26 to Q29, a transistor Q30 whose gate receives an external input activation clock *CLK, and a capacitor C.
9 is connected in series between the power supply VA and ground, and Q30
is connected in parallel with Q29, and C is connected between node N1 and ground. The voltage at node N1 (which is equal to gate voltage VG1) is V1 +V2, and assuming that the threshold voltages of transistors Q26 to Q29 are all the same Vth, V1 = 3Vth, V2 = Vth. clock*
When transistor Q30 is turned on by CLK, V2
= 0, and therefore the potential of the node N1 is 4Vth if Q30 is off, and 3Vth if Q30 is on.

When the chip is on standby, *CLK (eg DR
In AM, *CAS clock) is at a high level, so transistor Q30 is conductive, and the gate voltage of transistor Q1 is equal to the threshold voltage of three transistors Q26 to Q28. Of course, instead of using the threshold value of the MOS transistor, this portion may use another voltage, such as the forward voltage of a diode. The bias current for transistors Q26 to Q28 is supplied from an appropriate current source circuit I, and the voltage V1 remains constant even if the external voltage VA changes.
occurs from Q26 to Q28. Due to circuit characteristics, the power supply VA of the current source is set to a value VA higher than the standard value of the external supply voltage VEXT when the transistor Q1 is an enhancement type MOS (not necessarily VEXT).
It does not need to be higher, but it does need to be higher than the standard VEXT value. ) The source voltage of transistor Q1 is slightly lower than the voltage VG1 of node N1 and the threshold voltage Vth of Q1. That is, VINT=VG1-VGS. Note that VGS is the bias voltage between the gate and source of Q1 corresponding to the current consumed by the load during standby.
is approximately equal to the threshold voltage Vth of .

Next, as shown in FIG. 1(b), the clock *C
When LK falls and the chip is activated, circuits within the chip operate, increasing current consumption. *When CLK becomes low level, transistor Q30 is turned off, so the gate voltage VG1 of transistor Q1 tends to become higher by the threshold value V2 of transistor Q29. At this time, since a capacitor C is added to the gate of Q1, it is a relatively large capacitance component in addition to the gate capacitance of Q1 itself, so the increase in gate voltage VG1 is due to the charging of the capacitance component by the current source I. It is done and it does not happen instantly. When the clock *CLK is toggled several times, it follows the illustrated path and rises to V1 +V2 at time t3. Therefore, the internal voltage VINT decreases slightly from the moment the chip is activated until time t2. However, in a case other than the present invention (that is, without Q30), VINT continues to fall and VINT fluctuates greatly, but in the present invention, VINT recovers and rises as it is compensated by the voltage at node N1. In the case of the present invention, the solid line curve C1 is Q30, and the dotted line curve C2 is Q30.
This is the internal voltage VINT when there is no VINT.

While the clock *CLK toggles, the node N1 is close to V1 +V2 (if *CLK goes low for a long time, N1 becomes V1 +V2) and the voltage Q1
to compensate for the drop in VINT. In other words, the internal resistance of Q1 is controlled to be low.

Next, when the clock *CLK enters the standby state again, N1 has a value higher than necessary for the required voltage, so the internal voltage NINT rises transiently from time t4 to t5. . However, at some point t5
After that, it converges to the original state.

As described above, in the present invention, the transistor Q3
0 controls the internal resistance of the series control transistor Q1 according to the toggle frequency of the chip activation clock or the activation period of the clock, so the internal voltage VINT
fluctuations can be kept small. However, since no differential amplifier circuit is used, there is no extra current consumption, and since feedback control is not performed, problems such as oscillation do not occur.

FIG. 2(a) shows an embodiment of the present invention. The constant current source I of the on-chip voltage control circuit 100A is constituted by a depletion type nMOS transistor Q25 whose gate and source are short-circuited. The series control transistor Q1 is also composed of a depletion type nMOS transistor. Since Q1 causes a large current to flow in the pentode region, a so-called substrate current is generated. Therefore, as shown in Figure 2(b),
When making a transistor on a p-type silicon substrate 1, p
When the type substrate 1 is biased to VBB and the integrated circuit (IC) is designed so that the substrate bias VBB is generated within the chip, the substrate current of Q1 flows into the VBB generation circuit, causing the VBB generation circuit to malfunction. There is a problem with stability. For this purpose, as shown in the figure, an n-well 2 is formed in a p-type substrate, a p-well 3 is further formed within the n-well 2, and the p-well 3 is connected to the source electrode of Q1. As a result, the substrate current generated by Q1 overlaps with the output current of Q1, so no problem occurs.

Transistor Q25 has a similar structure, but
The reason for forming the p-well 3 in the n-well 2 is another reason. That is, the transistor Q25 configures a constant current source by connecting its gate to its source. Since the constant current output of Q25 is taken out from the source side, if Q25 is formed directly on the p-type substrate 1, the change in source potential will be caused by the back gate voltage (that is, the source of Q25 and the Q25
(difference from the substrate potential, which is the back gate of
Constant current characteristics deteriorate due to the substrate bias effect (the larger the back gate bias, the higher the threshold of Q25 and the lower the drain current). Therefore, the back gate of Q25 is not in the substrate 1, but in the p-well 3 in the n-well 2.
By connecting the p-well 3 to the source of Q25, when the source voltage changes, the back gate also changes in the same way, thereby preventing modulation of the drain current due to the substrate bias effect. This provides good constant current characteristics.

By making the transistor Q1 a depletion type, the external voltage VE is reduced as shown in FIG. 1(a).
There is no need to apply a voltage VA higher than XT. V
Although it is necessary to generate a voltage VA higher than EXT within the chip, this VA generation circuit also involves some power consumption, so the circuit shown in FIG. 2(a) which does not require this is more suitable.

FIG. 3 shows another embodiment corresponding to FIG. 2(b). In order to match the back gate voltage and source voltage of the transistor in order to prevent the substrate bias effect of the transistor, in this example, the transistor is formed in the p-well 5 using the n-type substrate 4, and the p-well 5 is connected to the source. There is.

In FIG. 1, etc., one of the transistors Q29 is short-circuited and released by the transistor Q30, but this can be done by short-circuiting and releasing the short-circuiting of multiple transistors (n) as shown in FIG. It's fine. The number of transistors Q26 to Q29 may also be increased or decreased (m) as necessary. Also, M.O.
Other resistance elements, such as diodes, may be used instead of the S transistor.

Next, a semiconductor device using the on-chip voltage control circuit of the present invention will be described with reference to FIG. FIG. 5 shows a DRAM, which includes a RAS system 200, a CAS system 300, a sense system 400, and an internal voltage generation circuit 500. R
The AS system 200 operates according to the *RAS signal or a clock synchronized thereto. The CAS system 300 operates according to the *CAS signal or a clock synchronized thereto. Sense type 30
0 operates according to sense amplifier drive clocks φS and *φS. Internal voltage generation circuit 500 includes three internal voltage generators 37, 38, and 39.

The RAS system 200 includes a predecoder 12b, a row address decoder 16, a clock generator 18, a mode controller 32, and a refresh address counter 34. CAS system 300 is address buffer 1
2a, a column address decoder 14, a clock generator 22, a write clock generator 26, and a data input buffer 28. A sense system 400 includes a memory cell array 10 and a sense amplifier/input/output (I/O) gate 2
It has 4. The memory cell array 10 has a plurality of memory cells arranged in row and column directions and connected to bit lines and word lines.

The multiplexed address signal ADD consisting of address bits A0 to A10 is sent to the address buffer 12.
Enter a. Address buffer 12a outputs a column address signal that is supplied to column address decoder 14. Address signal ADD is also applied to predecoder 12b. Predecoder 12b outputs a row address signal to row address decoder 16. A row address strobe signal *RAS output from an external device such as a CPU is input to the clock generator 18. Clock generator 18 outputs a clock signal to row address decoder 16. The row address strobe signal *RAS is a low active signal that defines the selection/non-selection timing of at least one word line. Sense amplifier/input/output gate 24
is a column address decoder 14 and a memory cell array 10.
It is connected to the.

Column address strobe signal *CAS from an external device is input to AND gate 20 via an inverter. The clock signal generated by the clock generator 18 is applied to an AND gate 20, and its output is input to a clock generator 22. *In response to the CAS signal, the clock generator 22 generates a clock signal provided to the column address decoder and the address buffer 12.
Generate a. Upon receiving the clock from clock generator 22, column address decoder 14 selects the corresponding one or more bit line pairs. Sense amplifier/input/output gate 24 is connected to bit lines in memory cell array 10. When writing input data Din,
Alternatively, when reading data Dout, the data is amplified by a sense amplifier.

The write clock generator 26 receives the clock signal from the clock generator 22 and the write enable signal *WE from the external device, and generates a write signal. The data input buffer 28 receives data Din at a timing defined by the write clock from the write clock generator 26. Data output from data input buffer 28 is input to sense amplifier/input/output gate 24 and written into memory cell array 10. Data from the sense amplifier/input/output gate 24 is output to a data output buffer 30, which outputs this data in synchronization with the clock signal from the clock generator 22. The mode controller 32 receives the *CAS signal and the clock signal from the clock generator 18, and selects read-modify-write mode or CAS-before mode.
- Output a mode signal indicating a predetermined operating mode such as RAS refresh mode. mode controller 3
The mode signal from 2 is input to the refresh address counter 34. Refresh address counter 34 generates address signals indicating memory cells to be refreshed. A substrate bias generator 36 generates a substrate bias voltage (eg, VBB as described above).

Internal voltage generator 3 of internal voltage generation circuit 500
7 is constructed in accordance with the present invention. For example, the internal voltage generator 37 has the configuration shown in FIGS. 2(a) and 2(b). Internal voltage generator 37 generates internal voltage VINT1. This internal voltage is controlled according to the *RAS signal input as a clock *CLK to the gate of the transistor Q30. As will be described later, a one-shot pulse synchronized with the falling edge of the *RAS signal is generated, and the transistor Q3
0 gate as clock *CLK. Internal voltage VINT1 is supplied to RAS system 200. For example, the external supply voltage VEXT is 5V (=VCC), and the internal voltage VINT1 is 3.3V.

The internal voltage generator 38 is, for example, as shown in FIG. 2(a).
, (b), address change detection (ATD
) signal to generate a regulated internal voltage VINT1.

The ATD signal is generated when an address change is detected. Address change detection (ATD) for this purpose
) circuit is provided within the block of the address buffer 12a, for example.

FIG. 6 is a block diagram showing the ATD circuit. As shown in the figure, edge trigger circuits (ETG) 270 to 270 provided for each address bit A0 to A10
2710, p-channel MOS transistors T0 to T1
0, an inverter INV, a resistor R1, and a pulse width controller PWC. Address bits A0 to A10
When an edge is detected (detection of address change) in any of the above, the edge trigger signal *ETGA0 ~ *ET
A corresponding one of the GAs 10 turns on a corresponding transistor. Power supply voltage VCC is input to pulse width controller PWC via inverter INV. The pulse width controller PWC outputs an ATD signal of a predetermined pulse duration.

Returning to FIG. 5, internal voltage generator 39 is similarly constructed. FIG. 7 shows the sense amplifier/input/output gate 24
Its peripheral circuits including the sense amplifier and internal voltage generator 39 are shown. The internal voltage generator 39 includes the aforementioned on-chip voltage control circuit 100A and the one-shot pulse generator 60.
, and two n-channel MOS transistors Q40,Q
It has 41. The gate of series control transistor Q1 is controlled by on-chip voltage control circuit 100A via transistor Q40. The drain of transistor Q41 is connected to the gate of series control transistor Q1, and the source is grounded. The source of the series control transistor Q1 is connected to the high potential side line 51. Sense amplifier SA is connected to a pair of bit lines BL, *BL. This bit line pair BL, *BL has a word line WLn
, WLn+1, respectively.
is connected. The one-shot pulse generator 6 outputs a one-shot pulse *CLK1 in synchronization with the sense amplifier drive signal *φS. More specifically, the sense amplifier drive signal *φS
One-shot pulse *CLK1 synchronized with the falling edge of
changes to low level.

The sense amplifier SA is also connected to a high potential line 51 and a low potential line 52. N-channel MOS transistor Q42 is provided within low potential side line 52. While the sense amplifier SA is in the inactive state, the sense amplifier drive signals φS and *φS are at low and high levels, respectively. Therefore, transistors Q40 and Q41 are off and on, respectively. In this state, sense amplifier SA is disconnected from lines 51 and 52. On the other hand, when sense amplifier SA is activated, the levels of φS and *φS are inverted, and sense amplifier SA starts operating.

At this time, as shown in FIG. 8(a), the sense amplifier drive signal *φS changes from high level to low level, and the one-shot pulse CLK1 falls. Therefore, transistor Q30 is turned off, and gate voltage VG1 rises rapidly as shown in FIG. 8(c). This rise is a slight overshoot. If one shot pulse*
Without CLK1, gate voltage VG1 would gradually rise as shown in FIG. 8(c). As shown in FIG. 8(d), in response to the rapid rise of gate voltage VG1,
Internal voltage VINT3 rises quickly. On the other hand, if there were no one-shot pulse *CLK1, the internal voltage would gradually rise.

From the above explanation, the state in which the sense amplifier SA starts operating is detected from the sense amplifier drive signal *φS, and when this is detected, the series control transistor Q1
increase the gate voltage VG1 of.

Note that instead of a one-shot pulse, a plurality of continuous pulses can be generated from the sense amplifier drive signal *φS and directly applied to the control transistor Q1. As described above, while the *RAS signal is at a low level, the transistor Q30 is controlled to be turned off continuously or intermittently. This increases the gate voltage VG1 of the series control transistor Q1. This results in
It is possible to compensate for a drop in internal voltage after RAS system 200 starts operating. On the other hand, when the *RAS signal is at a high level, the RAS system 200 consumes a small amount of power. Therefore, during this period, transistor Q29 is short-circuited with transistor Q30. The CAS system 300 and sense system 400 are also controlled like the RAS system 200.

In the configuration of FIG. 5, internal voltage VINT1 supplied to RAS system 200 is controlled separately from internal voltage VINT2 supplied to CAS system 300. Instead, *RAS signal and *CAS signal (or chip internal signals corresponding to these signals (here, simply *RAS signal)
It is also possible to control the internal voltages VINT1 and VINT2 based on logical synthesis of the internal voltages VINT1 and VINT2. As shown in FIG. 9, an n-channel MOS transistor Q3
1 is connected in parallel to transistor Q30. *R
The AS signal is applied to the gate of transistor Q31, *
The CAS signal is applied to the gate of transistor Q30. *When both RAS and CAS signals are at low level, increase gate voltage VG1. Normal CAS-be
In the fore-RAS refresh mode, the *CAS signal changes to low level before the *RAS signal changes to low level. If internal voltage compensation is performed when the *CAS signal becomes low level, the compensation will be excessively performed.

This is because the CAS system 300 does not operate in the CAS-before-RAS refresh mode. Therefore, as shown in FIG. 9, when both signals become active, internal voltage compensation (gate voltage VG1 increase).

The on-chip voltage control circuit of the present invention is a DRA
It can be applied not only to M but also to SRAM. In this case, the chip enable signal *CE or the output enable signal *OE can be used as the clock *CLK. It can also be applied to logic circuits, etc.

[0042]

According to the present invention, by applying the fact that the current consumption of a chip is proportional to the cycle of the activation clock input from the outside, the drop in the internal power supply voltage due to the increase in current consumption is adjusted to the cycle of the activation clock. By correspondingly compensating, a stable in-chip power supply voltage can be obtained at all times. In particular, CMOS circuits (DRAM, S
It is suitable for application to RAM, logic LSI).

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a sectional view showing a modification of the second embodiment.

FIG. 4 is a diagram showing another modification.

FIG. 5: DR using the on-chip voltage control circuit of the present invention
It is a diagram showing the configuration of AM.

FIG. 6 is a diagram showing the configuration of an ATD circuit.

FIG. 7 is a diagram showing a peripheral circuit including a sense amplifier and an internal voltage generator.

8 is a waveform diagram showing the operation of the circuit shown in FIG. 7. FIG.

FIG. 9 is a diagram illustrating the main parts of another configuration example of a DRAM.

FIG. 10 is a diagram showing a first conventional example.

FIG. 11 is a diagram showing a second conventional example.

[Explanation of symbols]

100,100A on-chip voltage control circuit Q1
Series control transistor VEXT External supply voltage VINT Chip internal voltage

Claims (5)

[Claims] 1. An on-chip voltage control circuit that generates a chip internal power supply voltage (VINT) by lowering an externally supplied power supply voltage (VEXT) by a series control transistor (Q1), and controls the activation/deactivation of internal circuits. The internal resistance of the series control transistor is changed according to the state of a clock (*CLK) that controls the circuit, thereby suppressing the difference in chip internal power supply voltage between when the internal circuit is in an inactive state and when the internal circuit is in an active state. Semiconductor integrated circuit device. 2. An on-chip voltage control circuit that steps down an externally supplied power supply voltage (VEXT) and supplies it to an internal circuit as an internal power supply voltage (VINT), the on-chip voltage control circuit when the internal circuit is activated. 1. A semiconductor integrated circuit device characterized in that the current supply capacity of the semiconductor integrated circuit device is controlled to be larger than when it is inactivated. 3. An on-chip voltage control circuit that steps down an externally supplied power supply voltage (VEXT) and supplies it to an internal circuit as an internal power supply voltage (VINT), and switches the internal circuit from an inactive state to an active state. 1. A semiconductor integrated circuit device, wherein the current supply capability of the on-chip voltage control circuit is controlled to temporarily increase in response to the on-chip voltage control circuit. [Claim 4] Row address strobe signal (*RA
A row address strobe system (200) that operates in accordance with a column address strobe signal (*CAS) or a signal generated in synchronization with this, and a column address strobe system (200) that operates in accordance with a column address strobe signal (*CAS) or a signal generated in synchronization with this. 300) and sense amplifier drive signals (φS, *φS
) or a sense system (400) that operates according to a signal generated in synchronization with this, and an externally supplied power supply voltage (VEXT
) to generate a chip internal power supply voltage (VINT), and the on-chip voltage control circuit changes the current supply capability according to the state of a predetermined clock (*CLK). A semiconductor integrated circuit device characterized by: 5. The on-chip voltage control circuit receives the row address strobe signal or a signal generated in synchronization therewith as the predetermined clock, generates a first internal voltage, and controls the row address strobe signal. System (20
0), the column address strobe signal or a signal generated in synchronization therewith is inputted as the predetermined clock;
second internal voltage generating means (38) that generates an internal voltage and supplies it to the column address strobe system (300);
and a third internal voltage generator that inputs the sense amplifier drive signal or a signal generated in synchronization therewith as the predetermined clock, generates a third internal voltage, and supplies the generated third internal voltage to the sense system (400). 5. The semiconductor integrated circuit device according to claim 4, further comprising means (39).