JPS60179998A - Voltage detecting circuit - Google Patents

Abstract

PURPOSE:To always correct a drop of potential due to the junction leakage and to set the node potential at a proper level, by grounding the node cascaded to a capacitor of a voltage detecting circuit via a switching transistor. CONSTITUTION:A switching transistor TRQ3 of a voltage control circuit 13 for an ROM which is capable of a program to be electrically erased forming a voltage detecting circuit, a nonvolatile RAM, etc. is kept on excepting for a period when a signal W/E is set at a high level in a write mode. Then a connection node N1 between cascaded capacitors C1' and C2 is always kept at a ground potential. Therefore, if the electric charge is injected by the junction leakage caused when the high potential voltage IVP0 is set at ''0'' the electric charge is discharged via the TRQ3. Thus a drop of potential is corrected at the node N1 and the node potential is set at a proper level to obtain the write voltage of a proper level. Furthermore the capacitor area can be reduced by using a poly Si substrate to the capacitor C1'.

Description

[Detailed description of the invention] Technical field The present invention relates to a voltage detection circuit using a cascade arrangement. .

This voltage detection circuit can be applied to, for example, electrically erasable programmable ROM (E2FROM), non-volatile RAM (NOV
It is used in write voltage control circuits such as RAM).

TECHNICAL BACKGROUND The voltage V is set to, for example, 20 to 25 V, which is much larger than the normal power supply voltage Vee (for example, 5 V).

Conventionally, this write voltage vpp has been supplied from outside, but recently, a booster circuit is provided in each chip, thereby generating the write voltage (abbreviated as IVP in this case). This allows the chip's external power supply and external terminals to be reduced.

A clock is supplied to the booster circuit at the time of writing, and the write voltage IVP rises in accordance with this clock. In this case, it is necessary to detect the write voltage IVP and limit the voltage IVP so that it does not rise above a predetermined value. A write voltage control circuit is required.

Prior Art and Problems FIG. 1 is an overall configuration diagram of an E2FROM to which the present invention is applied. In FIG. 1, l is a memory cell, 2 is an address buffer that receives the X address signal At (1=0 to n), 3 is an X decoder, and 4 is a Y address (i No. At' (
Address buffer for receiving t = 0~n), 5 is Y7
'Coder, 6 is a Y-dart, 9 which selectively connects the sense amplifier 7 and write enable circuit 8 to the memory cell 1.
is the output buffer of the output data Do, lO is the input data D
The input bar of I is F. 11 is a mode select circuit that receives the tick enable signal CE, write enable signal WF2, and output enable signal OE and selects an operation mode; 12 is a mode select circuit that generates a write voltage (VPI) at the time of writing (W/E="l"); The external voltage circuit 13 is a write voltage control circuit that detects the voltage IPVO (substantially the same as IPV+) generated by the booster circuit 12 and controls the booster circuit 12 so that the write voltage IVP does not rise above a predetermined value.

Write voltage IVP of booster circuit 12 is applied to charge pump circuits 14 and 15. Note that the conventional write voltage control circuit 13 is not supplied with the write enable signal W/E.

FIG. 2 is a circuit diagram of a conventional write voltage control circuit. In FIG. 2, the write voltage control circuit includes a voltage detection circuit VDI formed by cascade connection of capacitors C1+'C2;
Inverter I configured by a degradation type transistor Q1 and an enhancement type transistor Q2
It has NV. At this time, when the potential vN of the node N1 rises, and therefore the convolution voltage IvP rises as shown in FIG.
When the potential N1 reaches the threshold voltage Vth of the inverter INV (threshold voltage of the transistor Q2), the output of the inverter INV changes from high level to low level.

As a result, the clock supply in the booster circuit 12 of FIG.
It doesn't go beyond that. When the inverter INV is configured as shown in Fig. 2, its threshold voltage Vt
h is large and the flaw is at most 3 to 4V, therefore,
Since it is impossible to directly detect the write voltage IVPo by the inverter INV, the voltage is lowered by the voltage detection circuit VDI and then applied to the inverter INV. Moreover, since the voltage detection circuit VD cliff in FIG. 2 is capacitively divided, it has the advantage that there is no DC loss.

The voltage detection circuit of FIG. 2 is constructed with a two-layer polysilicon structure. Tsumashi, as shown in Figure 4, Canogushita C! The capacitor C2 is composed of a first polysilicon layer 45, a second polysilicon layer 46, and an insulating layer (SI02 not shown) between them, and the capacitor C2 is a diffusion-resistant layer in the P-silicon substrate 41 42, Insulating layer (8502)
43 and a first polysilicon layer 45.

However, in this case, the tunnel emission starting voltage of the insulating layer (SIO Therefore, there is a problem that the area has to be increased accordingly, and moreover, the charges injected into the node N1 through the tunnel (electrons are emitted from 45 to 46, so holes remain in the polysilicon layer 45). ) remains semi-permanently, resulting in a problem in that the node potential vN1 rises and the voltage IVP becomes lower than a predetermined value accordingly.

Note that two-layer polysilicon can also be applied to the capacitor CI.

Object of the Invention An object of the present invention is to ground the capacitor connection node N1 of the voltage detection circuit via a switching transistor, and turn on the switching transistor when the voltage detection circuit is not used to maintain the node potential vN at the ground potential. Particularly, the above-mentioned tunnel leakage problem is solved, and at the same time, the area of the capacitor is reduced by using a Po1ySi-81 substrate (reverse conductive layer) for the capacitor Ct. Even if charges due to leakage are injected into the node N1, the charges are discharged by the switching transistor, thereby making the potential of the node N1 appropriate.

Structure of the Invention In order to achieve the above-mentioned object, according to the present invention, a first capacitor having one electrode connected to a power supply line, a second capacitor connected in series with the first capacitor, a switching transistor connected between the connection point of the first and second capacitors and the power supply line; applying a detected voltage to one electrode of the second capacitor and outputting it to the connection point; The switching transistor is configured to detect that the value of the detected voltage has reached a predetermined value based on the divided voltage, and to conduct the switching transistor during a period when the detected voltage is not applied. A voltage detection circuit with features is provided.

Examples of the invention The present invention will be described in detail with reference to FIGS. 5 and 6.

FIG. 5 is a circuit diagram of a write voltage control circuit to which a voltage detection circuit according to an embodiment of the present invention is applied. In the voltage detection circuit VDl' of FIG. 5, the capacitor C of FIG.
A capacitor CM' is provided in place of node N1, and a transistor Q3 is connected between node N1 and ground. This transistor Q3 is controlled by a write enable signal W/g. During writing, the signal W/E is at a high level (=''1'') and the transistor Q3 is turned off, but at other times the signal W/E is at a low level (2'''0#).
), and the transistor Q3 turns on. Voltage IVP
0 becomes 0 level, therefore, the potential of the node N1 (■N1) swings to a negative voltage due to junction leakage, but due to the presence of the transistor Q3 in the on state, the potential of the node N (■8. is not negative. Furthermore, in this case, even if transistor Q3 is off, node N
! Potential ■8. can be suppressed to a negative value of the threshold voltage of transistor Q3, for example, -0.6V.Also, even if a pack bias of, for example, -5V is applied to the substrate, if the signal φ is in the 0'' state, the node N1 The potential does not shift to the back bias side.

FIG. 6 is a sectional view of the voltage detection circuit Dvf of FIG. 5.

In FIG. 6, an active area Al defined by a field oxide film 62 in a P-silicon substrate 61 is shown.
r Ax l A3 is provided, a capacitor C1' is formed in the area AI, and a capacitor C2 is formed in the area A2.
is formed, and a transistor Qs is formed in region A3. That is, in the region A1, the capacitor Cr, the impurity diffusion region 63 in the substrate 61, the polysilicon layer 64 to which the % pressure IVPo is applied, and the insulating layer (
SiO2 (not shown) is formed. In the region A, the capacitor C2 is the impurity diffusion region 6 in the substrate 61.
5, polysilicon layer 66, and an insulating layer between them (
(not shown). In this case, the polysilicon layer 66 is connected to the impurity diffusion region 63 through the impurity diffusion region 63', and the impurity diffusion region 65 is grounded through the impurity diffusion region 65'. Also, area A3
In this case, transistor Q3 has two impurity diffusion regions 67.
．． 68, polysilicon layer 69 to which signal W/E is applied;
and is formed on an insulating layer (not shown) directly below polysilicon layer 69. Note that in this case, the impurity diffusion region 68
is grounded.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, in the voltage detection circuit using vertically connected capacitors, the capacitor connection node is grounded via the switching transistor.
A drop in the potential of the node due to leakage is always corrected, and therefore the voltage detection circuit according to the present invention is
When applied to a write voltage control circuit for ROM or NOVRAM, an appropriate write voltage can be obtained.

[Brief explanation of the drawing]

Figure 1 is a professional circuit diagram showing the overall configuration of an E2FROM to which the present invention is applied, Figure 2 is a circuit diagram of a conventional write voltage control circuit, and Figure 3 is the write voltage IVP and node potential of Figure 2. vN, FIG. 4 is a cross-sectional view of the voltage detection circuit of FIG. 2, FIG. 5 is a circuit diagram of a write voltage control circuit including a voltage detection circuit as an embodiment of the present invention, and FIG. 6 is a cross-sectional view of the voltage detection circuit of FIG. 5. FIG. l2: External pressure circuit, 13: Write voltage control circuit, C1':
First capacitor, C2 = second capacitor NQ3
Niswitching transistor, IVPo = high potential signal. Patent Applicant: Fujitsu Limited, Patent Application Agent, Patent Attorney Akira Aoki, Patent Attorney Kazuyuki Nishidate (1) Yukio Patent Attorney, Akira Yamaguchi Procedural Amendment (Voluntary) February 7A, 1985 Director-General of the Japan Patent Office Will Manabu Ka 1, Indication of the case Patent Application No. 35115 filed in 1988 2, Name of the invention Voltage detection circuit 3, Relationship to the case by the person making the amendment Name of the patent applicant (522,) Fujitsu Ltd. 4, Agent resident Address: Shizuka Toranomon Pill, 8-10 Toranomon-chome, Minato-ku, Tokyo 105 Phone (504) 0721 1', . Name Patent Attorney (6579) Akira Aomi';', lj4'q,
L,'! (3 others) 1) ``Detailed Description of the Invention'' column in the Ministry of Specifications 2) ``Brief Description of Drawings'' column in the specification 3) Drawing (Figure 6) 6. Contents of the amendment 1) A ) Correct the formula in the 6th line of the 4th chapter of Book 4 + 1. B) Meikan 1po, page 4, line 13 from the bottom and page 6, line 2
Correct line rIVPJ to ``IVPo,j. C) Correct ``Light enable'' in the 3rd line of Meiso 1st Book 8th Tei to ``Write/Erase.'' 2) Specification No. 1 O-sei No. 16 item r IVPJ is changed to “IVP
Correct as O,i. 3) Correct the reference number "65" of the polysilicon layer in Figure 6 to the red line (II'66Jl). 7. Attached catalog drawings of class jM' (Figure 6) 1 Procedural Amendment Form Showa Hirozuki 7, 1960 Commissioner of the Japan Patent Office Gakudono Shiga 1, Indication of the case 1988 Patent Application No. 3511's 2, Name of the invention Voltage detection circuit 3, Person making the amendment Relationship to the case Name of patent applicant (522) Fujitsu Limited 5, Subject of amendment 1) “°Claims” column of the specification 2) 1 of the specification
- Column 6 of Detailed Description of the Invention j, Contents of Amendment l) As per the attached sheet. 2) A) Delete "and" on page 7, line 12 of the specification. 07. List of attached documents 1) Amended claims 1 copy 2. Percentage claims 1. One electrode connects the source line (= the first capacitor connected to the first capacitor, and the second
between the connection point of the first and second capacitors and the power supply line (two connected switching transistors), and applying a detected voltage to one electrode of the second capacitor; The value of the detected voltage has reached a predetermined value based on the connection point (2 output divided voltages (-)?
A voltage detection circuit that detects the voltage during a period in which the voltage to be detected is not applied.

Claims (1)

[Claims] 1. A first capacitor with one electrode connected to the power supply line, a second capacitor connected in series with the first capacitor, and the 1.2 capacitor. a switching transistor connected between the connection point and the power supply line, applying a detected voltage to one electrode of the second capacitor, and based on the divided voltage output to the connection point; A voltage detection circuit characterized in that it detects that the value of the voltage to be detected has reached a predetermined value, and the switching transistor is made conductive during a period when the voltage to be detected is not applied.