JPH10242519A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH10242519A
JPH10242519A JP4027197A JP4027197A JPH10242519A JP H10242519 A JPH10242519 A JP H10242519A JP 4027197 A JP4027197 A JP 4027197A JP 4027197 A JP4027197 A JP 4027197A JP H10242519 A JPH10242519 A JP H10242519A
Authority
JP
Japan
Prior art keywords
chips
electrodes
led chip
semiconductor device
led
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4027197A
Other languages
Japanese (ja)
Other versions
JP3267183B2 (en
Inventor
Jiro Hashizume
二郎 橋爪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP4027197A priority Critical patent/JP3267183B2/en
Publication of JPH10242519A publication Critical patent/JPH10242519A/en
Application granted granted Critical
Publication of JP3267183B2 publication Critical patent/JP3267183B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the productivity of a semiconductor device, by providing a three-dimensional molded substrate on which a plurality of recessed sections are formed for housing LED chips, and mounting the LED chips on the substrate so that the surfaces of the chips other than the electrode forming surfaces of the chips may come into contact with the bottoms of the recessed sections. SOLUTION: An LED chip 1 is constituted of a P-N junction and electrodes 11 and 12 are respectively formed on the surfaces of P- and N-type areas except joining surfaces. A three-dimensional molded substrate 3 has a plurality of recessed sections 31 for housing LED chips 1. The chips 1 are mounted on the substrate 3 so that the surfaces of the chips 1 other than the electrode forming surfaces of the chips 1 on which electrodes 11 and 12 are formed may come into contact with the bottoms 32 of the recessed sections 31. Since a conductive adhesive 5 enters the recessed sections 31 through holes 34 and adheres to the electrodes 11 and 12, the fixation of the chips 1 is made simultaneously with the connection between the electrodes 11 and 12 of the adjacent chips 1.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、回路基板に複数の
LEDチップを実装してなる半導体装置に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of LED chips mounted on a circuit board.

【0002】[0002]

【従来の技術】従来、LEDは電子機器のインジケータ
等の用途に用いられてきたものであるが、近年、その発
光効率や輝度が向上し、単位入力あたりの輝度が白熱ラ
ンプに優るようなLED素子が開発され、このLED素
子を複数個まとめることにより、照明用途への応用が可
能となってきた。
2. Description of the Related Art Conventionally, LEDs have been used for applications such as indicators of electronic equipment. In recent years, LEDs whose luminous efficiency and luminance have been improved, and whose luminance per unit input is superior to incandescent lamps, have been developed. A device has been developed, and by integrating a plurality of the LED devices, application to lighting applications has become possible.

【0003】また、LED素子は長寿命であることから
ランプの取り替えの省力化等のメンテナンス性のメリッ
トがあり、発光波長レンジが狭いことにより生鮮食物に
ダメージを与える赤外線が出ない照明(例えば、鮮魚店
のショウケース用照明)として使用できるというメリッ
ト、美術品を退色劣化させる紫外線が出ない照明(例え
ば、美術館、博物館の照明)等に使用できるというメリ
ット等がある。
[0003] Further, since the LED element has a long life, there is a merit of maintenance such as labor saving of lamp replacement, and an illumination which does not emit infrared rays which damage fresh food due to a narrow emission wavelength range (for example, There is an advantage that it can be used as illumination for a showcase of a fresh fish store), and that it can be used for illumination that does not emit ultraviolet rays (for example, illumination of art museums and museums) that discolors and degrades artworks.

【0004】ここで、現行のLED素子の実装例を図7
により説明する。1個のLEDチップ1の電極11の面
をリードフレーム2aに導電性接着剤でダイボンドする
ことにより固着し、LEDチップ1の他方の電極12は
他方のリードフレーム2bへボンディングワイヤ21に
よりワイヤボンドし、ダイオードのPN電極へのリード
フレーム2a、2bの接続がなされ、リードフレーム2
a、2bを介してLEDチップ1に給電されるようにな
っている。さらに、金型成形により透明の封止樹脂22
をレンズ状に成形することで、個別のLED素子が完成
する。このようにして完成された個別のLED素子のリ
ードフレーム2a、2bを基板の所定位置に半田付け等
により実装する。つまり、LEDチップ1の下面及び上
面の電極11、12に対して、接着及びワイヤボンディ
ングという別々の接合方法を使用している。
[0004] Here, a mounting example of a current LED element is shown in FIG.
This will be described below. The surface of the electrode 11 of one LED chip 1 is fixed to the lead frame 2a by die bonding with a conductive adhesive, and the other electrode 12 of the LED chip 1 is wire bonded to the other lead frame 2b by a bonding wire 21. The lead frames 2a and 2b are connected to the PN electrodes of the diodes,
Power is supplied to the LED chip 1 via a and 2b. Further, the transparent sealing resin 22 is formed by molding.
Is molded into a lens shape to complete an individual LED element. The lead frames 2a and 2b of the individual LED elements completed in this way are mounted at predetermined positions on the substrate by soldering or the like. That is, separate bonding methods of bonding and wire bonding are used for the electrodes 11 and 12 on the lower surface and the upper surface of the LED chip 1.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上述の
ようなLED素子を照明分野に応用する場合には、LE
D素子の個々の輝度は低いため多数個のLED素子を使
用する必要があり、複数のLED素子のリードフレーム
2a、2bを各素子への電流供給回路が形成された基板
の所定位置に半田付け等により一括して実装しなければ
ならない。
However, when the above-mentioned LED element is applied to the field of lighting, LE is required.
Since the brightness of each of the D elements is low, it is necessary to use a large number of LED elements, and the lead frames 2a and 2b of the plurality of LED elements are soldered to predetermined positions of a substrate on which a current supply circuit for each element is formed. It has to be implemented collectively by the method.

【0006】従って、、上述のようなLED素子を用い
て照明装置を作製する場合には、LED素子をつくる段
階で素子接着及びワイヤボンディングという2つの接合
方法により電極を11、12をリードフレーム2a、2
bに固着、接続し、さらに、複数のLED素子のリード
フレーム2a、2bを基板の所定位置に半田付け等によ
り実装するという工程が必要となり生産性が悪い。
Therefore, when manufacturing a lighting device using the above-described LED elements, the electrodes 11 and 12 are connected to the lead frame 2a by two bonding methods of element bonding and wire bonding at the stage of manufacturing the LED elements. , 2
b, and the steps of mounting the lead frames 2a and 2b of the plurality of LED elements at predetermined positions on the substrate by soldering or the like are required, and the productivity is poor.

【0007】本発明は、上記の点に鑑みてなしたもので
あり、その目的とするところは、複数のLEDチップを
基板に実装した半導体装置であって、生産性の良い半導
体装置を提供することにある。
[0007] The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device in which a plurality of LED chips are mounted on a substrate and which has high productivity. It is in.

【0008】[0008]

【課題を解決するための手段】請求項1記載の発明は、
複数のLEDチップと、該LEDチップの各々を収納す
る複数の凹部が形成された3次元成形基板とを有し、前
記LEDチップの電極面でない面が前記凹部の底面側に
なるように前記LEDチップを搭載し、隣接するLED
チップの電極間を導電性部材により接続するようにした
ことを特徴とするものである。
According to the first aspect of the present invention,
A plurality of LED chips, and a three-dimensional molded substrate formed with a plurality of recesses for accommodating each of the LED chips, wherein the LED chip has a non-electrode surface on the bottom side of the recesses. Chip mounted, adjacent LED
The electrodes of the chip are connected by a conductive member.

【0009】請求項2記載の発明は、請求項1記載の発
明において、前記凹部の側壁に貫通孔を形成し、前記導
電性部材として導電性接着剤を用い、前記貫通孔を介し
て導電性接着剤により隣接するLEDチップの電極間を
接続するようにしたことを特徴とするものである。
According to a second aspect of the present invention, in the first aspect of the present invention, a through hole is formed in a side wall of the recess, a conductive adhesive is used as the conductive member, and a conductive material is formed through the through hole. It is characterized in that the electrodes of adjacent LED chips are connected by an adhesive.

【0010】請求項3記載の発明は、請求項1記載の発
明において、前記凹部の側壁に貫通孔を形成するととも
に、該貫通孔の内面及び前記側壁の表裏両面に配線パタ
ーンを形成し、前記導電性部材として半田ペーストを用
い、前記貫通孔を介して半田ペーストにより隣接するL
EDチップの電極間を接続するようにしたことを特徴と
するものである。
According to a third aspect of the present invention, in the first aspect of the present invention, a through hole is formed in a side wall of the recess, and a wiring pattern is formed on an inner surface of the through hole and on both front and back surfaces of the side wall. A solder paste is used as the conductive member, and the adjacent L is connected with the solder paste through the through hole.
It is characterized in that the electrodes of the ED chip are connected.

【0011】請求項4記載の発明は、請求項1乃至請求
項3記載の発明において、前記LEDチップを前記凹部
の底面に搭載する際に接着剤により仮止めするようにし
たことを特徴とするものである。
According to a fourth aspect of the present invention, in the first to third aspects of the present invention, the LED chip is temporarily fixed with an adhesive when the LED chip is mounted on the bottom surface of the concave portion. Things.

【0012】請求項5記載の発明は、請求項1乃至請求
項4記載の発明において、前記凹部の側壁と底面とが鈍
角をなすようにしたことを特徴とするものである。
According to a fifth aspect of the present invention, in the first to fourth aspects of the present invention, the side wall and the bottom surface of the recess form an obtuse angle.

【0013】請求項6記載の発明は、請求項1乃至請求
項5記載の発明において、前記LEDチップの上面側を
樹脂封止する際に、透明な樹脂を注入し加熱硬化させる
ことによりレンズを形成するようにしたことを特徴とす
るものである。
According to a sixth aspect of the present invention, in the first to fifth aspects of the invention, when the upper surface side of the LED chip is sealed with a resin, a transparent resin is injected and cured by heating. It is characterized in that it is formed.

【0014】[0014]

【発明の実施の形態】以下、本発明の実施の形態の一例
を図面に基づき説明する。図1は本発明の実施の形態の
一例に係る半導体装置の一部の断面状態を示す模式図で
あり、1は0.3mm立方の微小なLEDチップであ
り、PN接合により構成され、PNの各領域の接合面で
ない面には各々電極11、12が形成されている。3は
3次元成形基板(MID基板:Molded Inte
rconnection Device)であり、各L
EDチップ1を収納するための複数の凹部31を有して
いる。LEDチップ1は、電極11、12の形成されて
いない面が凹部31の底面32に当接するように搭載さ
れる。LEDチップ1をMID基板3の凹部31に搭載
した状態を示す概略構成図を図2に示す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic view showing a cross-sectional state of a part of a semiconductor device according to an example of an embodiment of the present invention. Reference numeral 1 denotes a small LED chip of 0.3 mm 3 cubic, which is formed by a PN junction. Electrodes 11 and 12 are formed on the non-joining surfaces of the respective regions. 3 is a three-dimensional molded substrate (MID substrate: Molded Inte
rconnection Device), and each L
It has a plurality of recesses 31 for accommodating the ED chip 1. The LED chip 1 is mounted so that the surface on which the electrodes 11 and 12 are not formed contacts the bottom surface 32 of the concave portion 31. FIG. 2 is a schematic configuration diagram showing a state in which the LED chip 1 is mounted on the concave portion 31 of the MID substrate 3.

【0015】LEDチップ1の搭載部としての凹部31
のサイズは、LEDチップ1の寸法との関係で決めら
れ、凹部31の側壁33の傾斜角度や寸法はLEDチッ
プ1の側面の内、電極11、12の形成されていない面
から発光される光の側壁33による反射を考慮して決め
られる。つまり、電極11、12の形成されていない面
に対向する側壁33は側壁33による反射波が凹部31
の開口部側に行くように、凹部31の底面に対して鈍角
となるように、傾斜を持たせるのが良い。なお、全ての
側壁33に傾斜を持たせてもかまわない。
Recess 31 as mounting portion for LED chip 1
Is determined by the relationship with the dimensions of the LED chip 1, and the inclination angle and dimensions of the side wall 33 of the concave portion 31 are the light emitted from the side of the LED chip 1 where the electrodes 11 and 12 are not formed. Is determined in consideration of the reflection by the side wall 33. In other words, the side wall 33 facing the surface on which the electrodes 11 and 12 are not formed is reflected by the side wall 33 by the concave portion 31.
It is preferable to provide an inclination so as to reach the opening side of the concave portion 31 so as to form an obtuse angle with respect to the bottom surface of the concave portion 31. Note that all the side walls 33 may have an inclination.

【0016】また、電極11、12に対向する側壁33
には貫通孔34が形成されている。複数のLEDチップ
1を各々MID基板3の各凹部31に搭載した状態で、
MID基板3の裏側から銀等の導電性粒子が入った導電
性接着剤5を注入していけば、導電性接着剤5は貫通孔
34を介して凹部31内に入り込み、電極11、12に
付着し、LEDチップ1の固定と隣接のLEDチップ1
の電極11、12との接続とが同時に行われる。なお、
LEDチップ1の搭載時にUV接着剤や即時硬化型の接
着剤等の接着剤4により凹部31の底面に仮止めしてお
けば、導電性接着剤5の注入という次の工程までの位置
ずれ等を防止することができる。
Further, a side wall 33 facing the electrodes 11 and 12 is provided.
Is formed with a through hole 34. In a state where the plurality of LED chips 1 are mounted on the respective recesses 31 of the MID substrate 3,
If the conductive adhesive 5 containing conductive particles such as silver is injected from the back side of the MID substrate 3, the conductive adhesive 5 enters the recess 31 through the through-hole 34 and contacts the electrodes 11 and 12. Attach and fix LED chip 1 and adjacent LED chip 1
Connection with the electrodes 11 and 12 is performed at the same time. In addition,
If the LED chip 1 is temporarily mounted on the bottom surface of the concave portion 31 with an adhesive 4 such as a UV adhesive or an instant-curing adhesive at the time of mounting the LED chip 1, a displacement of the conductive adhesive 5 until the next step of injection is performed. Can be prevented.

【0017】図3は本発明の他の実施形態に係る半導体
装置の一部断面状態を示す模式図である。本実施形態で
は、上述の実施形態における導電性接着剤5の替わりに
半田ペースト6を使用している。半田ペースト6のMI
D基板3への濡れを良くするため、MID基板3の各凹
部31の側壁33の内外面及び貫通孔34の内面には配
線パターン7を形成しておく。従って、貫通孔34の内
面はスルーホール35となる。上述の実施形態と同様な
方法で導電性接着剤5に替えて半田ペースト6を注入
し、リフロー硬化させるのである。
FIG. 3 is a schematic diagram showing a partial cross-sectional state of a semiconductor device according to another embodiment of the present invention. In this embodiment, a solder paste 6 is used instead of the conductive adhesive 5 in the above-described embodiment. MI of solder paste 6
In order to improve the wetting of the D substrate 3, the wiring patterns 7 are formed on the inner and outer surfaces of the side walls 33 and the inner surfaces of the through holes 34 of the concave portions 31 of the MID substrate 3 in advance. Therefore, the inner surface of the through hole 34 becomes a through hole 35. The solder paste 6 is injected instead of the conductive adhesive 5 in the same manner as in the above-described embodiment, and is cured by reflow.

【0018】図4は本発明のさらに他の実施形態に係る
半導体装置の一部断面状態を示す模式図である。本実施
形態では、凹部31の側壁33には貫通孔34は形成せ
ず、隣接する凹部31の側壁33間が接続されるように
配線パターン8を形成しておく。ここで、LEDチップ
1を凹部31に搭載した状態で、LEDチップ1が搭載
された側から凹部31内に半田ペースト6を注入し、リ
フロー硬化させる。隣接するLEDチップ1の電極1
1、12間は配線パターン8及び半田ペースト6により
接続される。
FIG. 4 is a schematic diagram showing a partial cross-sectional state of a semiconductor device according to still another embodiment of the present invention. In the present embodiment, the through holes 34 are not formed in the side walls 33 of the concave portions 31, and the wiring patterns 8 are formed so as to connect between the side walls 33 of the adjacent concave portions 31. Here, in a state where the LED chip 1 is mounted in the concave portion 31, the solder paste 6 is injected into the concave portion 31 from the side on which the LED chip 1 is mounted, and is cured by reflow. Electrode 1 of adjacent LED chip 1
The wirings 1 and 12 are connected by the wiring pattern 8 and the solder paste 6.

【0019】以上の実施形態によれば、複数のLEDチ
ップ1を各々MID基板3の各凹部31に搭載した状態
で、導電性接着剤5あるいは半田ペースト6を注入すれ
ば、隣接するLEDチップ1の電極11、12間を一括
して接続できるので、素子接着及びワイヤボンディング
という接合工程及び基板への接続という工程という3つ
の工程が必要であった従来の半導体装置に比して、製造
工程の簡略化、生産性の向上が図れる。また、接合の工
程品質管理も1工程の管理ですむので、歩留まりの安定
性が期待できる。
According to the above embodiment, when the conductive adhesive 5 or the solder paste 6 is injected in a state where the plurality of LED chips 1 are mounted in the respective recesses 31 of the MID substrate 3, the adjacent LED chips 1 Electrodes 11 and 12 can be connected collectively, so that three steps of a bonding step of element bonding and wire bonding and a step of connection to a substrate are required, and thus the manufacturing process of the conventional semiconductor device is difficult. Simplification and improvement in productivity can be achieved. In addition, since the joining process quality control requires only one process, stable yield can be expected.

【0020】図3で示した実施形態では、半田ペースト
6を注入する工程での不良があった場合には、加熱する
ことにより容易に不良のLEDチップ1を取り除いた
り、良品への置き換えが可能となる。なお、導電性接着
剤5を用いた工程の方でも、仮硬化状態で電気導通検査
を行うことが可能である。
In the embodiment shown in FIG. 3, if there is a defect in the step of injecting the solder paste 6, the defective LED chip 1 can be easily removed by heating or replaced with a good one. Becomes Note that the electrical continuity test can be performed in a temporarily cured state even in the process using the conductive adhesive 5.

【0021】また、図4で示した実施形態では、図3で
示した実施形態と比べて半田ペーストの量が少なくて済
む。一方、図3で示した実施形態では、半田ペーストを
MID基板3のLEDチップ1が搭載された側と反対側
から注入しているので、過剰な半田ペーストが注入され
た場合でも半田ペーストがLEDチップ1の上面まで達
して短絡するというような事態を少なくできる。
Further, in the embodiment shown in FIG. 4, the amount of the solder paste is smaller than that in the embodiment shown in FIG. On the other hand, in the embodiment shown in FIG. 3, since the solder paste is injected from the side of the MID substrate 3 opposite to the side on which the LED chip 1 is mounted, even when excessive solder paste is injected, the solder paste is It is possible to reduce a situation in which a short circuit is reached by reaching the upper surface of the chip 1.

【0022】図5は本発明のさらに他の実施形態に係る
半導体装置の一部断面状態及び上面を示す模式図であ
る。本実施形態では、以上の実施形態のものにおいて、
凹部31の上方から透明な(光透過性を有し、必要に応
じ多少の着色可)封止樹脂を滴下し、加熱硬化させるこ
とにより、レンズ9を形成する。ここで、レンズ9は、
封止樹脂の吐出量の制御や、図6に示すように、凹部3
1の形状を変えることにより、所望の配光特性を実現す
ることができる。図5の場合は凹部31の平面形状が正
方形であり、XY軸に対称なレンズを形成するが、図6
(a)の場合は凹部31の平面形状が長方形であり、X
Y方向が等しくないレンズを形成することができ、図6
(b)の場合は凹部31の上部に円形の座ぐり10を設
けることにより球面のレンズを形成することが可能であ
る。
FIG. 5 is a schematic view showing a partial cross section and a top view of a semiconductor device according to still another embodiment of the present invention. In the present embodiment, in the above embodiment,
The lens 9 is formed by dropping a transparent (light-transmissive and somewhat colored as necessary) sealing resin from above the concave portion 31 and heating and curing the resin. Here, the lens 9
Control of the discharge amount of the sealing resin and, as shown in FIG.
By changing the shape of 1, the desired light distribution characteristics can be realized. In the case of FIG. 5, the plane shape of the concave portion 31 is a square, and a lens symmetric with respect to the XY axes is formed.
In the case of (a), the plane shape of the concave portion 31 is rectangular, and X
A lens having unequal Y directions can be formed, and FIG.
In the case of (b), it is possible to form a spherical lens by providing a circular counterbore 10 above the concave portion 31.

【0023】本実施形態によれば、凹部31内のLED
チップ1の上部に封止樹脂によりレンズ9を形成したの
で、所望の配光特性を有する照明用途に使用することが
できる。
According to this embodiment, the LED in the concave portion 31
Since the lens 9 is formed on the upper portion of the chip 1 with a sealing resin, the lens 9 can be used for lighting applications having desired light distribution characteristics.

【0024】なお、3次元成形基板3の成形時に、熱伝
導性の良い金属材料やセラミック等の無機材料を同時成
形したり、あるいは後で貼り付けることにより、放熱性
を良くすることも可能である。
When the three-dimensional molded substrate 3 is molded, it is also possible to improve the heat radiation by simultaneously molding or attaching an inorganic material such as a metal material or a ceramic having a good thermal conductivity, or attaching it later. is there.

【0025】[0025]

【発明の効果】以上のように、請求項1記載の発明によ
れば、複数のLEDチップと、該LEDチップの各々を
収納する複数の凹部が形成された3次元成形基板とを有
し、前記LEDチップの電極面でない面が前記凹部の底
面側になるように前記LEDチップを搭載し、隣接する
LEDチップの電極間を導電性部材により接続するよう
にしたので、製造工程が簡略化でき、複数のLEDチッ
プを搭載した半導体装置を生産性良く製造することがで
きる。
As described above, according to the first aspect of the present invention, there are provided a plurality of LED chips, and a three-dimensional molded substrate formed with a plurality of recesses for accommodating each of the LED chips. Since the LED chip is mounted such that the non-electrode surface of the LED chip is on the bottom side of the recess and the electrodes of adjacent LED chips are connected by a conductive member, the manufacturing process can be simplified. In addition, a semiconductor device on which a plurality of LED chips are mounted can be manufactured with high productivity.

【0026】請求項2記載の発明は、請求項1記載の発
明において、前記凹部の側壁に貫通孔を形成し、前記導
電性部材として導電性接着剤を用い、前記貫通孔を介し
て導電性接着剤により隣接するLEDチップの電極間を
接続するようにすれば、3次元成形基板の凹部のLED
チップが搭載されていない側から導電性接着剤を注入す
れば、貫通孔を介して導電性接着剤が流れ、隣接するL
EDチップの電極間の接続が行われるのである。
According to a second aspect of the present invention, in the first aspect of the present invention, a through hole is formed in a side wall of the concave portion, a conductive adhesive is used as the conductive member, and a conductive material is provided through the through hole. If the electrodes of adjacent LED chips are connected by an adhesive, the LED in the concave portion of the three-dimensional molded substrate
If the conductive adhesive is injected from the side where the chip is not mounted, the conductive adhesive flows through the through-hole and the adjacent L
The connection between the electrodes of the ED chip is made.

【0027】請求項3記載の発明は、請求項1記載の発
明において、前記凹部の側壁に貫通孔を形成するととも
に、該貫通孔の内面及び前記側壁の表裏両面に配線パタ
ーンを形成し、前記導電性部材として半田ペーストを用
い、前記貫通孔を介して半田ペーストにより隣接するL
EDチップの電極間を接続するようにすれば、3次元成
形基板の凹部のLEDチップが搭載されていない側から
半田ペーストを注入すれば、貫通孔を介して半田ペース
トが流れ、隣接するLEDチップの電極間の接続が行わ
れるのである。
According to a third aspect of the present invention, in the first aspect of the present invention, a through hole is formed in a side wall of the concave portion, and a wiring pattern is formed on an inner surface of the through hole and on both front and back surfaces of the side wall. A solder paste is used as the conductive member, and the adjacent L is connected with the solder paste through the through hole.
If the electrodes of the ED chip are connected, if the solder paste is injected from the side of the concave portion of the three-dimensional molded substrate on which the LED chip is not mounted, the solder paste flows through the through-hole and the adjacent LED chip The connection between the electrodes is made.

【0028】請求項4記載の発明は、請求項1乃至請求
項3記載の発明において、前記LEDチップを前記凹部
の底面に搭載する際に接着剤により仮止めするようにす
れば、導電性接着剤や半田ペースト等の導電性部材5の
注入という次の工程までのLEDチップの位置ずれ等を
防止することができるのである。
According to a fourth aspect of the present invention, in the first to third aspects of the present invention, when the LED chip is temporarily fixed with an adhesive when the LED chip is mounted on the bottom surface of the concave portion, the conductive adhesive is provided. It is possible to prevent the LED chip from being displaced until the next step of injecting the conductive member 5 such as an agent or a solder paste.

【0029】請求項5記載の発明は、請求項1乃至請求
項4記載の発明において、前記凹部の側壁と底面とが鈍
角をなすようにすれば、LEDチップから発光される光
を効率良く外部に取り出すことができる。
According to a fifth aspect of the present invention, in the first to fourth aspects of the present invention, if the side wall and the bottom surface of the concave portion form an obtuse angle, the light emitted from the LED chip can be efficiently emitted to the outside. Can be taken out.

【0030】請求項6記載の発明は、請求項1乃至請求
項5記載の発明において、前記LEDチップの上面側を
樹脂封止する際に、透明な樹脂を注入し加熱硬化させる
ことによりレンズを形成するようにすれば、レンズ形状
を所望の形状にすることにより、所望の配光特性を有す
る照明用途に使用することができる。
According to a sixth aspect of the present invention, in the first to fifth aspects of the present invention, when the upper surface of the LED chip is sealed with a resin, a transparent resin is injected and cured by heating. If it is formed, it can be used for lighting applications having desired light distribution characteristics by making the lens shape a desired shape.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態に係る半導体装置の一部の
断面状態を示す模式図である。
FIG. 1 is a schematic diagram showing a cross-sectional state of a part of a semiconductor device according to an embodiment of the present invention.

【図2】同上に係るLEDチップをMID基板の凹部に
搭載した状態を示す概略構成図である。
FIG. 2 is a schematic configuration diagram showing a state where the LED chip according to the above is mounted in a concave portion of an MID substrate.

【図3】本発明の他の実施形態に係る半導体装置の一部
の断面状態を示す模式図である。
FIG. 3 is a schematic diagram showing a cross-sectional state of a part of a semiconductor device according to another embodiment of the present invention.

【図4】本発明のさらに他の実施形態に係る半導体装置
の一部の断面状態を示す模式図である。
FIG. 4 is a schematic view showing a partial cross-sectional state of a semiconductor device according to still another embodiment of the present invention.

【図5】本発明のさらに他の実施形態に係る半導体装置
の一部の断面状態及び平面状態を示す模式図である。
FIG. 5 is a schematic diagram showing a cross-sectional state and a planar state of a part of a semiconductor device according to still another embodiment of the present invention.

【図6】同上に係るMID基板の凹部の他の形態の断面
状態及び平面状態を示す模式図である。
FIG. 6 is a schematic diagram showing a cross-sectional state and a planar state of another mode of the concave portion of the MID substrate according to the above.

【図7】従来のLED素子の断面状態を示す模式図であ
る。
FIG. 7 is a schematic diagram showing a cross-sectional state of a conventional LED element.

【符号の説明】[Explanation of symbols]

1 LEDチップ 3 3次元成形基板(MID基板) 4 接着剤 5 導電性接着剤 6 半田ペースト 7 配線パターン 8 配線パターン 9 レンズ 10 座ぐり 11 電極 12 電極 31 凹部 32 底面 33 側壁 34 貫通孔 35 スルーホール DESCRIPTION OF SYMBOLS 1 LED chip 3 Three-dimensional molded board (MID board) 4 Adhesive 5 Conductive adhesive 6 Solder paste 7 Wiring pattern 8 Wiring pattern 9 Lens 10 Counterbore 11 Electrode 12 Electrode 31 Depression 32 Bottom surface 33 Side wall 34 Through hole 35 Through hole

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 複数のLEDチップと、該LEDチップ
の各々を収納する複数の凹部が形成された3次元成形基
板とを有し、前記LEDチップの電極面でない面が前記
凹部の底面側になるように前記LEDチップを搭載し、
隣接するLEDチップの電極間を導電性部材により接続
するようにしたことを特徴とする半導体装置。
1. A three-dimensional molded substrate having a plurality of LED chips and a plurality of recesses for accommodating each of the LED chips, wherein a surface of the LED chip that is not an electrode surface is on a bottom side of the recess. Mounting the LED chip so that
A semiconductor device wherein electrodes of adjacent LED chips are connected by a conductive member.
【請求項2】 前記凹部の側壁に貫通孔を形成し、前記
導電性部材として導電性接着剤を用い、前記貫通孔を介
して導電性接着剤により隣接するLEDチップの電極間
を接続するようにしたことを特徴とする請求項1記載の
半導体装置。
2. A through hole is formed in a side wall of the concave portion, a conductive adhesive is used as the conductive member, and electrodes of adjacent LED chips are connected by the conductive adhesive through the through hole. 2. The semiconductor device according to claim 1, wherein:
【請求項3】 前記凹部の側壁に貫通孔を形成するとと
もに、該貫通孔の内面及び前記側壁の表裏両面に配線パ
ターンを形成し、前記導電性部材として半田ペーストを
用い、前記貫通孔を介して半田ペーストにより隣接する
LEDチップの電極間を接続するようにしたことを特徴
とする請求項1記載の半導体装置。
3. A through hole is formed in a side wall of the concave portion, and a wiring pattern is formed on an inner surface of the through hole and on both front and back surfaces of the side wall, and a solder paste is used as the conductive member. 2. The semiconductor device according to claim 1, wherein electrodes of adjacent LED chips are connected by solder paste.
【請求項4】 前記LEDチップを前記凹部の底面に搭
載する際に接着剤により仮止めするようにしたことを特
徴とする請求項1乃至請求項3記載の半導体装置。
4. The semiconductor device according to claim 1, wherein said LED chip is temporarily fixed by an adhesive when said LED chip is mounted on a bottom surface of said concave portion.
【請求項5】 前記凹部の側壁と底面とが鈍角をなすよ
うにしたことを特徴とする請求項1乃至請求項4記載の
半導体装置。
5. The semiconductor device according to claim 1, wherein the side wall and the bottom surface of the recess form an obtuse angle.
【請求項6】 前記LEDチップの上面側を樹脂封止す
る際に、透明な樹脂を注入し加熱硬化させることにより
レンズを形成するようにしたことを特徴とする請求項1
乃至請求項5記載の半導体装置。
6. A lens is formed by injecting a transparent resin and curing by heating when sealing the upper surface side of the LED chip with a resin.
The semiconductor device according to claim 5.
JP4027197A 1997-02-25 1997-02-25 Semiconductor device Expired - Fee Related JP3267183B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4027197A JP3267183B2 (en) 1997-02-25 1997-02-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4027197A JP3267183B2 (en) 1997-02-25 1997-02-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH10242519A true JPH10242519A (en) 1998-09-11
JP3267183B2 JP3267183B2 (en) 2002-03-18

Family

ID=12575984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4027197A Expired - Fee Related JP3267183B2 (en) 1997-02-25 1997-02-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3267183B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6288851B1 (en) 1999-06-02 2001-09-11 Mitsubishi Denki Kabushiki Kaisha Optical semiconductor device with convergent lens
JP2005019653A (en) * 2003-06-25 2005-01-20 Matsushita Electric Works Ltd Semiconductor light emitting element and light emitting device
US8093616B2 (en) 2006-11-29 2012-01-10 Fujitsu Limited Electronic component, manufacturing method of the electronic component, electronic component assembly body, and electronic device
JP2016184714A (en) * 2015-03-27 2016-10-20 日亜化学工業株式会社 Method of manufacturing light emission device
JP2019145577A (en) * 2018-02-16 2019-08-29 京セラ株式会社 Semiconductor module and manufacturing method of semiconductor module
WO2022188468A1 (en) * 2021-03-10 2022-09-15 重庆康佳光电技术研究院有限公司 Led touch chip and manufacturing method therefor, and display device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6288851B1 (en) 1999-06-02 2001-09-11 Mitsubishi Denki Kabushiki Kaisha Optical semiconductor device with convergent lens
JP2005019653A (en) * 2003-06-25 2005-01-20 Matsushita Electric Works Ltd Semiconductor light emitting element and light emitting device
US8093616B2 (en) 2006-11-29 2012-01-10 Fujitsu Limited Electronic component, manufacturing method of the electronic component, electronic component assembly body, and electronic device
US8440481B2 (en) 2006-11-29 2013-05-14 Fujitsu Limited Manufacturing method of the electronic component
JP2016184714A (en) * 2015-03-27 2016-10-20 日亜化学工業株式会社 Method of manufacturing light emission device
JP2019145577A (en) * 2018-02-16 2019-08-29 京セラ株式会社 Semiconductor module and manufacturing method of semiconductor module
WO2022188468A1 (en) * 2021-03-10 2022-09-15 重庆康佳光电技术研究院有限公司 Led touch chip and manufacturing method therefor, and display device

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