JPH10242436A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce memory cells by forming opening parts for floating gate electrode in the element separation-formation area of a second gate area, introducing impurities to the opening parts, forming oxide films so as to bury them in the opening parts, forming the channel width direction of the element separation area in terms of self-matching and reducing steps. SOLUTION: A first polysilicon layer for the floating gate electrode 52 is formed on the silicon semiconductor substrate and the opening parts 52R are formed. Ions are implanted to the opening parts 52R and field dope impurities are introduced to a part becoming the element separation/formation area 56. Nitride films and the oxide films are formed in the opening parts 52R. Then, the oxide films are etched back with the nitride films as end points so as to form the buried oxide films 56. Then, a second polysilicon layer for a control gate electrode 53 is formed. The forming process of a field oxide film for element separation is omitted and a memory cell array can be formed. The field step and the step of the floating gate electrode 52 can be prevented from being developed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory represented by an electrically erasable EEPROM having a floating gate electrode, a flash memory (flash EEPROM) or the like. The present invention relates to a semiconductor memory device and a method for manufacturing the same.

Such a semiconductor storage device is useful as, for example, a storage device for a signal processing circuit typified by an electronic organizer, a camera, a voice recognition / storage device, and a computer.

[0003]

2. Description of the Related Art In a nonvolatile semiconductor memory device (EEPROM) that can be electrically rewritten and erased, a flash EEPROM (hereinafter abbreviated as a flash memory) has attracted attention in recent years.

[0004] In general, an EEPROM has a basic operation of erasing a single bit, whereas a flash memory has a basic operation.
The device is relatively difficult to use because the basic operation is erasing in block units. However, by adopting various technologies such as 1-bit single element technology and block erasing technology, the degree of integration equal to or higher than that of DRAM is achieved. It is attracting attention as a promising next-generation memory (specifically, ROM), and its market size is said to be immeasurable.

Regarding such flash memory technology,
Until now, various companies have proposed various semiconductor storage devices and methods for manufacturing the same.

For example, U.S. Pat. S. P. 5280446 (U
S005280446A, Title of invention: FLASH E
PROM MEMORY CIRCUIT HAVI
NGSOURCE SIDE PROGRAMMIN
G, filing date: June 8, 1992, inventor: Yueh
Y. Ma)).

FIG. 24 shows a conventional technology (USP 528).
0446) is a plan view of a memory cell structure constituting a flash EEPROM cell array disclosed in US Pat.

As shown in the plan view of the memory cell structure in FIG. 24, this flash memory has a field oxide film (LOCOS: LOCal Oxid) for separating each memory cell.
, a floating gate electrode 12, a linear control gate electrode 13 formed on the floating gate electrode 12 via an insulating film, and a laminated portion of the floating gate electrode 12 and the control gate electrode 13. 12
(First gate region) and region 19 (second region) on the semiconductor substrate.
(A gate region), a line-shaped select gate electrode 20 formed via each insulating film, and a control gate electrode 1
And regions (source / drain) 14 and 15 for forming a semiconductor substrate diffusion layer formed in parallel to 3.

The source diffusion region 15 which is one of the regions (source / drain) 14 and 15 for forming the semiconductor substrate diffusion layer is formed offset from the control gate electrode 13 by the second gate region. I have. Here, reference numeral 30 in FIG. 24 indicates a semiconductor substrate active region (region other than LOCOS).

By adopting such a memory cell structure, a semiconductor substrate channel region sandwiched between a first gate region (a predetermined region in the floating gate electrode 12) and a second gate region (a region indicated by 19 in FIG. 24). Of channel hot electrons from the semiconductor device to the floating gate electrode 12 (So
It is disclosed that high efficiency of electron injection from the channel region of the semiconductor substrate to the floating gate electrode 12 can be realized as a result of enabling rc (Side Side Injection: SSI).

Further, by controlling the control gate electrode 13 and the selection gate electrode 20, a memory cell can be selected in a matrix. Therefore, the memory cell can be selected through the regions (source / drain) 14, 15 where the semiconductor substrate diffusion layer is formed. It is disclosed that adjacent memory cells can share a source diffusion layer and a drain diffusion layer, and as a result, a cell array area can be reduced (in other words, an integration degree can be improved).

[0012]

However, in the memory cell structure of the prior art, since the field oxide film (LOCOS) 10 is formed for element isolation, the floating gate electrode 12, the control gate electrode 13, and the select gate are formed. Electrode 2
There is a technical problem that an alignment margin is required for the field oxide film 10 when three electrodes 0 and contact holes are formed. As a result, there is a technical problem that it is difficult to miniaturize the memory cell.

Further, in the conventional memory cell structure, a resolution step and a dimensional defect of the control gate electrode 13 and the select gate electrode 20 occur due to a field step and a step of the floating gate electrode 12. As a result, there is a technical problem that it is difficult to miniaturize the memory cell.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a conventional problem. In particular, only a rectangular element isolation formation region sandwiched between regions for forming respective memory cells is used for a floating gate electrode. An opening forming step of forming an opening by performing opening processing for removing the first polysilicon layer; an opening impurity introducing step of introducing a field-doped impurity of the same conductivity type as the semiconductor substrate into the opening; And / or having an opening filling step of filling the opening with a single-layer film or a laminated film formed using a nitride film,
The channel width direction of the element isolation formation region is formed in a self-aligned manner, or the first region for the floating gate electrode is formed in a stripe-shaped region including the element isolation formation region adjacent to the semiconductor substrate diffusion layer. An opening forming step of forming an opening of the polysilicon layer, an opening impurity introducing step of introducing a field doping impurity of the same conductivity type as the semiconductor substrate into the opening, and formation using an oxide film and / or a nitride film Having an opening embedding step of embedding an opening by using a single-layer film or a laminated film that has been formed, the channel width direction of the element isolation formation region is formed in a self-aligned manner, or the line of the drain diffusion layer is sandwiched. An opening forming step of forming an opening of the first polysilicon layer for a floating gate electrode in a rectangular area including a pair of adjacent element isolation forming areas; Opening impurity introducing step of introducing field doping impurities of the same conductivity type as the body substrate, and opening burying step of burying the opening with a single-layer film or a laminated film formed using an oxide film and / or a nitride film It is an object of the present invention to form the element isolation formation region in the channel width direction in a self-aligned manner.

In addition, the step of processing the insulating film buried in the opening into a square shape and the step of introducing impurities into the substrate diffusion layer are performed by using the same mask, so that the channel length direction of the element isolation region is formed in a self-aligned manner. In other words, an object is to form a substrate diffusion layer line in a self-aligned manner. At this time, the fact that the number of mask steps can be reduced once is also an important effect, which directly leads to cost reduction.

Further, by forming the channel width direction of the element isolation formation region in a self-aligned manner, the second gate region can be formed in a self-aligned manner with the gate length of the second gate region without a field oxide film for element isolation (LOCOS). A memory cell array can be formed, which not only eliminates the need for an alignment margin between layers, but also leads to the avoidance of field steps and steps of floating gate electrodes, thereby further reducing the cell area of memory cells. As a result, it is an object to significantly reduce the memory area (high integration).

It is another object of the present invention to prevent a resolution defect and a dimensional defect (this phenomenon is called halation) of a control gate electrode and a selection gate electrode at the time of photo development, which are caused by a field step or the like. I have.

In addition, it is also possible to use a method of forming a gate length of the second gate region in a self-aligned manner (a method using a gate sidewall) while enabling self-alignment of the element isolation region. By doing so, it is excessive to further reduce the memory area.

[0019]

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising the second gate region. Area 71 for forming each of the memory cells
An opening 52R forming step of forming an opening 52R by performing an opening treatment for removing the first polysilicon layer for the floating gate electrode 52 only on the rectangular element isolation formation region 56 interposed therebetween; 52R impurity introducing step of introducing a field dope impurity of the same conductivity type as that of the semiconductor substrate, and an opening 52R embedding step of embedding the opening 52R using a single-layer film or a laminated film formed using an oxide film. Thus, a method for manufacturing a semiconductor memory device 70 in which a channel width direction of an element isolation region is formed in a self-aligned manner and a step is reduced.

According to the first aspect of the present invention, when the gate length L2 of the second gate region 49 is self-aligned,
Since the memory cell array 72 can be formed by omitting the step of forming the element isolation field oxide film 10, the alignment margin between the layers can be eliminated, and the alignment margin between the rectangular element isolation formation region 56 and the floating gate electrode 52 can be eliminated. Can be reduced.

The rectangular element isolation formation region 56 is
Buried oxide film 56 in opening 52R of polysilicon layer
The rounding of the square element isolation formation region 56 due to the influence of the conventional bird's beak (the phenomenon that the square element isolation formation region 56 is rounded through a photographic process and an oxidation process) is reduced. Therefore, the alignment margin between the rectangular element isolation formation region 56 and the control gate electrode 53 and the selection gate electrode 60 can be reduced.

Since the end surface of the rectangular element isolation formation region 56 is formed by etching, the rounding of the square element isolation formation region 56 can be practically avoided.
The alignment margin between the rectangular element isolation formation region 56 and the control gate electrode 53 can be further reduced.

The select gate length L2 of the second gate region 49 of the memory cell array 72 can be formed in a self-aligned manner while keeping the alignment margin reduced.

Since the alignment margin can be reduced in this manner, the cell area of the memory cell 71 can be further reduced, and as a result, the memory area can be significantly reduced (high integration). become.

The memory cell array 72 can be formed by omitting the step of forming the field oxide film 10 for element isolation. As a result, it is possible to avoid the occurrence of a field step or a step of the floating gate electrode 52.

Further, the control gate electrode 53 and the selection gate electrode 6 at the time of photo-developing, which are generated due to a field step or the like.
It is possible to avoid the halation phenomenon which causes the resolution failure and the dimensional failure of 0.

According to a second aspect of the present invention, which has been made to solve the above-mentioned problems, the present invention relates to a method of manufacturing a semiconductor memory device 70, comprising the steps of:
An opening 52R forming step of forming an opening 52R by performing an opening treatment for removing the first polysilicon layer for the floating gate electrode 52 only on the rectangular element isolation formation region 56 interposed therebetween; 52R impurity introducing step of introducing a field dope impurity of the same conductivity type as that of the semiconductor substrate, and an opening 52R embedding step of embedding the opening 52R using a single-layer film or a laminated film formed using a nitride film Thus, a method for manufacturing a semiconductor memory device 70 in which a channel width direction of an element isolation region is formed in a self-aligned manner and a step is reduced.

According to the second aspect of the present invention, the gate length L2 of the second gate region 49 is formed in a self-aligned manner.
Since the memory cell array 72 can be formed by omitting the step of forming the element isolation field oxide film 10, the alignment margin between the layers can be eliminated, and the alignment margin between the rectangular element isolation formation region 56 and the floating gate electrode 52 can be eliminated. Can be reduced.

By performing such an opening filling step, the rounding phenomenon of the square element isolation formation region 56 due to the influence of the conventional bird's beak (the square element isolation formation region 56 is used for the photographic process and the oxidation process). (A phenomenon of being rounded after passing through) is reduced, so that an alignment margin between the rectangular element isolation formation region 56 and the control gate electrode 53 and the selection gate electrode 60 can be reduced.

Since the end face of the rectangular element isolation formation region 56 is formed by etching, the rounding of the square element isolation formation region 56 can be practically avoided.
The alignment margin between the rectangular element isolation formation region 56 and the control gate electrode 53 can be further reduced.

The select gate length L2 of the second gate region 49 of the memory cell array 72 can be formed in a self-aligned manner while keeping the alignment margin reduced.

Since the alignment margin can be reduced in this manner, the cell area of the memory cell 71 can be further reduced, and as a result, the memory area can be significantly reduced (high integration). become.

Further, since the memory cell array 72 can be formed by omitting the step of forming the field oxide film 10 for element isolation, generation of a field step and a step of the floating gate electrode 52 can be avoided.

Further, the control gate electrode 53 and the selection gate electrode 6 at the time of photo development generated due to a field step or the like.
It is possible to avoid the halation phenomenon which causes the resolution failure and the dimensional failure of 0.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising the steps of: forming a rectangular shape sandwiched between regions forming memory cells; An opening 52R forming step of forming an opening 52R by performing an opening process for removing the first polysilicon layer for the floating gate electrode 52 only on the element isolation formation region 56; and forming the opening 52R with the same conductivity type as that of the semiconductor substrate. 52R for introducing a field dope impurity, and an opening 52R for filling the opening 52R using a single-layer film or a laminated film formed using an oxide film and a nitride film.
This is a method for manufacturing a semiconductor memory device 70 that includes an R embedding step, thereby forming a channel width direction of an element isolation region in a self-aligned manner, and reducing a step.

According to the invention of claim 3, according to claim 2,
In addition to the effects described in (1), by executing such an opening filling step, the rounding phenomenon of the square element isolation formation region 56 due to the influence of the conventional bird's beak (the square element isolation formation region 56 is Since the process and the oxidation process are rounded, the alignment margin between the rectangular element isolation formation region 56 and the control gate electrode 53 and the select gate electrode 60 can be reduced.

According to a fourth aspect of the present invention, which is made according to the present invention to solve the above-mentioned problems, there is provided a method of manufacturing a semiconductor memory device 70, comprising the steps of:
The floating gate electrode 52 is formed in a stripe-shaped region constituted by element isolation formation regions 56 adjacent to each other with the interposition of the floating gate electrodes 52 and 55 therebetween.
Forming an opening 52R of the first polysilicon layer for use in the first polysilicon layer, an impurity introducing a field doping impurity of the same conductivity type as that of the semiconductor substrate into the opening 52R, A step of burying the opening 52R using a single-layer film or a laminated film formed using a film, thereby forming a channel width direction of the element isolation region in a self-aligned manner and reducing a step. Is a method of manufacturing a semiconductor memory device 70 that executes the following.

According to the invention set forth in claim 4, according to claim 3,
The same effect as the effect described in (1) is obtained.

According to a fifth aspect of the present invention for solving the above-mentioned problems, a method of manufacturing a semiconductor memory device 70 comprises a method of forming a semiconductor substrate diffusion layer with regions 54 and 55 interposed therebetween. The floating gate electrode 5 is formed in a stripe-shaped region composed of adjacent element isolation formation regions 56.
An opening 52R for forming an opening 52R of the first polysilicon layer for the second step; an opening 52R for introducing an impurity having the same conductivity type as that of the semiconductor substrate into the opening 52R; An opening 52R embedding step of embedding the opening 52R using a single-layer film or a laminated film formed using a nitride film,
The channel width direction of the element isolation region is formed in a self-aligned manner,
In addition, this is a method for manufacturing a semiconductor memory device 70 that executes step reduction.

According to the fifth aspect of the present invention, when the gate length L2 of the second gate region 49 is self-aligned,
Since the memory cell array 72 can be formed by omitting the step of forming the field oxide film 10 for element isolation, an alignment margin between the layers can be eliminated, and the alignment between the element isolation formation region 56 and the floating gate electrode 52 adjacent to each other is sandwiched. The margin can be reduced.

By performing such an opening filling step, a rounding phenomenon of the element isolation formation regions 56 adjacent to each other due to the influence of the conventional bird's beak (the element separation formation regions 56 adjacent to each other is formed by a photographic process and an oxidation process). Since the phenomenon of rounding through the process is reduced, the alignment margin between the element isolation formation region 56 and the control gate electrode 53 and the select gate electrode 60 that are adjacent to each other can be reduced.

According to a sixth aspect of the present invention, there is provided a method for manufacturing the semiconductor memory device 70, wherein the regions 54, 55 for forming the semiconductor substrate diffusion layer are provided. Forming an opening 52R of the first polysilicon layer for the floating gate electrode 52 in a stripe-shaped region composed of element isolation formation regions 56 adjacent to each other with the opening interposed therebetween; 52R for introducing a field dope impurity of the same conductivity type as that of the semiconductor substrate, and an opening for burying the opening 52R using a single-layer film or a laminated film formed using an oxide film and a nitride film. 6. A method according to claim 1, further comprising: a 52R burying step; and a step of forming the element isolation formation region 56 in a self-alignment manner to reduce a step. It is a manufacturing method of the semiconductor memory device 70 according to any one.

According to the invention described in claim 6, according to claim 5,
The same effect as the effect described in (1) is obtained.

According to a seventh aspect of the present invention, which has been made to solve the above problem, in the method of manufacturing a semiconductor memory device according to any one of the first to sixth aspects, the shape of the stripe is changed. Element formation region 56 having
Forming the semiconductor substrate diffusion layer, forming the semiconductor substrate diffusion layer, removing the element isolation insulating film in the regions 54 and 55 where the semiconductor substrate diffusion layer is to be formed, and forming the semiconductor substrate diffusion layer. A semiconductor substrate diffusion layer forming step of introducing impurities for performing the element isolation insulating film removing step and the semiconductor substrate diffusion layer forming step by using the same mask. This is a method for manufacturing a semiconductor memory device 70 in which 56 channel length directions are formed in a self-aligned manner.

According to the invention described in claim 7, according to claim 1 of the present invention,
In addition to the effects described in any one of (1) to (6), in addition to the self-aligned formation of the gate length L2 of the second gate region 49,
Since the memory cell array 72 can be formed by omitting the step of forming the field oxide film 10 for element isolation, an alignment margin between the layers can be eliminated, and the alignment between the element isolation formation region 56 having a stripe shape and the floating gate electrode 52 can be eliminated. The margin can be reduced.

By performing such an opening filling step, the element isolation formation region 56 having a stripe shape due to the influence of the conventional bird's beak is rounded (the element isolation formation region 56 sandwiched between the photolithography process and the oxidation process). Since the phenomenon of rounding through the process is reduced, the alignment margin between the element isolation formation region 56 having a stripe shape, the control gate electrode 53, and the select gate electrode 60 can be reduced.

The invention according to claim 8, which has been made by the present invention to solve the above problem, is a method for manufacturing a semiconductor memory device 70, comprising a pair of element isolation formations adjacent to each other across a line of a drain diffusion layer. Forming an opening 52R for forming the opening 52R of the first polysilicon layer for the floating gate electrode 52 in a rectangular region including the region 56, and forming a field dope of the same conductivity type as that of the semiconductor substrate in the opening 52R. An opening 52R for introducing an impurity, and an opening 52R burying step for burying the opening 52R using a single-layer film or a laminated film formed using an oxide film are included, so that an element isolation region can be formed. This is a method for manufacturing a semiconductor memory device 70 in which the channel width direction is formed in a self-aligned manner and the step is reduced.

According to the eighth aspect of the present invention, by performing such an opening filling process, the rectangular element isolation formation region 5 due to the influence of the conventional bird's beak and the like can be obtained.
6 (a phenomenon in which the rectangular element isolation formation region 56 is rounded through a photolithography process and an oxidation step) is reduced, so that the rectangular element isolation formation region 56, the control gate electrode 53, and the selection gate electrode 60 are reduced. The alignment margin between them can be reduced.

Since the end face of the rectangular element isolation formation region 56 is formed by etching, the rounding of the rectangular element isolation formation region 56 can be practically avoided. The alignment margin between the gate electrodes 53 can be further reduced.

The select gate length L2 of the second gate region 49 of the memory cell array 72 can be formed in a self-aligned manner while keeping the alignment margin reduced.

Since the alignment margin can be reduced in this manner, the cell area of the memory cell 71 can be further reduced, and as a result, the memory area can be greatly reduced (high integration). become.

The memory cell array 72 can be formed by omitting the step of forming the field oxide film 10 for element isolation. As a result, it is possible to avoid the occurrence of a field step or a step of the floating gate electrode 52.

Further, the control gate electrode 53 and the selection gate electrode 6 at the time of photo-developing, which are generated due to a field step or the like.
It is possible to avoid the halation phenomenon which causes the resolution failure and the dimensional failure of 0.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising the steps of: forming a pair of element isolations adjacent to each other with a drain diffusion layer line interposed therebetween; Forming an opening 52R for forming the opening 52R of the first polysilicon layer for the floating gate electrode 52 in a rectangular region including the region 56, and forming a field dope of the same conductivity type as that of the semiconductor substrate in the opening 52R. An opening 52R impurity introducing step for introducing impurities, an opening 52R impurity introducing step for introducing a field doping impurity of the same conductivity type as that of the semiconductor substrate into the opening 52R, and a single-layer film formed using a nitride film Or a step of burying the opening 52R using a laminated film to embed the opening 52R, whereby the channel width direction of the element isolation region is self-aligned. Formed in, and a method of manufacturing a semiconductor memory device 70 to execute the step height reduction.

According to the invention of claim 9, according to claim 8,
The same effect as the effect described in (1) is obtained.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising the steps of: forming a pair of elements adjacent to each other across a line of a drain diffusion layer; A step of forming an opening 52R of the first polysilicon layer for the floating gate electrode 52 in a rectangular area including an isolation formation area 56; and forming the opening 52R in the opening 52R with the same conductivity type as a semiconductor substrate. An opening 52R impurity introduction step for introducing a field dope impurity and an opening 52R filling step for filling the opening 52R using a single-layer film or a laminated film formed using an oxide film and a nitride film are provided. A method of manufacturing a semiconductor memory device 70 in which a channel width direction of an element isolation region is formed in a self-aligned manner and a step is reduced.

According to the tenth aspect, the same effect as that of the eighth aspect is obtained.

In order to solve the above-mentioned problems, the present invention according to claim 11 has been made according to claims 6, 7, 8, and 1.
14. In the method of manufacturing the semiconductor memory device 70 according to any one of 2, 13, 14, 15, and 13, the step of forming the element isolation formation region 56 includes a step of forming the element isolation formation region 56 in a self-aligned manner. (1) A self-alignment forming step, and a thick side wall 61 is formed on the line of the control gate electrode 53, and impurity ions are implanted into a part to be the source region in a self-aligned manner, thereby self-aligning the second gate region 49. This is a method for manufacturing a semiconductor memory device 70 that includes a second self-alignment forming step of forming a semiconductor device.

According to the eleventh aspect, in addition to the effects described in any one of the sixth, seventh, eighth, twelfth, thirteenth, thirteenth, and thirteenth aspects, the second gate region 49 Along with the self-aligning formation of the gate length L2, the memory cell array 72 can be formed by omitting the step of forming the field oxide film 10 for element isolation. Formation area 56
-The alignment margin between the floating gate electrodes 52 can be reduced.

In addition, the select gate length L2 of the second gate region 49 of the memory cell array 72 can be formed in a self-aligned manner while keeping the alignment margin reduced.

Since the alignment margin can be reduced in this manner, the cell area of the memory cell 71 can be further reduced, and as a result, the memory area can be significantly reduced (high integration). become.

The memory cell array 72 can be formed by omitting the step of forming the field oxide film 10 for element isolation. As a result, it is possible to avoid the occurrence of a field step or a step of the floating gate electrode 52.

Further, the control gate electrode 53 and the selection gate electrode 6 at the time of photo development generated due to a field step or the like.
It is possible to avoid the halation phenomenon which causes the resolution failure and the dimensional failure of 0.

According to a twelfth aspect of the present invention for solving the above-mentioned problems, in the method according to the twelfth aspect, prior to performing the step of forming the opening 52R, a step of forming a first nitride film layer; Forming the opening 52R in the first nitride film layer and the first polysilicon layer, and １ ／ or more of a shorter dimension of the width or the length of the opening 52R in the first polysilicon layer. A buried oxide film forming step of forming a buried oxide film having a thickness of 3 nm, and an etch-back step of etching back the oxide film with the first nitride film layer as an end point. 12. The method of manufacturing a semiconductor memory device 70 according to claim 11, wherein an insulating film for element isolation is buried in said opening 52R.

According to the twelfth aspect, the same effect as the eleventh aspect can be obtained.

According to a thirteenth aspect of the present invention for solving the above-mentioned problem, according to the eleventh aspect of the present invention, in the method of manufacturing a semiconductor memory device according to the eleventh aspect, an opening 52R of the first polysilicon layer is formed. Prior to formation, a step of forming a first nitride film layer, a step of forming the opening 52R in the first nitride film layer and the first polysilicon layer, and an opening of the first polysilicon layer later A buried oxide film forming step of forming a CVD oxide film having a thickness equal to or more than の of the shorter dimension of the width or the length of the portion 52R, and the CVD oxidation using the first nitride film layer as an end point. A method of manufacturing a semiconductor memory device 70 including an etch-back step of etching back a film to bury an isolation insulating film in an opening 52R of the first polysilicon layer.

According to the thirteenth aspect of the present invention, in addition to the effect of the eleventh aspect, by performing such an opening filling step, the element isolation formation region 56 due to the influence of the conventional bird's beak and the like can be obtained. (A phenomenon in which the element isolation formation region 56 is rounded through a photographic process and an oxidation process) is reduced, so that the alignment margin between the element isolation formation region 56 and the control gate electrode 53 and the selection gate electrode 60 is reduced. Will be able to do it.

Since the end surface of the element isolation formation region 56 is formed by etching, the rounding of the element isolation formation region 56 can be practically avoided. Therefore, the alignment margin between the element isolation formation region 56 and the control gate electrode 53 is further increased. A further reduction can be realized.

The select gate length L2 of the second gate region 49 of the memory cell array 72 can be formed in a self-aligned manner while the reduction of the alignment margin is maintained.

Since the alignment margin can be reduced in this manner, the cell area of the memory cell 71 can be further reduced, and as a result, the memory area can be significantly reduced (high integration). become.

According to a fourteenth aspect of the present invention, which is achieved by the present invention to solve the above problem, in the method of manufacturing a semiconductor memory device according to any one of the first to twelfth aspects, the first polycrystalline semiconductor memory device comprises: Forming a thin second nitride film layer after the formation of the opening 52R in the silicon layer; and forming a film having at least half the shorter dimension of the width or the length of the opening 52R in the first polysilicon layer. A step of forming a buried oxide film having a thick buried oxide film; and an etch back step of etching back the oxide film using the second nitride film layer as an end point to form an opening in the first polysilicon layer. This is a method for manufacturing a semiconductor memory device 70 in which an insulating film for element isolation is embedded in a portion 52R.

According to the fourteenth aspect of the present invention, in addition to the effect of any one of the first to twelfth aspects, the element isolation formation region 5 formed by such a CVD oxide film is provided.
No. 6 has a smaller rounded corner than the LOCOS 10 described above. Therefore, by performing the opening filling step using a CVD oxide film having an optimum film thickness, the element isolation formation region due to the influence of the conventional bird's beak and the like is obtained. Since a rounding phenomenon of the element isolation region 56 (a phenomenon in which the element isolation formation region 56 is rounded through a photographic process and an oxidation process) is reduced, the alignment margin between the element isolation formation region 56 and the control gate electrode 53 and the selection gate electrode 60 is reduced. Will be able to

Further, as a result of reducing the rounding phenomenon, the alignment margin between the element isolation formation region 56 and the MD resist mask 80 can be reduced.

When the end surface of the element isolation formation region 56 is formed by etching using the first nitride film layer as an end point, the element isolation formation region 56 can be effectively prevented from being rounded. And the control margin between the control gate electrode 53 and the control gate electrode 53 can be further reduced.

The selection gate length L2 of the second gate region 49 of the memory cell array 72 can be formed in a self-aligned manner while maintaining the reduction of the alignment margin.

Since the alignment margin can be reduced in this manner, the cell area of the memory cell 71 can be further reduced, and as a result, the memory area can be significantly reduced (high integration). become.

According to a fifteenth aspect of the present invention for solving the above-mentioned problem, the first polycrystalline semiconductor memory device according to any one of the first to twelfth aspects, further comprises: Forming a thin second nitride film layer after the formation of the opening 52R in the silicon layer; and forming a film having at least half the shorter dimension of the width or the length of the opening 52R in the first polysilicon layer. A buried oxide film forming step of forming a thick CVD oxide film; and an etchback step of etching back the CVD oxide film using the second nitride film layer as an end point.
13. The method of manufacturing a semiconductor memory device 70 according to claim 1, wherein an insulating film for element isolation is buried in the opening 52R of the polysilicon layer.

According to the fifteenth aspect, in addition to the effects of the first aspect, the second aspect
By forming a thin oxide film before forming the nitride film layer,
This makes it possible to reduce memory reliability and memory characteristic variations.

Further, by performing the opening filling step using the CVD oxide film having such an optimum film thickness, the rounding phenomenon of the element isolation formation region 56 due to the influence of the conventional bird's beak (the element isolation formation region) is performed. The phenomenon that the element 56 is rounded through a photolithography step and an oxidation step) is reduced, so that the alignment margin between the element isolation formation region 56 and the control gate electrode 53 and the selection gate electrode 60 can be reduced.

Further, since the end surface of the element isolation formation region 56 is formed by etching using the second nitride film layer as an end point, the rounding of the element isolation formation region 56 can be practically avoided. And the control margin between the control gate electrode 53 and the control gate electrode 53 can be further reduced.

The second gate region 4 of the memory cell array 72 is maintained in a state where the reduction of the alignment margin is maintained.
Nine select gate lengths L2 can be formed in a self-aligned manner.

Since the alignment margin can be reduced in this manner, the cell area of memory cell 71 can be further reduced, and as a result, the memory area can be significantly reduced (high integration). become.

[0083]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of the present invention will be described below with reference to the drawings.

The present semiconductor memory device 70 has an electrically erasable memory cell array 72 using the floating gate electrode 52.
Is a non-volatile semiconductor storage device typified by an EEPROM, a flash memory (flash EEPROM), or the like, on which is formed.

Such a semiconductor memory device 70 is, for example,
It is considered to be useful as a storage device of a signal processing circuit represented by an electronic organizer, a camera, a voice recognition / storage device, a computer, and the like.

The memory cell array 72 formed in the semiconductor memory device 70 has a floating gate electrode 52 formed on a semiconductor substrate such as silicon via a tunnel oxide film 48, and an interpoly insulation on the floating gate electrode 52. Line-shaped control gate electrode 53 covering through film 57
And second insulating film 58 and 61 formed above and on the side surfaces of first gate region 52 (53), which is a laminated portion of floating gate electrode 52 and control gate electrode 53, and part of the semiconductor substrate. A line-shaped select gate electrode 60 having a gate region formed through a gate oxide film 49 and formed in a direction perpendicular to the control gate electrode 53;
A region 5 in which a line-shaped semiconductor substrate diffusion layer is formed alternately and in parallel with the control gate electrode 53.
4, 55.

The region 5 where the semiconductor substrate diffusion layer is to be formed
4 and 55, the source diffusion layer line 55 is the first
The structure is such that the gate region 52 (53) is offset (hereinafter, this offset portion, that is, the portion where the gate oxide film 49 is formed is defined as a second region).

The present semiconductor memory device 70 uses the control gate electrode 53 and the select gate electrode 60 in the memory cell array 72 having such a configuration to
1 has a function of selecting a matrix.

According to the embodiment of the semiconductor memory device 70 having such a configuration, the memory cell array 72 can be formed without forming the field oxide film 10 for element isolation (hereinafter, referred to as LOCOS). Element isolation formation region 56-floating gate electrode 52, element isolation formation region 56-
The substrate diffusion layer 55 and the alignment margin between the element isolation formation region 56 and the control gate 53 can be eliminated.

By eliminating the alignment margin in this way, the cell area of the memory cell 71 can be further reduced, and as a result, the memory area can be significantly reduced (high integration). become.

As a result of forming the memory cell array 72 without forming the field oxide film 10 for element isolation, it is possible to avoid the occurrence of a field step or a step of the floating gate electrode 52. Accordingly, it is possible to avoid a halation phenomenon which is caused by a field step or the like and causes a resolution defect or a dimensional defect of the control gate electrode 53 or the select gate electrode 60 at the time of photo development. Furthermore, the cell area can be further reduced by using the self-alignment method of forming the gate length L2 of the second gate region 49 together.

Next, a first embodiment of a method for manufacturing the above-described semiconductor memory device 70 will be described.

The manufacturing method according to the first embodiment includes an opening forming step, an opening impurity introducing step, and an opening filling step.

In the step of forming the opening, the first gate region 52 is formed.
(53) and a square element isolation formation region 5 sandwiched between each memory cell region 71 constituted by the second gate region 49
This is a step of forming an opening 52R by performing an opening process for removing the first polysilicon layer for the floating gate electrode 52 only on the upper surface 6.

The opening impurity introducing step performed after the opening forming step is a step of introducing a field doping impurity of the same conductivity type as that of the semiconductor substrate into the opening 52R.

The opening filling step performed after the opening impurity introducing step forms a single layer film or a laminated film formed using an oxide film, and etches it back to form the opening 5.
This is a step of embedding an oxide film in 2R.

Further, in the step of burying the opening, a step of forming a thin first nitride film layer (a step of forming a nitride film layer) before forming the opening 52R of the first polysilicon layer or a step of forming an opening in the first polysilicon layer is performed. Forming a thin second nitride film layer after the formation of the portion 52R (nitride film layer forming step); and forming at least one half of the width or the length of the opening 52R of the first polysilicon layer, whichever is shorter. A buried oxide film forming step of forming a CVD oxide film having a thickness, and a first nitride film layer or a second nitride film layer.
An etch-back step of etching back the CVD oxide film using the nitride film layer as an end point.

Also, by performing an opening filling step using a CVD oxide film having such an optimum film thickness to form an element isolation region, a bird's beak is required as compared with a conventional element isolation formation step by LOCOS. Of the element isolation formation region 56 (a phenomenon in which the element isolation formation region 56 is more rounded through an oxidation process) due to the above-described process, the element isolation formation region 56, the floating gate 52, the substrate diffusion layer 55, and the The alignment margin between the gate electrodes 60 can be eliminated.

Further, by performing the CVD film etching process using the first nitride film layer or the second nitride film layer as an end point, a buried insulating film having a small step can be formed.

Since the alignment margin can be eliminated in this manner, the cell area of the memory cell 71 can be further reduced, and as a result, the memory area can be significantly reduced (high integration). become.

A single-layer film or a laminated film formed by using a nitride film instead of the oxide film may be formed, and this may be etched back to fill the opening 52R. Alternatively, a single-layer film or a stacked film formed using an oxide film and a nitride film may be formed, and this may be etched back to fill the opening 52R.

Next, a specific example of the first embodiment of the manufacturing method will be described with reference to the drawings.

FIG. 1 illustrates the first, second, and third aspects of the present invention. In the method of manufacturing a semiconductor memory device according to the first embodiment, a photolithography technique (resist coating and development) and dry etching are used. FIG. 5 is a plan view of a memory cell structure for explaining an opening forming step performed using a technique.

First, a tunnel oxide film 48 is formed on a silicon semiconductor substrate on which a well has been formed or the like using a known appropriate method, and a first polysilicon layer for a floating gate electrode 52 is formed.

Next, the first photolithography technique (such as resist coating and development) and dry etching
An opening process is performed on the polysilicon layer as shown in FIG. 1 (opening forming step).

Subsequently, impurity ions of the same conductivity type as that of the semiconductor substrate are implanted to form openings 52 in the first polysilicon layer.
R, that is, a field dope impurity is introduced in a self-aligned manner into a portion to be the element isolation formation region 56 (opening impurity introduction step).

In FIG. 1 to FIG. 7, reference numeral 52 denotes a portion where the first polysilicon layer remains, and 52R denotes a portion where the first polysilicon layer is subjected to an opening (removal) process.

Next, a thin nitride film layer used as an end point in the buried oxide film etch back step is formed. This film may be several tens of nanometers.

Next, the opening 52R of the first polysilicon layer is formed.
Next, a CVD oxide film having a thickness equal to or more than の of the shorter dimension of the width of the opening 52R or the length of the opening 52R is formed (nitride film layer forming step and buried oxide film forming step).

Here, instead of using the second nitride film layer, a first nitride film layer may be used. In this case, the first nitride film layer is formed before the opening forming step. The film thickness is the second
It may be about the same as nitriding winding.

FIG. 2 is a block diagram showing a second embodiment of the present invention.
2, 13, 14, and 15 are plan views of a memory cell structure for explaining a step of burying an opening for forming a buried oxide film in the method for manufacturing a semiconductor memory device according to the first embodiment. is there.

Next, the CVD oxide film is etched back using the first or second nitride film layer previously formed below the CVD oxide film as an end point (etchback step), and the buried oxide film is formed as shown in FIG. A film 56 is formed (step of embedding an insulating film for element isolation).

In this embodiment, the alignment margin between the element isolation formation region 56 and the floating gate electrode 52 can be reduced as described above.

Here, the case where the first nitride film layer is formed before the opening of the first polysilicon layer corresponds to claims 12 and 13, and a thin second nitride film layer is formed after the opening of the first polysilicon layer. This case corresponds to claims 14 and 15.

A thin oxide film layer is provided below the first nitride film layer or the second nitride film layer, and the thin oxide film layer and the nitride film layer are connected to the second gate region which is a part of the interpoly ONO film 57. However, since these nitride film layers (the first nitride film layer and the second nitride film layer) are used as end points of the CVD oxide film etch back, it is difficult to control the etching damage and the film thickness. Therefore, it is desirable to remove and re-form at least once.

In the case where the first nitride film layer is used, it is preferable to perform a light oxidation treatment before forming the buried CVD oxide film.
Memory reliability is improved. This is because the side surface of the opening (side wall of the opening) of the first polysilicon layer is not directly exposed to the CVD oxide film, and is sometimes effective in improving memory retention characteristics.

In the case where the second nitride film layer is used, it has been found that forming a thin oxide film before forming the second nitride film layer has the effect of reducing the memory reliability and the variation in memory characteristics. It is considered that the oxidation treatment is more effective.

As described above, in this embodiment, it is preferable to perform light oxidation treatment after the opening of the first polysilicon layer, but it is considered that gate bird's beak occurs when the degree of oxidation increases (that is, at the gate edge). Tunnel oxide film 48
It is necessary to pay attention to this, since it will affect the writing characteristics and the erasing characteristics.

As described above, after forming the buried oxide film 56, an interpoly insulating film 57 (such as an interpoly ONO film) is formed.

Next, a second polysilicon layer for the control gate electrode 53 is formed, and an insulating film 58 for insulation from the control gate electrode 53 is formed.

FIG. 3 is a memory cell structure for explaining a step of forming a control gate electrode line by using photolithography and etching in the method of manufacturing a semiconductor memory device according to the first embodiment of the present invention. FIG.

Next, as shown in FIG. 3, the control gate electrode 53 is formed by using a known photoengraving technique and etching technique.
Is formed.

As shown in this embodiment, embedded CVD
The element isolation formation region 56 formed by the oxide film
Since the corner rounding is smaller than that of the COS 10, the alignment margin between the element isolation formation region 56 and the control gate electrode 53 can be reduced as compared with the related art.

FIG. 4 shows a method of manufacturing a semiconductor memory device according to the first embodiment of the present invention. In the step of implanting impurity ions for a diffusion layer (for MD) through a resist mask step in photolithography, FIG. 4 is a plan view of a memory cell structure for explaining a state in which lines are aligned in a self-aligned manner at control gate electrode ends and source lines are aligned using a mask resist.

Next, through a known photoengraving technique (resist mask 80), as shown in FIG.
Impurity ions). In this case, the drain line 54 is the control gate electrode 53 (electrode width = L1).
The ends are self-aligned and the source lines 55 are aligned with the mask resist 80.

In this case, similarly, since the corners of the element isolation formation region 56 are considered to be less rounded than in the conventional case, the element isolation formation region 56 and the MD resist mask 8
The alignment margin between zeros can be reduced.

FIG. 5 is a plan view of a memory cell structure formed by using the method for manufacturing a semiconductor memory device according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view of the SS ′ element of the memory cell structure of FIG. FIG. 7 is a cross-sectional view of the CC ′ element of the memory cell structure of FIG.

Next, an insulating film sidewall 61 is formed on the side surface of the control gate electrode 53 (the side surface including the portion where the floating gate electrode 52 is stacked) (see FIGS. 5 and 6).

As a result, the insulation between the control gate electrode 53 and the select gate electrode 60 is ensured, and the second gate region (49 in the cross section of the SS ′ element in FIG. 6) and the floating gate electrode 52 (the The gap length (the thickness of the side wall 61 in the cross-sectional view of the SS ′ element in FIG. 6) with the gate region (one gate region 48) can be obtained with good controllability. Further, the gap length (the thickness of the side wall 61) can be formed with good control, so that the source side injection, which is the process of injecting electrons from the source side to the floating gate electrode 52, can be performed with high efficiency.

The gap length is considered to be an important dimension for obtaining highly efficient source side injection (injection of electrons from the source side to the floating gate electrode 52) which is a feature of the semiconductor memory device 70. It is preferable to set the thickness to about 10 nm to 100 nm.

The method of forming the insulating film sidewall 61 is different from the gist of the present invention, and therefore the description is omitted. However, the dry etching back of the oxide film is performed in the second gate region (49 in FIG. 6). It is considered necessary to consider the process so as not to be damaged by the above.

Next, a sectional view of the SS ′ element of FIG. 6 and FIG.
As shown in the cross-sectional view of the element CC ′, a gate oxide film 49 is formed in the second gate region.
Forming a third polysilicon layer.

Next, a line 60 of a select gate electrode is formed by using a known photolithography technique and etching technique, and FIG.
The memory structure as shown in FIG.

The following processes are out of the scope of the present embodiment, and will not be described.

According to the first embodiment of such a manufacturing method, in the memory array formation region, the element isolation region is formed by the opening buried insulating film without forming the element isolation field oxide film 10. Accordingly, the alignment margin between the element isolation formation region 56 and the floating gate electrode 52 can be eliminated.

Further, the rounding phenomenon of the rectangular element isolation formation region 56 due to the conventional bird's beak (the phenomenon that the square element isolation formation region 56 is more rounded through the oxidation process) is eliminated. By reducing the rounding phenomenon of 56, the alignment margin between the element isolation formation region 56 and the control gate electrode 53, the source line 55, and the select gate electrode 60 can be eliminated.

The details are omitted because they are not within the scope of the present invention, but rounding also occurs in the photographic process in the opening forming process. This is because the size of the opening is close to the optical wavelength of photographic exposure, resulting in poor resolution. Numerous methods for preventing rounding have been devised, and there is no problem in using them together.

By eliminating the alignment margin in this manner, the cell area of the memory cell 71 can be further reduced, and as a result, the memory area can be significantly reduced (high integration). become.

Further, the memory cell array 7 is formed without forming the field oxide film 10 for element isolation in the memory cell array formation region.
As a result of the formation of No. 2, it is possible to avoid the occurrence of the field step and the step of the floating gate electrode 52.

The control gate electrode 53 and the select gate electrode 60 at the time of photo development generated due to the field steps and the like.
Halation, which causes poor resolution and dimensional defects, can be avoided.

Next, a second embodiment of the method of manufacturing the semiconductor memory device 70 will be described with reference to the drawings.

The manufacturing method according to the second embodiment is an embodiment according to the invention of the manufacturing method according to claims 4, 5, 6, 7, 12, 13, and 14 of the present invention. Note that the same parts as those already described in the first embodiment are denoted by the same reference numerals, and redundant description will be omitted.

The second embodiment of the manufacturing method includes an opening forming step, an opening impurity introducing step, an opening filling step, and a diffusion layer line self-alignment forming step.

In the step of forming the opening, the first polysilicon layer for the floating gate electrode 52 is formed in a stripe-shaped region composed of element isolation formation regions 56 adjacent to each other with the regions 54 and 55 for forming the semiconductor substrate diffusion layer interposed therebetween. This is a step of forming the opening 52R.

The opening impurity introducing step performed after the opening forming step is a step of introducing a field doping impurity of the same conductivity type as that of the semiconductor substrate into the opening 52R.

In the step of filling the opening, which is performed after the step of introducing the impurity in the opening, a single-layer film or a laminated film formed using an oxide film is formed, and this is etched back to form the opening 5.
This is a step of embedding an oxide film in 2R. Note that it is also possible to form a single-layer film or a stacked film using a nitride film instead of the oxide film. Alternatively, a single-layer film or a stacked film can be formed using an oxide film and a nitride film.

In the diffusion layer line self-alignment forming step, the insulating film for the element isolation formation region 56 having a stripe shape is processed into a square shape to form the element isolation insulating film on the region where the semiconductor substrate diffusion layers 54 and 55 are formed. And a semiconductor substrate diffusion layer forming step of introducing an impurity for forming a diffusion layer into a region where the semiconductor substrate diffusion layers 54 and 55 are formed. By performing the film removing step and the semiconductor substrate diffusion layer forming step using the same mask, the diffusion layer lines 54 and 55 are self-aligned (in other words, the channel length direction of the element isolation region 56). Can be formed.

According to the embodiment of such a manufacturing method, the element isolation region is formed by the buried insulating film without forming the element isolation field oxide film 10 in the memory array formation region. The alignment margin between the element isolation formation region 56 and the floating gate electrode 52 can be eliminated.

In addition, by executing the diffusion layer self-alignment forming step, the whole of the element isolation region 56 can be practically eliminated, and the element isolation formation region 56 and the control gate electrode 5 can be removed.
3. The alignment margin with the diffusion layer line 55 is completely removed, and the element isolation region 56 and the selection gate electrode 60 are removed.
The alignment margin between them can be deleted.

Next, a specific example of the second embodiment of the manufacturing method will be described with reference to the drawings.

As in the case of the first embodiment, first, a tunnel oxide film 48 is formed on a silicon semiconductor substrate on which a well has been formed using a known appropriate method, and a first oxide film for the floating gate electrode 52 is formed. A polysilicon layer is formed.

FIG. 8 illustrates a fourth embodiment of the present invention. In the method of manufacturing a semiconductor memory device according to the second embodiment, a photolithography technique (resist coating and development) and dry etching are used. FIG. 10 is a plan view of the memory cell structure for explaining an opening filling step of performing opening processing on a stripe-shaped region including an element isolation formation region using a technique.

Next, using known photolithographic techniques (such as resist coating and development) and dry etching techniques,
As shown in (1), the first polysilicon layer is subjected to opening processing in a stripe-shaped region including the element isolation formation region 56 (opening forming step).

In the figure, 52 is a portion where the first polysilicon layer remains, and 52R is a portion where the first polysilicon layer is opened (removed).

Then, impurity ions of the same conductivity type as that of the semiconductor substrate are implanted, and a field dope impurity is introduced into the opening 52R of the first polysilicon layer in a self-aligned manner (opening impurity introducing step).

Next, the opening 52R of the first polysilicon layer is formed.
Next, a CVD oxide film having a film thickness equal to or more than の of the width of the opening 52R is formed.

FIG. 9 is a block diagram showing a fourth embodiment of the present invention.
In the method for manufacturing a semiconductor memory device according to the second embodiment, the CVD oxide film is etched back using a nitride film layer previously formed below the CVD oxide film as an end point. FIG. 11 is a plan view of the memory cell structure for explaining a buried oxide film forming step of forming a buried oxide film by performing an etch-back step of FIG.

Next, the CVD oxide film is etched back using the nitride film layer previously formed below the CVD oxide film as an end point, and as shown in FIG.
6 are formed (opening filling step).

In the present invention, as described above, the element isolation formation region 5
6, the alignment margin between the floating gate electrodes 52 can be reduced.

Here, a case where the first nitride film layer is formed before the opening of the first polysilicon layer as the nitride film layer corresponds to the twelfth and thirteenth aspects, and the second thin film layer is formed after the opening of the first polysilicon layer. The case where the nitride film layer is formed corresponds to claims 14 and 15.

Next, a second polysilicon layer for the control gate electrode 53 is formed, and an insulating film 58 for insulation from the control gate electrode 53 is additionally formed. Further, in the element isolation insulating film removing step, a nitride film layer 58b for preventing control gate etching is formed. In addition, in the subsequent step of removing the insulating film for element isolation, the nitride film
8b is formed.

Next, after forming the buried oxide film 56,
The interpoly insulating film 57 (specifically, the interpoly O
NO film).

FIG. 10 is a diagram showing a memory cell for explaining a step of forming a line of a control gate electrode by using a photolithography technique and an etching technique in a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention. It is a top view of a structure.

Next, as shown in FIG. 10, a control gate electrode line 53 is formed by using a known photolithography technique and etching technique.

FIG. 11 illustrates a seventh embodiment of the present invention. In the method of manufacturing a semiconductor memory device according to the second embodiment, a stripe-shaped pattern is formed through photolithography (MD resist mask processing). Explains an element isolation insulating film removal step of processing a buried oxide film into a square element isolation formation region using dry etching technology, and a semiconductor substrate diffusion layer formation step of introducing impurities for forming a semiconductor substrate diffusion layer. FIG. 4 is a plan view of a memory cell structure for performing the above.

Then, the buried oxide film 56 having a stripe shape is processed into a square shape by a dry etching technology through a known photolithography technology (resist mask 80 for MD), and is directly processed for a diffusion layer as shown in FIG. Is implanted.

FIG. 12 is a plan view of a memory cell structure formed by using the method for manufacturing a semiconductor memory device according to the second embodiment of the present invention. FIG. 13 is a cross-sectional view of the SS ′ element of the memory cell structure of FIG. FIG. 14 is a cross-sectional view of the CC ′ element of the memory cell structure of FIG.

In this case, as shown in FIG. 12, the drain line 54 is self-aligned at the end of the control gate electrode 53, and the source line 55 is aligned with the mask resist 80. That is, the source line 55 is also formed in a self-aligned manner with the element isolation formation region 56.

As described above, in the present embodiment, as shown in FIG. 13, unlike the conventional LOCOS, the corners of the element isolation formation region 56 can be practically eliminated, and the alignment margin can be reduced accordingly. Become. In addition, the alignment margin between the element isolation formation region 56 and the impurity implantation region for MD (= source line 55, which inline 54) and the alignment margin between the element isolation region and the control gate electrode can be reduced.

The following processes are the same as those in the first embodiment, and therefore description thereof is omitted. However, the state after the formation of the sidewall 61, the gate oxide film 49 in the second gate region, and the line 60 of the select gate electrode is shown in FIG. Shown in

Next, a third embodiment of the method of manufacturing the semiconductor memory device 70 will be described with reference to the drawings.

The manufacturing method according to the third embodiment is an embodiment of the manufacturing method according to claims 8, 9, 10, and 11 of the present invention. The same parts as those already described in the first embodiment or the second embodiment are denoted by the same reference numerals, and redundant description will be omitted.

The third embodiment of the manufacturing method includes an opening forming step, an opening impurity introducing step, an opening filling step, a drain self-alignment forming step, and a source line self-aligning forming step. Here, any of the in-line self-forming process from the opening forming process is referred to as a first self-alignment forming process, and the source line self-aligning forming process is referred to as a second second matching forming process. ,

In the opening forming step, the opening 52R of the first polysilicon layer for the floating gate electrode 52 is formed in a rectangular region including a pair of element isolation forming regions 56 adjacent to each other across the line of the drain diffusion layer 54. This is the step of forming.

The opening impurity introduction step is a step of introducing a field dope impurity of the same conductivity type as that of the semiconductor substrate into the opening 52R.

In the step of filling the opening, the step of introducing impurity in the opening is a step of forming a single-layer film or a laminated film formed using an oxide film and etching back the film to bury the oxide film in the opening 52R. .

In the drain line self-aligning formation step, the insulating film on the element isolation region 56 obtained in the above step is processed to remove the element isolation insulating film on the region where the drain diffusion layer 54 is to be formed. An element isolation insulating film removing step, and a semiconductor substrate diffusion layer impurity introducing step of introducing a diffusion layer forming impurity into a region where the drain diffusion layer 54 is formed. By performing the impurity introduction step with the same mask, the drain line 5
4 can be formed in a self-aligned manner.

As described above, since the element isolation film obtained by the opening filling step has a smaller rounded corner than the conventional LOCOS, the alignment margin between the element isolation region 56 and the source diffusion layer 55 can be reduced. . Also,
By performing the diffusion layer self-aligned forming step,
In effect, the alignment margin between the element isolation region 56 and the drain diffusion layer 54-control gate 53 can be completely eliminated.

In the source line self-aligning forming step (second self-aligning forming step), a thick sidewall 71 is formed on the line of the control gate electrode 53, and impurity ions are implanted into a part to be a source region in a self-aligning manner. And forming the second gate region 49 in a self-aligned manner.

By providing the first self-aligned formation step, the memory cell array 72 can be formed without the conventional LOCOS 10, and as a result, the alignment between the element isolation formation region 56, the floating gate electrode 52, the drain line 54, and the control gate can be achieved. The margin can be deleted.

In the case of the present embodiment, the element isolation region 56
In addition, the method of forming the select gate length L2 of the second gate region 49 of the memory cell array 72 in a self-aligned manner while eliminating and reducing the alignment margin between the layers can be used.

The process of making the select gate length L2 self-aligned not only reduces the alignment margin, but also has the effect of greatly reducing variations in memory cell characteristics such as threshold voltage, ON current, and speed.

Next, a specific example of the third embodiment of the manufacturing method will be described with reference to the drawings.

As in the case of the first and second embodiments, first, a tunnel oxide film 48 is formed on a silicon semiconductor substrate on which a well has been formed using a known appropriate method, and a floating gate electrode is formed. A polysilicon layer for 52 is formed.

FIG. 15 is for explaining the eighth, ninth, and tenth aspects of the present invention. In the method of manufacturing a semiconductor memory device according to the third embodiment, a pair of element isolations adjacent to each other with a drain region interposed therebetween is provided. FIG. 11 is a plan view of the memory cell structure for explaining an opening forming step of performing opening processing in a rectangular shape including a forming region.

Next, using known photoengraving techniques (such as resist coating and development) and dry etching techniques, FIG.
As shown in FIG. 5, the polysilicon layer is opened in a rectangular shape including a pair of element isolation formation regions 56 adjacent to each other across the drain region. In the figure, 52 is a portion where the first polysilicon layer remains, and 52R is a portion where the first polysilicon layer is opened (removed).

Then, impurity ions of the same conductivity type as that of the semiconductor substrate are implanted, and a field-doped impurity is introduced into opening 52R of the first polysilicon layer in a self-aligned manner.

Next, the opening 52R of the first polysilicon layer is formed.
Then, a CVD oxide film having a film thickness of １ ／ or more of the shorter dimension of the width or the length of the opening 52R is formed.

FIG. 16 is a block diagram of the present invention.
In the method for manufacturing a semiconductor memory device according to the third embodiment, a CVD oxide film is etched back using a nitride film layer previously formed below a CVD oxide film as an end point. FIG. 11 is a plan view of the memory cell structure for explaining a buried oxide film forming step of forming a buried oxide film by performing an etch-back step of FIG.

Next, the CVD oxide film is etched back using the nitride film layer previously formed below the CVD oxide film as an end point to form a buried oxide film 56 as shown in FIG.

In the present invention, as described above, the element isolation formation region 5
6 and the floating gate electrode 52 can be reduced in alignment margin.

Here, the case where the first nitride film layer is formed before the opening of the first polysilicon layer corresponds to claims 12 and 13, and a thin second nitride film layer is formed after the opening of the first polysilicon layer. This case corresponds to claims 14 and 15.

Next, after forming the buried oxide film 56,
An interpoly insulating film 57 (such as an interpoly ONO film) is formed.

Next, a second polysilicon layer for the control gate electrode 53 is formed, and an insulating film 58 for insulation from the control gate electrode 53 is formed. Further, in the element isolation insulating film removing step, a nitride film layer 58b for preventing control gate etching is formed.

FIG. 17 shows a memory cell structure for explaining a step of forming a control gate electrode line by using photolithography and etching in the method of manufacturing a semiconductor memory device according to the third embodiment of the present invention. FIG.

Next, as shown in FIG. 17, a control gate electrode line 53 is formed by using a known photolithography technique and etching technique.

FIG. 18 illustrates a seventh embodiment of the present invention. In the method of manufacturing a semiconductor memory device according to the third embodiment, a rectangular shape is formed through photolithography (MD resist mask processing). The drain line-shaped region of the buried oxide film is removed by dry etching technology,
FIG. 10 is a plan view of the memory cell structure for explaining a step of implanting impurity ions for forming a drain in a state where the drain line is aligned in a self-aligned manner at a control gate electrode end.

Next, through a known photolithography technique (MD resist mask 80), as shown in FIG. 18, a region to be the drain line 54 of the rectangular buried oxide film 56 is removed by dry etching technique. Impurity ion implantation for forming the drain electrode 54 is performed as it is. In this case, the drain line 54 is self-aligned at the end of the control gate electrode 53.

FIG. 19 is a block diagram showing a configuration according to the present invention.
0) or 11, wherein in the method of manufacturing a semiconductor memory device according to the third embodiment, after performing the first self-alignment forming step, the select gate length of the second gate region is determined in a self-aligned manner. FIG. 9 is a plan view of the memory cell structure for explaining a second self-alignment forming step of forming a thick sidewall on a line side surface of a control gate electrode.

Next, as shown in FIG. 19, a thick sidewall 71 for determining the length L2 (referred to as select gate length) of the second gate region in a self-aligned manner is formed on the side surface of the control gate electrode 53 line. I do. This side wall 7
1 is formed of an oxide film, polysilicon, or the like, and requires other complicated layer configurations and processes. However, since it is not included in the scope of the present invention, its description is omitted.

FIG. 20 is a block diagram of the present invention.
0) or 11; a plan view of a memory cell structure for explaining how source lines are self-aligned at side wall edges in the method of manufacturing a semiconductor memory device according to the third embodiment; FIG.

Next, as shown in FIG. 21, in the memory cell structure, as shown in FIG. 22 or 23, the self-aligning sidewall 61 is removed.

In this case, as shown in FIG. 20, the source line 55 is self-aligned at the end of the sidewall 71. The self-alignment processing of the select gate length L2
In addition to the reduction of the alignment margin, there is an effect that the variation in the memory cell characteristics such as the threshold voltage, the ON current, and the speed is significantly reduced.

FIG. 21 is a plan view of a memory cell structure formed by using the method for manufacturing a semiconductor memory device according to the third embodiment of the present invention. FIG. 22 is a cross-sectional view of the SS ′ element of the memory cell structure of FIG. FIG. 23 is a cross-sectional view taken along the line CC ′ of the memory cell structure in FIG.

Next, as shown in FIG. 21, in the memory cell structure, as shown in FIG. 22 or 23, the self-alignment side wall 61 is removed.

Since the process is the same as that of the first and second embodiments, the description is omitted. However, the side wall 61, the gate oxide film 49 in the second gate region, the line 60 of the select gate electrode, and the like are formed. FIG. 21 and FIG. 22 show the state after this.

As described above, since the element isolation film obtained by the opening filling step has a smaller rounded corner than the conventional LOCOS, the alignment margin between the element isolation region 56 and the source diffusion layer 55 can be reduced. . Also,
By performing the diffusion layer self-aligned forming step,
In effect, the alignment margin between the element isolation region 56 and the drain diffusion layer 54-control gate 53 can be completely eliminated.

As described above, by executing the manufacturing method of the first to third embodiments, the size of the memory array can be reduced, the manufacturing process can be performed easily and stably, and the device has little electrical variation. A stable element can be obtained.

In carrying out the semiconductor memory device and the method of manufacturing the same according to the present invention, all or a part of the claims may be used, and the present invention is not limited thereto. Although the description has been omitted in the above description, a means such as laminating a WSi layer or the like on the control gate electrode 53 and / or the selection gate electrode 60 to reduce the resistance may be used. It does not impose any restrictions on the use of known techniques that have not been used.

[0210]

According to the first aspect of the present invention, a memory cell array can be formed by omitting the step of forming a field oxide film for element isolation in conjunction with the self-alignment of the gate length of the second gate region. As a result, the alignment margin between the layers can be made unnecessary, and the alignment margin between the rectangular element isolation formation region and the floating gate electrode can be reduced. In addition, by forming the rectangular element isolation formation region with a buried oxide film in the opening 52R of the first polysilicon layer, the rectangular element isolation formation region is rounded by the influence of the conventional bird's beak (the square shape). (A phenomenon in which the element isolation formation region is rounded through a photographic process and an oxidation process) is reduced, so that the alignment margin between the square element isolation formation region and the control gate electrode and the selection gate electrode can be reduced. become. Since the end face of the rectangular element isolation formation region is formed by etching, the rounding phenomenon of the square element isolation formation region can be practically avoided, so that the alignment margin between the square element isolation formation region and the control gate electrode is reduced. Can be further reduced. Further, the length of the select gate in the second gate region of the memory cell array can be formed in a self-aligned manner while maintaining the reduction of the alignment margin. Since the alignment margin can be reduced in this manner, the cell area of the memory cell can be further reduced, and as a result, the memory area can be significantly reduced (high integration). In addition, the memory cell array can be formed by omitting the step of forming the field oxide film for element isolation. As a result, it is possible to avoid the occurrence of field steps and steps of the floating gate electrode.
Further, it is possible to avoid a halation phenomenon which is caused by a field step or the like and causes a resolution defect and a dimensional defect of the control gate electrode and the select gate electrode at the time of photo development.

According to the second aspect of the present invention, the memory cell array can be formed by omitting the step of forming the field oxide film for element isolation in conjunction with the self-alignment of the gate length of the second gate region. The alignment margin between the layers can be made unnecessary, and the alignment margin between the rectangular element isolation formation region and the floating gate electrode can be reduced. By performing such an opening filling step, the rectangular element isolation forming region is rounded due to the influence of the conventional bird's beak (the phenomenon that the rectangular element isolation forming region is rounded through the photographic process and the oxidation process). ) Can be reduced, so that the alignment margin between the rectangular element isolation formation region and the control gate electrode and the selection gate electrode can be reduced. Since the end face of the rectangular element isolation formation region is formed by etching, the rounding phenomenon of the square element isolation formation region can be practically avoided, so that the alignment margin between the square element isolation formation region and the control gate electrode is reduced. Can be further reduced. The select gate length of the second gate region of the memory cell array can be formed in a self-aligned manner while keeping the alignment margin reduced. Since the alignment margin can be reduced in this manner, the cell area of the memory cell can be further reduced, and as a result, the memory area can be significantly reduced (high integration). In addition, since the memory cell array can be formed by omitting the step of forming the field oxide film for element isolation, generation of a field step or a step of a floating gate electrode can be avoided. It is possible to avoid a halation phenomenon which causes a resolution defect and a dimensional defect of the control gate electrode and the select gate electrode during photo development.

According to the invention described in claim 3, according to claim 2
In addition to the effects described in (1), by performing such an opening filling step, the rounding phenomenon of the square element isolation formation region due to the influence of the conventional bird's beak (the square element isolation formation region is a photo process, Since the phenomenon of being rounded through the oxidation step) is reduced, the alignment margin between the rectangular element isolation formation region and the control gate electrode and the select gate electrode can be reduced.

According to the invention set forth in claim 4, according to claim 3,
The same effect as the effect described in (1) is obtained.

According to the fifth aspect of the present invention, a memory cell array can be formed by omitting the step of forming a field oxide film for element isolation in conjunction with the self-alignment of the gate length of the second gate region. The alignment margin between the layers can be made unnecessary, and the alignment margin between the element isolation formation region and the floating gate electrode adjacent to each other can be reduced. By performing such an opening filling step, a rounding phenomenon of adjacent element isolation forming regions due to the influence of a conventional bird's beak (the adjacent element isolation forming regions are rounded through a photographic process and an oxidation process) Phenomenon) is reduced, so that the alignment margin between the element isolation formation region and the control gate electrode and the selection gate electrode adjacent to each other can be reduced.

According to the invention described in claim 6, according to claim 5
The same effect as the effect described in (1) is obtained.

According to the invention of claim 7, according to claim 1,
7. In addition to the effects described in any one of Items 6 to 6, a memory cell array can be formed by omitting the step of forming a field oxide film for element isolation in conjunction with the self-alignment of the gate length of the second gate region. In addition, the alignment margin between the layers can be eliminated, and the alignment margin between the element isolation formation region having a stripe shape and the floating gate electrode can be reduced. By performing such an opening filling step, the element isolation formation region having a stripe shape due to the influence of the conventional bird's beak is rounded (the element isolation formation region sandwiched between the stripes is rounded through a photo process and an oxidation process). This phenomenon can reduce the alignment margin between the stripe-shaped element isolation formation region and the control gate electrode and select gate electrode.

According to the eighth aspect of the present invention, by performing such an opening filling step, the rounding phenomenon of the rectangular element isolation formation region due to the influence of the bird's beak and the like (rectangular element isolation) can be achieved. The formation area is a photo process,
Since the phenomenon of being rounded through the oxidation step is reduced, the alignment margin between the rectangular element isolation formation region and the control gate electrode and the select gate electrode can be reduced. Since the end surface of the rectangular element isolation formation region is formed by etching, the rounding of the rectangular element isolation formation region can be practically avoided, so that the alignment margin between the rectangular element isolation formation region and the control gate electrode is reduced. Can be further reduced. The select gate length of the second gate region of the memory cell array can be formed in a self-aligned manner while keeping the alignment margin reduced. Since the alignment margin can be reduced in this manner, the cell area of the memory cell 71 can be further reduced, and as a result, the memory area can be significantly reduced (high integration). In addition, the memory cell array can be formed by omitting the step of forming the field oxide film for element isolation. As a result, it is possible to avoid the occurrence of field steps and steps of the floating gate electrode. Further, it is possible to avoid a halation phenomenon which is caused by a field step or the like and causes a resolution defect and a dimensional defect of the control gate electrode and the select gate electrode at the time of photo development.

According to the ninth aspect, the eighth aspect is provided.
The same effect as the effect described in (1) is obtained.

According to the tenth aspect, the same effect as the eighth aspect can be obtained.

According to the eleventh aspect, in addition to the effects described in any one of the sixth, seventh, eighth, twelfth, thirteenth, thirteenth, thirteenth and thirteenth aspects, the gate of the second gate region is provided. Along with the self-aligned formation of the length, the memory cell array can be formed by omitting the step of forming the field oxide film for element isolation. As a result, the alignment margin between the layers can be eliminated, and the rectangular element isolation formation region-floating The alignment margin between the gate electrodes can be reduced. Further, the length of the select gate in the second gate region of the memory cell array can be formed in a self-aligned manner while maintaining the reduction of the alignment margin. Since the alignment margin can be reduced in this manner, the cell area of the memory cell 71 can be further reduced, and as a result, the memory area can be significantly reduced (high integration). In addition, the memory cell array can be formed by omitting the step of forming the field oxide film for element isolation. As a result, it is possible to avoid the occurrence of field steps and steps of the floating gate electrode. Further, it is possible to avoid a halation phenomenon which is caused by a field step or the like and causes a resolution defect and a dimensional defect of the control gate electrode and the select gate electrode at the time of photo development.

According to the twelfth aspect, the same effect as the eleventh aspect can be obtained.

According to the thirteenth aspect of the present invention, in addition to the effect of the eleventh aspect, by performing such an opening burying step, it is possible to reduce the influence of the conventional bird's beak on the element isolation formation region. Since the rounding phenomenon (the phenomenon that the element isolation formation area is rounded through the photographic process and the oxidation step) is reduced, the element isolation formation area and the control gate electrode,
The alignment margin between the select gate electrodes can be reduced. Since the end surface of the element isolation formation region is formed by etching, the rounding of the element isolation formation region can be substantially avoided, so that the alignment margin between the element isolation formation region and the control gate electrode can be further reduced. Become. The select gate length of the second gate region of the memory cell array can be formed in a self-aligned manner while keeping the alignment margin reduced. Since the alignment margin can be reduced in this way, the cell area of the memory cell can be further reduced, and as a result, the memory area can be significantly reduced (high integration).

According to the fourteenth aspect of the present invention, in addition to the effects of any one of the first to twelfth aspects, the element isolation formation region formed by such a CVD oxide film has the above-mentioned characteristics. Since the corner rounding is smaller than that of LOCOS, the opening burying step is performed by using a CVD oxide film having an optimum film thickness, and the rounding phenomenon of the element isolation formation region due to the influence of the conventional bird's beak (device The phenomenon that the isolation formation region is rounded through the photographic process and the oxidation process) is reduced, so that the alignment margin between the element isolation formation region and the control gate electrode and the selection gate electrode can be reduced. Further, as a result of the reduction of the rounding phenomenon, the alignment margin between the element isolation formation region and the MD resist mask can be reduced.
When the end face of the element isolation formation region is formed by etching using the first nitride film layer as an end point,
Actually, the rounding phenomenon of the element isolation formation region can be avoided, so that the alignment margin between the element isolation formation region and the control gate electrode can be further reduced. The select gate length of the second gate region of the memory cell array can be formed in a self-aligned manner while keeping the alignment margin reduced. Since the alignment margin can be reduced in this way, the cell area of the memory cell can be further reduced, and as a result, the memory area can be significantly reduced (high integration).

According to the fifteenth aspect, in addition to the effects described in any one of the first to twelfth aspects, the second aspect
By forming a thin oxide film before forming the nitride film layer,
This makes it possible to reduce memory reliability and memory characteristic variations. Also, by performing the opening filling step using a CVD oxide film having such an optimal film thickness, the element isolation formation region is rounded due to the influence of the conventional bird's beak (the element isolation formation region is a photo process, Since the phenomenon of curling through the oxidation step is reduced, the alignment margin between the element isolation formation region and the control gate electrode and the select gate electrode can be reduced. Also,
Since the end face of the element isolation formation region is formed by etching using the second nitride film layer as an end point, the rounding phenomenon of the element isolation formation region can be practically avoided.
The alignment margin between the element isolation formation region and the control gate electrode can be further reduced. Further, it is possible to form the select gate length of the second gate region of the memory cell array in a self-aligned manner while maintaining the reduction of the alignment margin. Since the alignment margin can be reduced in this manner, the cell area of the memory cell can be further reduced, and as a result, the memory area can be significantly reduced (high integration).

[Brief description of the drawings]

FIG. 1 is a view for explaining claims 1, 2 and 3 of the present invention. In a method for manufacturing a semiconductor memory device according to a first embodiment, a photoengraving technique (resist coating and development) and a dry etching technique are used. FIG. 11 is a plan view of the memory cell structure for explaining an opening forming step performed by the method.

FIG. 2 is a block diagram of the present invention;
FIGS. 4A and 4B are plan views of the memory cell structure for explaining an opening filling step for forming a buried oxide film in the method for manufacturing a semiconductor memory device according to the first embodiment.

FIG. 3 is a plan view of a memory cell structure for explaining a step of forming a control gate electrode line using a photolithography technique and an etching technique in the method for manufacturing a semiconductor memory device according to the first embodiment of the present invention; It is.

FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor memory device according to a first embodiment of the present invention. FIG. 9 is a plan view of a memory cell structure for describing a state in which a gate electrode end is self-aligned and a source line is aligned using a mask resist.

FIG. 5 is a plan view of a memory cell structure formed by using the method for manufacturing a semiconductor memory device according to the first embodiment of the present invention.

6 is a cross-sectional view of an SS ′ element of the memory cell structure of FIG. 5;

7 is a cross-sectional view of the memory cell structure of FIG. 5 along the line CC ';

FIG. 8 is a view for explaining claims 4, 5 and 6 of the present invention. In the method for manufacturing a semiconductor memory device according to the second embodiment, a photoengraving technique (resist coating and development) and a dry etching technique are used. FIG. 9 is a plan view of the memory cell structure for explaining an opening filling step for performing opening processing on a stripe-shaped region including an element isolation formation region.

FIG. 9 is a block diagram of the present invention;
4 and 15 are described. In the method for manufacturing a semiconductor memory device according to the second embodiment, the CV is performed using a nitride film layer previously formed below a CVD oxide film as an end point.
FIG. 11 is a plan view of the memory cell structure for explaining a buried oxide film forming step of forming a buried oxide film by performing an etch back step of etching back a D oxide film.

FIG. 10 is a plan view of a memory cell structure for explaining a step of forming a control gate electrode line by using photolithography and etching in a method for manufacturing a semiconductor memory device according to a second embodiment of the present invention; FIG.

FIG. 11 is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to a second embodiment of the present invention, in which a buried oxide film having a stripe shape is formed through photolithography (resist mask processing for MD). For the purpose of explaining a device isolation insulating film removing step of processing an element isolation formation region into a square shape using a dry etching technique and a semiconductor substrate diffusion layer forming step of introducing impurities for forming a semiconductor substrate diffusion layer. It is a top view of a memory cell structure.

FIG. 12 is a plan view of a memory cell structure formed by using a method for manufacturing a semiconductor memory device according to a second embodiment of the present invention.

13 is a cross-sectional view of an SS ′ element having the memory cell structure of FIG. 12;

FIG. 14 is a cross-sectional view taken along the line CC ′ of the memory cell structure in FIG. 12;

FIG. 15 is a view for explaining the eighth, ninth, and tenth aspects of the present invention. In the method for manufacturing a semiconductor memory device according to the third embodiment, a pair of element isolation formation regions adjacent to each other with a drain region interposed therebetween is formed. FIG. 9 is a plan view of a memory cell structure for explaining an opening forming step of performing opening processing to include a rectangular shape.

FIG. 16 is a block diagram showing an embodiment of the present invention;
14 and 15 are described. In the method for manufacturing a semiconductor memory device according to the third embodiment, the nitride film layer previously formed below the CVD oxide film is used as an endpoint.
FIG. 11 is a plan view of the memory cell structure for explaining a buried oxide film forming step of forming an buried oxide film by performing an etch-back step of etching back a VD oxide film.

FIG. 17 is a plan view of a memory cell structure for explaining a step of forming a control gate electrode line by using a photolithography technique and an etching technique in a method of manufacturing a semiconductor memory device according to a third embodiment of the present invention. It is.

FIG. 18 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to a third embodiment of the present invention, in which a rectangular buried oxide film is formed through photolithography (resist mask processing for MD). A memory cell for explaining a step of implanting impurity ions for forming a drain in a state where the drain line-shaped region is removed by a dry etching technique and the drain line is self-aligned at the control gate electrode end. It is a top view of a structure.

FIG. 19: Claims (8, 9, 10) or 11 of the present invention
In the method for manufacturing a semiconductor memory device according to the third embodiment, after the first self-alignment forming step is performed, a thick sidewall for determining the select gate length of the second gate region in a self-aligned manner is formed. FIG. 11 is a plan view of the memory cell structure for explaining a second self-alignment forming step formed on the side surface of the line of the control gate electrode.

20. Claims (8, 9, 10) or 11 of the present invention
FIG. 13 is a plan view of a memory cell structure for explaining a state in which source lines are aligned in a self-aligned manner at side wall edges in a method of manufacturing a semiconductor memory device according to a third embodiment.

FIG. 21 is a plan view of a memory cell structure formed by using a method for manufacturing a semiconductor memory device according to a third embodiment of the present invention.

FIG. 22 is a cross-sectional view of the SS ′ element of the memory cell structure in FIG. 21;

FIG. 23 is a cross-sectional view of the memory cell structure taken along the line CC ′ of FIG. 21;

FIG. 24 is a flash EEP disclosed in the prior art;
FIG. 2 is a plan view of a memory cell structure forming a ROM cell array.

[Explanation of symbols]

 Reference Signs List 48 tunnel oxide film 49 gate oxide film (second gate region) 52 floating gate electrode (first gate region) 52R opening 53 control gate electrode (first gate region) 54 substrate diffusion region (drain, drain line) 55 substrate diffusion Region (source, source line) 56 Buried oxide film (element isolation formation region) 57 Interpoly insulating film (Interpoly ONO film) 58 Insulating film 60 Select gate electrode 61 Insulating film (insulating film sidewall) 70 Semiconductor storage device 71 Memory Cell region 72 Memory cell array 80 Resist mask L2 Select gate length

Claims (15)

[Claims] 1. A method of manufacturing a semiconductor memory device, comprising: a step for forming a floating gate electrode only on a rectangular element isolation forming region sandwiched between regions forming each of the memory cells formed by the second gate region. An opening forming step of forming an opening by performing an opening process for removing the first polysilicon layer, an opening impurity introducing step of introducing a field dope impurity of the same conductivity type as that of the semiconductor substrate into the opening, An opening filling step of filling the opening with a single-layer film or a laminated film formed using a film, thereby forming a channel width direction of the element isolation region in a self-aligned manner,
And a method for reducing a level difference. 2. A method for manufacturing a semiconductor memory device, comprising: removing a first polysilicon layer for a floating gate electrode only on a rectangular element isolation formation region sandwiched between regions for forming the respective memory cells. An opening forming step of forming an opening by performing an opening process; an opening impurity introducing step of introducing a field dope impurity of the same conductivity type as that of the semiconductor substrate into the opening; and a single-layer film formed using a nitride film Or an opening burying step of burying the opening by using a laminated film, so that the channel width direction of the element isolation region is formed in a self-aligned manner,
And a method for reducing a level difference. 3. A method for manufacturing a semiconductor memory device, comprising an opening for removing the first polysilicon layer for a floating gate electrode only on a rectangular element isolation formation region sandwiched between regions for forming respective memory cells. An opening forming step of forming an opening by processing, an opening impurity introducing step of introducing a field dope impurity of the same conductivity type as that of the semiconductor substrate into the opening, and a single step formed by using an oxide film and a nitride film. An opening filling step of filling the opening by using a layer film or a laminated film, thereby forming a channel width direction of the element isolation region in a self-aligned manner,
And a method for reducing a level difference. 4. The method of manufacturing a semiconductor memory device according to claim 1, wherein the floating gate electrode is formed in a stripe-shaped region formed by element isolation formation regions adjacent to each other across a region for forming a semiconductor substrate diffusion layer. An opening forming step of forming an opening of one polysilicon layer; an opening impurity introducing step of introducing a field dope impurity of the same conductivity type as that of the semiconductor substrate into the opening; a single layer formed using an oxide film And an opening filling step of filling the opening by using a film or a laminated film, thereby forming a channel width direction of the element isolation region in a self-aligned manner,
And a method for reducing a level difference. 5. The method for manufacturing a semiconductor memory device according to claim 1, wherein the floating gate electrode is formed in a stripe-shaped region formed by element isolation formation regions adjacent to each other across a region where the semiconductor substrate diffusion layer is formed. An opening forming step of forming an opening of the first polysilicon layer; an opening impurity introducing step of introducing a field dope impurity of the same conductivity type as that of the semiconductor substrate into the opening; An opening filling step of filling the opening by using a layer film or a laminated film, thereby forming a channel width direction of the element isolation region in a self-aligned manner,
And a method for reducing a level difference. 6. The method for manufacturing a semiconductor memory device, wherein the floating gate electrode is formed in a stripe-shaped region composed of element isolation formation regions adjacent to each other with a region for forming the semiconductor substrate diffusion layer interposed therebetween. An opening forming step of forming an opening of the first polysilicon layer; an opening impurity introducing step of introducing a field-doped impurity of the same conductivity type as the semiconductor substrate into the opening; and an oxide film and a nitride film. An opening burying step of burying the opening by using the formed single-layer film or the laminated film; and an element isolation forming area forming step of forming an element isolation forming area in a self-alignment manner to reduce a step. The method for manufacturing a semiconductor memory device according to claim 1, wherein: 7. A process of processing an insulating film for an element isolation formation region having a stripe shape into a square shape, removing the element isolation insulating film in a region where a semiconductor substrate diffusion layer is formed. And a semiconductor substrate diffusion layer forming step of introducing an impurity for forming the semiconductor substrate diffusion layer. The element isolation insulating film removing step and the semiconductor substrate diffusion layer forming step are performed using the same mask. The method according to claim 1, wherein a channel length direction of the element isolation formation region is formed in a self-aligned manner by performing the process. 8. A method of manufacturing a semiconductor memory device, comprising: forming a first polysilicon layer for a floating gate electrode in a rectangular region including a pair of element isolation formation regions adjacent to each other across a line of a drain diffusion layer; An opening forming step for forming an opening, an opening impurity introducing step for introducing a field-doped impurity of the same conductivity type as that of the semiconductor substrate into the opening, a single-layer film or a laminated film formed using an oxide film And an opening filling step of filling the opening by using the method described above, whereby the channel width direction of the element isolation region is formed in a self-aligned manner,
And a method for reducing a level difference. 9. A method for manufacturing a semiconductor memory device, comprising: forming a first polysilicon layer for the floating gate electrode in a rectangular region including a pair of element isolation formation regions adjacent to each other across a line of a drain diffusion layer; An opening forming step of forming an opening; an opening impurity introducing step of introducing a field doping impurity of the same conductivity type as the semiconductor substrate into the opening; and a field doping of the same conductivity type as the semiconductor substrate into the opening. An opening impurity introducing step of introducing an impurity; and an opening filling step of filling the opening with a single-layer film or a laminated film formed using a nitride film. Is formed in a self-aligned manner,
And a method for reducing a level difference. 10. A method of manufacturing a semiconductor memory device, comprising: forming a first polysilicon layer for a floating gate electrode in a rectangular region including a pair of element isolation formation regions adjacent to each other across a drain diffusion layer line; An opening forming step of forming an opening, an opening impurity introducing step of introducing a field-doped impurity of the same conductivity type as the semiconductor substrate into the opening, and a single-layer film formed using an oxide film and a nitride film. Or an opening burying step of burying the opening by using a laminated film, so that the channel width direction of the element isolation region is formed in a self-aligned manner,
And a method for reducing a level difference. 11. The element isolation formation region forming step includes: a first self-alignment formation step of forming the element isolation formation region in a self-alignment manner; and a self-alignment by forming a thick sidewall on the control gate electrode line. 9. A second self-alignment forming step of forming the second gate region in a self-aligned manner by implanting impurity ions into a portion to be the source region. 12,13,1
14. The method of manufacturing a semiconductor memory device according to any one of 4, 15, and 13. 12. A step of forming a first nitride film layer prior to performing the opening forming step; and forming the opening in the first nitride film layer and the first polysilicon layer. A buried oxide film forming step of forming a buried oxide film having a thickness equal to or more than の of a shorter dimension of a width or a length of an opening of the first polysilicon layer; 12. An etch-back step of etching back the oxide film with the end point as an end point, whereby an insulating film for element isolation is buried in an opening of the first polysilicon layer. A method for manufacturing a semiconductor storage device. 13. A step of forming a first nitride layer prior to forming an opening in the first polysilicon layer; and forming the opening in the first nitride layer and the first polysilicon layer. And CV having a film thickness equal to or more than １ ／ of the shorter dimension of the width or the length of the opening of the first polysilicon layer.
A buried oxide film forming step of forming a D oxide film; and an etch back step of etching back the CVD oxide film using the first nitride film layer as an end point. The method for manufacturing a semiconductor memory device according to claim 11, wherein an insulating film for element isolation is buried. 14. A step of forming a thin second nitride film layer after forming the opening of the first polysilicon layer, and the width or the length of the opening of the first polysilicon layer, whichever is shorter. A buried oxide film forming step of forming a buried oxide film having a film thickness of の or more of the following, and an etch back step of etching back the oxide film with the second nitride film layer as an end point. 13. The method for manufacturing a semiconductor memory device according to claim 1, wherein an insulating film for element isolation is buried in an opening of the first polysilicon layer. 15. A step of forming a thin second nitride film layer after forming the opening of the first polysilicon layer, and the width or the length of the opening of the first polysilicon layer, whichever is shorter. A buried oxide film forming step of forming a CVD oxide film having a film thickness of １ ／ or more of the following, and an etch back step of etching back the CVD oxide film using the second nitride film layer as an end point. The method according to claim 1, wherein an insulating film for element isolation is buried in the opening of the first polysilicon layer.