JPH10242388A - Method for manufacturing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To assemble a MOS element and a MIM capacitor with a simple process by forming a spacer with polycrystalline silicon. SOLUTION: A first polycrystalline silicon layer is subjected to patterning, thus forming a gate electrode 13 and a lower electrode 14. A TEOS oxide film 16 is formed on an entire surface and a second polycrystalline silicon layer is deposited. By forming a resist mask 18 so that a part that becomes an upper electrode 20 is covered and performing an etchback, a spacer 19 and an upper electrode are formed. An insulation film 22 is deposited, thus forming a contact hole and an electrode 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit which can incorporate a relatively large-capacity capacitive element into a MOS integrated circuit in a simple process.

[0002]

2. Description of the Related Art The simplest structure as a capacitor incorporated in an integrated circuit is a structure using a PN junction. However, since the obtained capacitance value is small, for example, as described in Japanese Patent Application Laid-Open No. A configuration of a MOS type using a film, a MIS type using a silicon nitride film, and a MIM type both using an electrode wiring material as a counter electrode have been considered.

The MOS and MIS type configurations are shown in FIG.
As shown in FIG. 2, a silicon nitride film 2 is formed on an N + diffusion layer 1 as a lower electrode, and an upper electrode 3 is formed thereon. As shown in FIG. 6 (B), the MIM type structure has a structure in which a part of an electrode wiring layer is used as a lower electrode 4, a silicon nitride film 5 is formed thereon, and an upper electrode 6 is formed thereon. Is formed.

[0004] There is a strong demand for incorporating these capacitive elements into digital LSIs such as microcomputers and logics, for example, for switched capacitor filter circuits.

[0005]

However, the incorporation of such a capacitive element in an increasingly complicated and highly integrated LSI process has the disadvantage of further complicating the process.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and forms a lower electrode of a capacitor simultaneously with formation of a gate electrode, thereby forming a spacer for the gate electrode. An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit that can incorporate a large-capacitance element by a simple process by simultaneously forming an upper electrode of the capacitance element.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. First, referring to FIG. 1A, a P-type single-crystal silicon substrate 11 having an impurity concentration of about 1E15 is prepared. After cleaning the surface, an oxide film with a thickness of several hundred angstroms is formed, and CVD
A silicon nitride film is deposited by the method. After patterning this to form an oxidation resistant film and forming a channel stop region, etc., the entire substrate 11 is thermally oxidized for several hours to form a LOCOS oxide film 12 for element isolation.

Referring to FIG. 1B, the oxidation-resistant film is removed, the oxide film on the surface of the element region surrounded by the LOCOS oxide film 12 is removed, and the surface is oxidized again to obtain a clean film thickness 15.
A gate oxide film 15 of about 0 ° is formed. CV on it
A first polysilicon layer having a thickness of about 1500 ° is deposited by the method D, and is doped with phosphorus to give conductivity.
After depositing a tungsten silicide (WSi) film 30 having a thickness of about 1500 ° by a method, the tungsten silicide (WSi) film 30 is patterned with a photoresist to form a gate electrode 13 on the gate oxide film.
Is formed on the LOCOS oxide film 12 by the lower electrode 14 of the capacitive element.
To form

Referring to FIG. 2 (A), an impurity such as phosphorus is ion-implanted from the surface at 3E13 at 60 Kev by a self-alignment method using gate electrode 13 as a mask to form N- type source / drain regions. 15 are formed. Referring to FIG. 2B, a TEOS oxide film 16 having a thickness of about 100 ° is formed on the entire surface by a low pressure CVD method, and an annealing process is performed at 900 ° C. for about 30 minutes. TE
The OS oxide film 16 plays a role in preventing the tungsten silicide film 30 from peeling off the surface of the gate electrode 13 in the oxidation step, and serves as a dielectric thin film in the capacitor.

Referring to FIG. 3A, a film thickness of 300
A second polysilicon layer 17 of about 0 ° is deposited by a CVD method and is doped with phosphorus to give a conductivity type. Referring to FIG. 3B, a photoresist film is deposited on second polysilicon layer 17, exposed and developed to form lower electrode 14.
A resist mask 18 covering the upper part of the substrate is formed.

Referring to FIG. 4A, by etching back second polysilicon layer 17 by anisotropic dry etching, spacers 19 are formed on the side walls of gate electrode 13.
To form A spacer 19 is inevitably formed on the side wall of the lower electrode 14. The portion of the lower electrode 14 covered with the resist mask 18 does not have the second polycrystalline silicon layer 17 removed, and forms the upper electrode 20 opposed to the lower electrode 14 with the TEOS oxide film 16 interposed therebetween.

Referring to FIG. 4B, resist mask 1
After removing 8, phosphorus is ion-implanted from the surface under the conditions of 5e15 and 60 Kev to form N + source / drain regions 21 by a self-alignment method using the spacers 19 as a mask. With reference to FIG.
An insulating film 22 such as a BPSG film is formed on the entire surface by the VD method, and a contact hole 23 is formed by forming and etching a photoresist. Since the TEOS oxide film 16 is a silicon oxide film, an opening on the surface of the lower electrode 14 can be formed simultaneously with an opening on the surface of the source / drain regions 15 and 21. Then, an aluminum electrode 24 is formed as shown in FIG.

According to the method of the present invention described above, the lower electrode 14 of the capacitor is formed by forming the gate electrode 13, and the upper electrode 20 of the capacitor is formed simultaneously with the formation of the spacer 19.
Is formed, so that the manufacturing process can be simplified. In addition, since the TEOS oxide film 16 is used as the dielectric film, the gate electrode 13 can be used also as a protective film for the silicide film when the silicide structure is adopted, so that the process can be further simplified.

Further, the contact hole 23 on the surface of the source / drain regions 15 and 21, the contact hole 23 for the lower electrode 14, and the contact hole 23 for the aluminum electrode for leading the upper electrode can be simultaneously formed. It can be simplified.

[0015]

As described above, according to the present invention,
The gate electrode 13 and the lower electrode 14 can be shared by the spacer 19 and the upper electrode 20, and the TEOS oxide film 16 and the formation of the contact hole 23 can be shared. Has the advantage of being able to incorporate the capacitive element.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a cross-sectional view for explaining the present invention.

FIG. 4 is a cross-sectional view for explaining the present invention.

FIG. 5 is a cross-sectional view for explaining the present invention.

FIG. 6 is a cross-sectional view for explaining a conventional example.

Claims (2)

[Claims] A step of selectively oxidizing a surface of the one-conductivity-type semiconductor layer to form a LOCOS insulating film; and forming a gate insulating film on the surface of the one-conductivity-type semiconductor layer surrounded by the LOCOS oxide film. Depositing a polycrystalline silicon layer on the gate insulating film, patterning the polycrystalline silicon layer, forming a gate electrode on the gate insulating film, and a lower electrode of a capacitive element on the LOCOS insulating film. Forming an insulating film covering an upper portion of the gate electrode and the lower electrode; forming a second polycrystalline silicon layer on the insulating film; Forming a resist mask on the surface of the second polycrystalline silicon layer; etching the second polycrystalline silicon layer to form a spacer on the side wall of the gate electrode; A method for manufacturing a semiconductor integrated circuit, comprising: a step of forming an upper electrode of a capacitor; and a step of forming source / drain regions on a surface of the semiconductor layer near the gate electrode. 2. The method according to claim 1, wherein said insulating film is a TEOS film.