JPH10242273A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device which is capable of high integration by narrowing the diameter of a contact hole, and the contact hole of which has raised the reliability on wiring such as security of voltage resistance, etc. SOLUTION: Insulating films 21 and 22 are formed on a semiconductor substrate 10, and the first mask layer 33 is made on the insulating films 21 and 22, and the first contact hole is opened in the first mask layer 33. Next, the second mask layer 34 is made by the selective growth at the inwall surface of the first contact hole, and with the second mask layer 34 as a mask, the second contact hole CH2 is opened in the insulating films 21 and 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having fine contacts.

[0002]

2. Description of the Related Art As is seen in recent semiconductor memory devices and the like, as semiconductor devices become more highly integrated and higher in performance, fine processing of semiconductor devices has become an essential condition. In particular, in semiconductor storage devices that require a high degree of integration, it is necessary to reduce the gate width of the gate electrode of a transistor and the area occupied by a capacitor in a DRAM, etc., while forming a contact hole with a fine size equal to or greater than the resolution of photolithography. There is.

For example, in a DRAM using a COB structure (Capacitor Over Bitline; a structure in which a capacitor is formed above a bit line), which is one of structures for reducing the size of a memory cell, the structure is formed as a first wiring. There are a word line and a bit line formed in an upper layer of the word line in a layout orthogonal to the word line, and a storage node is formed in the upper layer. In this case, the storage node contact must be formed in a gap where the word line and the bit line intersect.

If the misalignment occurs in the photolithography process for forming the storage node contact, a short circuit may occur between the storage node contact and the word line or between the storage node contact and the bit line. . Even if such misalignment occurs, in order to ensure the withstand voltage between the storage node contact and the word line and between the storage node contact and the bit line,
The distance between the storage node contact and the word line and the distance between the storage node contact and the bit line may be increased. In this case, however, the cell size increases.
There is a disadvantage that adverse effects occur in high integration.

[0005] As a technique for avoiding the above disadvantages and ensuring the withstand voltage without increasing the distance between the storage node contact and the word line and between the storage node contact and the bit line, alignment of a contact hole step is performed. A self-aligned contact technology that can eliminate the need for a design margin on a mask has been attracting attention, and in particular, has been activated in the generations after the 0.25 μm rule. However, in order to put the self-aligned contact into practical use, it is necessary to clear a difficult etching technique that stops etching on thin Si ₃ N _4. Absent.

On the other hand, without increasing the distance between the storage node contact and the word line and between the storage node contact and the bit line, the contact hole can be made smaller than the resolution of photolithography and the diameter can be reduced. 2. Description of the Related Art There is known a technique for securing a certain distance between a storage node contact and a word line and between a storage node contact and a bit line to secure a breakdown voltage. Hereinafter, a method of reducing the diameter of the contact hole and opening the contact hole will be described with reference to the drawings.

First, as shown in FIG. 5A, a semiconductor device such as a transistor including a gate oxide film (not shown), a gate electrode (word line) 31 and a diffusion layer (not shown) is formed on a silicon semiconductor substrate 10. After the formation, these elements are covered, for example, silicon oxide is deposited by a normal pressure CVD method or the like, and is flattened by reflow or etch back to form a first insulating film 21. next,
A bit line 32 is formed on the first insulating film 21, and the bit line 32 is covered, for example, silicon oxide is deposited by a normal pressure CVD method or the like, and is flattened by reflow or etch back to form a second insulating film 22. Form. Next, for example, polysilicon is deposited on the upper layer of the second insulating film 22 under reduced pressure CV.
The first mask layer 33 is formed by depositing 200 nm by the method D. A resist film R is patterned on the first mask layer 33 to a diameter of, for example, 0.32 μm.

Next, as shown in FIG. 5B, etching such as RIE (reactive ion etching) is performed using the resist R as a mask, penetrating the first mask layer 33, and forming the second insulating film 22. A first contact hole CH1 for exposing the surface is opened. Next, the resist R is removed.

Next, as shown in FIG. 6 (c), the first mask layer 31 and the inside of the first contact hole CH1 are entirely covered with, for example, polysilicon by a low-pressure CVD method to form 100 n.
Then, a second mask layer 36 is formed.

Next, as shown in FIG. 6D, etching such as RIE is performed to etch the second mask layer 36 so as to leave the side wall in the first contact hole CH1 in a sidewall shape. Sidewall mask layer 36a
To form Thereafter, the sidewall mask layer 26a is formed.
Is used as a mask to form a second contact hole that penetrates the first insulating film 21 and the second insulating film 22 and exposes the semiconductor substrate 10. At this time, the opening diameter of the second contact hole is, for example, about 0.1 μm, and a fine contact hole can be formed by reducing the diameter of the etching mask by forming the sidewall mask layer 36a.

According to the above-described method, unlike the above-described self-aligned contact, a new approach such as a high selectivity ratio to Si ₃ N ₄ is not required, and a conventional approach of carefully clearing the microloading effect. By applying the method, it is possible to achieve the opening of a contact hole having an extremely fine and high aspect ratio of about 0.1 μmφ.

[0012]

However, in the case where a fine contact hole is formed by narrowing the diameter of the etching mask by forming the sidewall mask layer as described above, as shown in FIG. When etching the insulating film 21 and the second insulating film 22, the etching selectivity is set such that silicon oxide is etched more than polysilicon, but receding occurs at the shoulder of the sidewall mask layer 36a. . In FIG. 7E, the position of the surface of the sidewall mask layer 36a before the shoulder portion is set back is indicated by a dotted line. If the recession of the sidewall mask layer 36a continues to be severe, the diameter of the effective contact hole becomes large.

Further, as the etching of the shoulder portion of the sidewall mask layer 36a progresses, etching ions in RIE or the like are reflected on the surface of the sidewall mask layer 36a and enter the contact hole, and ions corresponding to the inner wall portion of the contact hole are removed. Increase. For this reason, bowing B easily occurs on the inner wall of the contact hole.
When bowing B occurs, the contact and bit line 32
The distance between the wiring layer and the like becomes short, and the withstand voltage deteriorates.

As shown in FIG. 7F, when the buried wiring layer 37 is formed by burying the inside of the contact hole with a conductor such as polysilicon, a void V may be generated near the bowing B. is there. When the cleaning liquid in the wet cleaning remains in the void V, there is a risk that an explosion may occur in a subsequent heat treatment step. In addition, when the buried wiring layer 37 is etched back to form a contact plug, if there is a void V, plug loss (recess amount) increases, coverage in connection with the upper wiring becomes poor, and wiring reliability decreases. I do. Further, when an extremely large void V occurs, the semiconductor substrate at the bottom of the contact hole is etched during the etching for forming the contact plug, which may cause an increase in junction leak current.

As described above, the side wall mask layer recedes to widen the opening diameter of the contact hole, and bowing and voids are generated to lower the withstand voltage. The surface of the sidewall mask layer formed by etching back after the deposition of the two mask layers has a surface oblique to the semiconductor substrate. Since the side wall mask layer is formed by etch back, the shoulder of the second mask layer drops and the second mask layer has an oblique surface. This is due to the fact that the sputtering efficiency of etching ions is maximized at a surface angle of 40 to 60 degrees.

As described above, the side wall mask layer having an oblique surface has a large surface angle with the etching ions, and the etching ions hit the oblique surface. Obliquely incident on the inside, bowing is likely to occur.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and accordingly, it is an object of the present invention to reduce the diameter of a contact hole so as to make it smaller than the resolution of photolithography and suppress the occurrence of bowing and voids. It is another object of the present invention to provide a method of manufacturing a semiconductor device having a contact hole with improved wiring reliability such as ensuring withstand voltage and capable of high integration and high performance.

[0018]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of forming an insulating film on a semiconductor substrate and forming a first mask layer on the insulating film. Forming a first contact hole in the first mask layer, forming a second mask layer by selective growth on the inner wall surface of the first contact hole, and using the second mask layer as a mask. Opening a second contact hole in the insulating film.

Since most of the etching ions in the contact hole opening step and the like are incident perpendicularly to the semiconductor substrate, the etching mask should have a shape (rectangular) that is as perpendicular to the semiconductor substrate as possible. In this case, the etching ions enter the contact hole vertically. By forming the etching mask into a shape (rectangular) that is perpendicular to the semiconductor substrate, the etching ions expand the contact hole against the mask layer, or are reflected from the mask layer and obliquely enter the inside of the contact hole. Bowing and the like can be prevented.

As described above, in order to form the etching mask into a shape (rectangular shape) that is as perpendicular to the semiconductor substrate as possible, the etching mask is formed on the first mask layer without forming the sidewall mask layer by etching back. This can be realized by forming the second mask layer in the opening only by selective growth without etching back. The first contact hole formed in the first mask layer can be processed so as to have a surface that is steep perpendicular to the semiconductor substrate, and the second mask layer is formed while maintaining the angle of the surface even in selective growth. Is possible.

When the second mask layer is formed by the selective growth as described above, the etching ions spread on the mask layer to expand the contact hole, or are reflected from the mask layer and obliquely enter the inside of the contact hole to form a bowing. Can be prevented, and the generation of voids can be suppressed, so that an increase in plug loss can be suppressed.

In the method of manufacturing a semiconductor device described above, preferably, the step of forming the second mask layer is a step of forming the second mask layer by a selective CVD method. First by selective CVD
The second mask layer can be formed while maintaining the angle of the surface of the inner wall of the contact hole.

The method of manufacturing a semiconductor device preferably includes a step of polishing the second mask layer from its upper surface after the step of forming the second mask layer and before the step of opening the second contact hole. . When the second mask layer is formed by selective growth, the vicinity of the bottom of the contact hole becomes a surface almost perpendicular to the semiconductor substrate, but the upper part of the contact hole becomes rounded or oblique. Sometimes. The upper portion of the second mask layer is polished by CMP (Chemical Mechanical Polishing) or the like to remove the rounded or inclined portion of the upper portion of the second mask layer, so that the upper portion is perpendicular to the semiconductor substrate. A second mask layer having only a near surface can be formed.

In the above-described method of manufacturing a semiconductor device, preferably, at least one of the step of opening the first contact hole and the step of opening the second contact hole is opened by low-pressure high-density plasma etching. Process, and more preferably ECR (Electron Cyclo
tron Resonance) Type plasma type etching, I
This is a step of opening by either CP (Inductively Coupled Plasma) type plasma etching or helicon wave plasma etching. Although the opening of the first contact hole and the second contact hole can be made in principle by a conventional type of plasma processing apparatus, the first contact hole is preferably opened perpendicularly to the semiconductor substrate. Since the holes are contact holes having a high aspect ratio, it is desirable to use an etching process using a low-pressure high-density plasma source in these opening steps. In low-pressure high-density plasma, an electric field is induced in a discharge space to accelerate free electrons in the plasma, and the resulting high-energy electrons ionize a neutral gas to obtain high-density plasma. When high-density plasma is generated in a low-pressure etching chamber, the probability of ions colliding with other ions or neutral gas particles in the ion sheath formed near the substrate surface is reduced, so that the straightness of ions is reduced. Since the ionization degree is high and the ionization degree is high, the ratio of ion to neutral radical can be increased, and the anisotropy of etching can be increased.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the present embodiment. Semiconductor substrate 1
A transistor and other semiconductor elements including a gate insulating film (not shown), a gate electrode (word line) 31, a diffusion layer (not shown), and the like are formed on the semiconductor substrate 10, and a first insulating film 21 covers an upper layer of the semiconductor substrate 10. doing. A bit line 32 is formed on the first insulating film 21, and a second insulating film 22 covers an upper layer thereof. A contact hole reaching the semiconductor substrate 10 is opened in the first insulating film 21 and the second insulating film 22, and a buried wiring layer 35a is buried in the contact hole.

Such a semiconductor device is a semiconductor device having a contact hole which is reduced in diameter beyond the resolution of photolithography by narrowing the diameter of the contact hole, has no bowing and voids, and has improved wiring reliability such as ensuring withstand voltage. .

Hereinafter, a method for manufacturing the semiconductor device of the present embodiment will be described. First, as shown in FIG. 2A, an element isolation insulating film (not shown) is formed on a silicon semiconductor substrate 10 by a LOCOS method or the like, and an active region of a transistor is formed and ion implantation for improving punch-through breakdown voltage is performed. Next, a gate oxide film (not shown) is formed, and for example, polysilicon and tungsten silicide are formed by CVD.
A gate electrode (word line) 31 of polycide is formed by depositing by a method and etching like a gate electrode. Next, a diffusion layer (not shown) is formed by ion implantation to form a field-effect transistor. In addition, the semiconductor substrate 10
Other semiconductor elements can be formed thereon.

After forming semiconductor elements such as transistors, these elements are covered, for example, silicon oxide is deposited by atmospheric pressure CVD or the like, and is flattened by reflow or etch back to form a first insulating film 21. . On the upper layer, for example, polysilicon and tungsten silicide are deposited by a CVD method and etched like a bit line to form a polycide bit line 32.
Next, the bit line 32 is covered, for example, silicon oxide is deposited by a normal pressure CVD method or the like, and is flattened by reflow or etch back to form the second insulating film 22.

Next, a first mask layer 33 is formed on the second insulating film 22 by depositing, for example, polysilicon to a thickness of 300 nm by a low pressure CVD method. The deposition condition of the first mask layer at this time is, for example, (apparatus: reduced pressure CVD apparatus, gas: SiH ₄ / He /
N ₂ = 100/400/200 sccm, pressure: 70 Pa, temperature: 550
° C). Next, a resist film R is patterned on the first mask layer 33 to a diameter of, for example, 0.32 μm.

Next, as shown in FIG. 2B, etching is performed using the resist R as a mask to form a first mask layer 33.
And a first contact hole CH1 exposing the surface of the second insulating film 22 is opened. The etching conditions at this time are, for example, (apparatus: ECR type plasma etching apparatus, gas: C ₂ Cl ₃ F ₃ / SF ₆ = 60/10 sccm, pressure: 1.3).
Pa, microwave: 850 W, RF Power: 100 W, susceptor temperature: 20 ° C.). Next, the resist R is removed.

Next, as shown in FIG. 3C, for example, polysilicon is deposited on the surface of the first mask layer 33 by selective growth, for example, to a thickness of 100 nm by low-pressure CVD, and the second mask layer is formed. 34 are formed. The deposition conditions of the second mask layer at this time are as follows, for example (apparatus: reduced pressure CVD apparatus, gas: SiH ₂ Cl ₂ / H ₂ / HCl = 100/2000/50 sccm, pressure: 15 P
a, temperature: 800 ° C.).

After the second mask layer is formed as shown in FIG. 3 (c), the upper portion of the second mask layer may be removed by polishing to remove the rounded or inclined portion. By removing the rounded portion of the second mask layer or the like, the second mask layer has only a surface near perpendicular to the semiconductor substrate.
A mask layer can be formed. As a polishing method, for example, C
MP (Chemical Mechanical Polishing) can be used.

Next, as shown in FIG. 3D, etching such as RIE is performed by using the second mask layer 34 as a mask to penetrate the first insulating film 21 and the second insulating film 22 to form a semiconductor substrate. Second contact hole CH exposing 10
Open 2 The etching conditions at this time are, for example, (apparatus: sheet-type magnetron reactive ion etching apparatus, gas: C ₄ F ₈ / CO / Ar = 8/60/200 sccm, pressure: 5.3P
a, RF Power: 1600 W, susceptor temperature: 20 ° C.).

Next, as shown in FIG. 4, for example, polysilicon is formed in a second contact hole CH2 by a low pressure CVD method.
The inside is buried, and the entire surface is covered with the second mask
Then, a buried wiring layer 35 is formed.

Next, as shown in FIG. 1, the entire surface is etched back by etching such as RIE to remove the conductive layer outside the contact hole, and a buried wiring layer 35a is formed in the second contact hole CH2. Form.

As described above, as shown in FIG. 1, the diameter of the contact hole is reduced to be smaller than the resolution of the photolithography, and the contact hole having no bowing and voids and having improved wiring reliability such as withstanding pressure resistance is formed. The semiconductor device having the above structure can be formed. Further, according to the embodiment, the etching back step of the second mask layer and the cleaning step after the etching back step can be reduced compared to the conventional method, and the steps can be simplified.

The present invention can be applied to any semiconductor device having a contact hole, such as a MOS transistor semiconductor device, a bipolar semiconductor device, or an A / D converter. In particular, the present invention can be preferably applied to a COB type DRAM requiring high integration, and can provide a fine and highly reliable contact bonding to a semiconductor device which has been miniaturized and miniaturized. it can.

The present invention is not limited to the above embodiment. For example, in the opening step of the first contact hole, the etching is terminated when the surface of the second insulating film 22 is exposed by penetrating the first mask layer 33.
An opening may be provided by etching to a position above the insulating film 22 or may be stopped before the first mask layer 33 is penetrated. Further, the first mask layer, the second mask layer, the buried wiring layer, and the like may have a multilayer structure. Although the gate electrode and the bit line have a two-layer structure of polycide, they may have a single-layer structure or a structure of three or more layers. In addition, various changes can be made without departing from the spirit of the present invention.

[0040]

According to the present invention, there is provided a semiconductor having a contact hole which is reduced in diameter beyond the resolution of photolithography by reducing the diameter of the contact hole, has no bowing and voids, and has improved wiring reliability such as withstand voltage. The device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to the present invention.

FIGS. 2A and 2B are cross-sectional views showing a manufacturing process of a method for manufacturing a semiconductor device according to the present invention, wherein FIG. 2A shows up to a resist film forming process, and FIG.

FIG. 3 shows a step that follows the step shown in FIG. 2;
(D) shows up to the step of forming the mask layer and up to the step of opening the second contact hole.

FIG. 4 shows a step that follows the step shown in FIG. 3 up to the step of forming an embedded wiring layer.

FIGS. 5A and 5B are cross-sectional views illustrating a manufacturing process of a conventional semiconductor device manufacturing method, in which FIG. 5A illustrates up to a resist film forming process, and FIG.

FIG. 6 shows a step that follows the step shown in FIG. 5;
(D) shows up to the step of forming the mask layer, and (d) shows the step of forming the sidewall mask layer.

FIG. 7 shows a step that follows the step shown in FIG. 6;
(F) shows up to the step of forming a buried wiring layer until the step of opening a contact hole.

[Explanation of symbols]

10 semiconductor substrate, 21 first insulating film, 22 second
Insulating film, 31 gate electrode (word line), 32 bit line, 33 first mask layer, 34, 36 second mask layer
35, 35a, 37 ... embedded wiring layer, 36a ... sidewall mask layer, R ... resist, CH1, CH2 ... contact hole

Claims (5)

[Claims] A step of forming an insulating film on the semiconductor substrate; forming a first mask layer on the insulating film; opening a first contact hole in the first mask layer; A method for manufacturing a semiconductor device, comprising: forming a second mask layer by selective growth on the inner wall surface of one contact hole; and opening a second contact hole in the insulating film using the second mask layer as a mask. 2. The method according to claim 1, wherein the step of forming the second mask layer is a step of forming by a selective CVD method. 3. The method according to claim 1, further comprising the step of forming the second mask layer after the step of forming the second mask layer.
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of polishing the second mask layer from its upper surface before a step of opening a contact hole. 4. The semiconductor device according to claim 1, wherein at least one of the step of opening the first contact hole and the step of opening the second contact hole is a step of opening by low pressure and high density plasma etching. Production method. 5. The low-pressure high-density plasma etching is performed by E
5. The method for manufacturing a semiconductor device according to claim 4, wherein the method is any one of CR type plasma etching, ICP type plasma etching, and helicon wave plasma etching.