JPH10242149A - Method of connecting solder bumps - Google Patents

Method of connecting solder bumps

Info

Publication number
JPH10242149A
JPH10242149A JP9043632A JP4363297A JPH10242149A JP H10242149 A JPH10242149 A JP H10242149A JP 9043632 A JP9043632 A JP 9043632A JP 4363297 A JP4363297 A JP 4363297A JP H10242149 A JPH10242149 A JP H10242149A
Authority
JP
Japan
Prior art keywords
solder
bump
carrier substrate
solder layer
soldered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9043632A
Other languages
Japanese (ja)
Other versions
JP3090427B2 (en
Inventor
Hideki Tsunetsugu
秀起 恒次
Masakaze Hosoya
正風 細矢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP09043632A priority Critical patent/JP3090427B2/en
Publication of JPH10242149A publication Critical patent/JPH10242149A/en
Application granted granted Critical
Publication of JP3090427B2 publication Critical patent/JP3090427B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3478Applying solder preforms; Transferring prefabricated solder patterns

Landscapes

  • Semiconductor Lasers (AREA)
  • Optical Couplings Of Light Guides (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method of connecting solder bumps which aligns them at a high accuracy in the transverse and height directions. SOLUTION: The method comprises steps a) of forming a first solder layer 22 on a transferring carrier substrate 21, b) of aligning with electrodes 23 of LD5, c) soldering to form solder bumps 24 on electrodes 23, d) of aligning and melting a second solder layer formed on a second transferring substrate 26 with the bumps 24 and e) of obtaining second solder bumps 27 of desired size.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高精度な位置合わ
せが要求される被はんだ付け部品(半導体素子や電気・
光部品あるいは配線基板)の位置合わせ方法であり、特
に溶融はんだの表面張力を利用した横方向および高さ方
向の高精度な位置合わせが可能なはんだバンプの接続方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a component to be soldered (such as a semiconductor element or
More particularly, the present invention relates to a solder bump connection method capable of performing high-precision lateral and height alignment using the surface tension of molten solder.

【0002】[0002]

【従来の技術】従来のはんだバンプの表面張力とスタン
ドオフを利用した高精度な位置合わせ方法の例を図5に
示す(文献:K.P.Jackson et al.“A Compact Multicha
nnel Tranceiver Module Using Planar-Processed Opti
cal Waveguides and Flip-ChipOptoelectronic Compone
nts”,42nd ECTC,1992)。基板1上に横
方向の位置決めを行うためのスタンドオフ2と高さ方向
の位置決めを行うためのスタンドオフ3を形成してお
き、はんだバンプ4の表面張力により、LD(レーザダ
イオード)5の切り欠き部6を二つのスタンドオフ2,
3に突き当てることにより横方向と高さ方向の高精度な
位置合わせを行うものである。すなわち、図5で、右の
バンプ(斜めに変形したもの)は表面張力で斜め右に引
き付ける力が働く。このためスタンドオフ2はLD5の
右側の切り欠き部6に嵌合するため、高さ方向と合わせ
て横方向の位置を決めることができる。また、はんだの
表面張力でスタンドオフ3は高さ方向のみの位置を決め
ることができる。
2. Description of the Related Art An example of a conventional highly accurate alignment method using the surface tension and standoff of a solder bump is shown in FIG. 5 (KP Jackson et al., “A Compact Multicha”).
nnel Tranceiver Module Using Planar-Processed Opti
cal Waveguides and Flip-ChipOptoelectronic Compone
nts ", 42nd ECTC, 1992). A standoff 2 for positioning in the horizontal direction and a standoff 3 for positioning in the height direction are formed on the substrate 1, and the surface tension of the solder bump 4 is used. , A notch 6 of an LD (laser diode) 5 with two standoffs 2,
3 to perform high-accuracy positioning in the horizontal direction and the height direction. That is, in FIG. 5, the right bump (obliquely deformed) exerts a diagonally right pulling force due to surface tension. Therefore, since the standoff 2 is fitted into the cutout 6 on the right side of the LD 5, the position in the horizontal direction can be determined in accordance with the height direction. The standoff 3 can be positioned only in the height direction by the surface tension of the solder.

【0003】また、これまでに開発されている転写形の
はんだバンプ接続方法の概略工程を図6に示す(特開平
5−166880号公報参照)。はんだの濡れ性に劣る
転写用キャリア基板7上にドット状のはんだ層8をパタ
ーン形成した後(a)、上記転写用キャリア基板7を半
導体素子9の電極10上に位置合わせし(b)、はんだ
を溶融することにより、転写用キャリア基板7上のはん
だ層8を半導体素子9の電極10上に転写し、はんだバ
ンプ11を形成する(c)。さらに、半導体素子9を配
線基板12上の電極13に位置合わせし(d)、はんだ
バンプ11をリフロすることによりフリップチップ接続
する(e)方法である。
FIG. 6 shows a schematic process of a transfer type solder bump connection method which has been developed so far (see Japanese Patent Application Laid-Open No. Hei 5-166880). After patterning the dot-shaped solder layer 8 on the transfer carrier substrate 7 having poor solder wettability (a), the transfer carrier substrate 7 is positioned on the electrode 10 of the semiconductor element 9 (b). By melting the solder, the solder layer 8 on the transfer carrier substrate 7 is transferred onto the electrode 10 of the semiconductor element 9 to form a solder bump 11 (c). Furthermore, the method is such that the semiconductor element 9 is aligned with the electrode 13 on the wiring board 12 (d), and the solder bump 11 is reflowed to perform flip-chip connection (e).

【0004】[0004]

【発明が解決しようとする課題】しかしながら、表面張
力とスタンドオフを用いた図5の方法では、位置合わせ
精度は、二つのスタンドオフ2,3やLD5の切り欠き
部6の加工精度に大きく依存する。この加工精度は、マ
スクを用いたリアクティブイオンエッチング法が主であ
り、マスクを用いたパターンの形成精度やリアクティブ
イオンエッチング法による加工精度を考慮すると1μm
以下の加工精度を得るには限界がある。
However, in the method of FIG. 5 using the surface tension and the standoff, the positioning accuracy greatly depends on the processing accuracy of the two standoffs 2 and 3 and the notch 6 of the LD 5. I do. This processing accuracy is mainly performed by a reactive ion etching method using a mask, and is 1 μm in consideration of the pattern forming accuracy using the mask and the processing accuracy by the reactive ion etching method.
There is a limit in obtaining the following processing accuracy.

【0005】また、はんだバンプ11を用いた図6の方
法で形成したはんだバンプ11を用いて図5のようなL
D5の発光部と基板1上の光ファイバとの位置合わせを
行う方法を図7および図8に示した。はんだ膜厚のばら
つきの影響を図7、チップ形状のばらつきの影響を図8
にそれぞれ示した。
[0005] Further, by using the solder bump 11 formed by the method of FIG.
FIGS. 7 and 8 show a method of aligning the light emitting portion of D5 with the optical fiber on the substrate 1. FIG. FIG. 7 shows the effect of variation in solder film thickness, and FIG. 8 shows the effect of variation in chip shape.
Respectively.

【0006】図7の(a)は、はんだ体積が最適化され
た場合の例であり、(b)は、はんだの体積が少なく所
望の高さより小さい高さ方向の位置ずれ16を生じた場
合、(c)は、はんだの体積が多く所望の高さより大き
い高さ方向の位置ずれ16を生じた場合を示している。
FIG. 7A shows an example in which the solder volume is optimized, and FIG. 7B shows a case in which the position displacement 16 in the height direction is smaller than the desired height due to a small solder volume. , (C) shows the case where the displacement of the solder in the height direction is larger than the desired height due to the large volume of the solder.

【0007】図8の(a)は、チップの重量に対しては
んだ体積が最適化された場合の例であり、(b)は、チ
ップ(LD5)の形状が大きく重量が多いため所望の高
さより小さい高さ方向の位置ずれ16を生じた場合、
(c)は、チップの重量が少ないため所望の高さより大
きい高さ方向の位置ずれ16を生じた場合を示してい
る。このように、高さ方向の位置合わせについては、は
んだ膜厚(はんだ体積)にばらつきを生じたり、また、
バンプ接続されるチップの形状(チップ重量)のばらつ
きのためにバンプ高さの高精度な制御は困難である。
FIG. 8A shows an example in which the solder volume is optimized with respect to the weight of the chip, and FIG. 8B shows a case in which the shape of the chip (LD5) is large and heavy, so that the desired height is obtained. When the position shift 16 in the height direction smaller than
(C) shows the case where the position shift 16 in the height direction larger than the desired height occurs due to the small weight of the chip. As described above, regarding the alignment in the height direction, the thickness of the solder (solder volume) varies,
It is difficult to control the bump height with high accuracy due to variations in the shape (chip weight) of the chip to be bump-connected.

【0008】特にLDや光導波路形の受光素子と光ファ
イバや光導波路との光結合系においては1μm以下の高
精度な位置合わせが必要であることを考慮すると、上記
の二つの従来方法では、横方向と高さ方向の二つの方向
で同時に高精度な位置合わせをするには限界がある。
In consideration of the necessity of high-precision alignment of 1 μm or less in an optical coupling system between an LD or an optical waveguide type light receiving element and an optical fiber or an optical waveguide, the above two conventional methods require: There is a limit in performing high-precision alignment simultaneously in two directions, the horizontal direction and the height direction.

【0009】本発明は、前記従来の問題点を解消し、本
来の溶融はんだの表面張力による自己整合力で横方向の
高精度な位置合わせが可能なことに加えて、本発明の複
数回の転写により高さ方向の位置合わせが高精度に行え
る転写形のはんだバンプの接続方法を提供することを目
的とするものである。
The present invention solves the above-mentioned conventional problems, and in addition to being capable of performing high-precision lateral alignment with the self-alignment force due to the surface tension of the original molten solder, the present invention is also applicable to a plurality of times. It is an object of the present invention to provide a transfer type solder bump connection method in which positioning in the height direction can be performed with high precision by transfer.

【0010】[0010]

【課題を解決するための手段】本発明にかかるはんだバ
ンプの接続方法は、はんだの濡れ性に劣る転写用キャリ
ア基板上に所定の形状,ピッチからなる複数のドット状
のはんだ層を形成し、当該はんだ層と対向する位置に被
はんだ付け部品の電極部を位置合わせし、前記はんだ層
を加熱溶融して前記はんだ層を前記被はんだ付け部品の
電極部に転写することによりはんだバンプを形成し、さ
らに、当該はんだバンプを形成した前記被はんだ付け部
品を、他の被はんだ付け部品の電極部に位置合わせした
後、再度前記はんだバンプを加熱溶融することによりバ
ンプ接続する転写形のはんだバンプの接続方法におい
て、はんだ層を形成した転写用キャリア基板を用いて転
写する前記工程を複数回繰り返すことにより所望の大き
さのはんだバンプを形成するものである
According to the method for connecting solder bumps of the present invention, a plurality of dot-shaped solder layers having a predetermined shape and a predetermined pitch are formed on a transfer carrier substrate having poor solder wettability. The solder bump is formed by aligning the electrode portion of the component to be soldered at a position facing the solder layer, heating and melting the solder layer and transferring the solder layer to the electrode portion of the component to be soldered. Further, after the soldered component on which the solder bump is formed is aligned with an electrode portion of another soldered component, the solder bump is connected again by heating and melting the solder bump again. In the connection method, a solder bump having a desired size is formed by repeating the process of transferring using the transfer carrier substrate on which the solder layer is formed a plurality of times. It is intended to formed

【0011】[0011]

【発明の実施の形態】本発明の実施の形態として、はん
だバンプを用いてLDと光ファイバとの光結合を行う場
合の概略工程を図1に示す。はんだとの濡れ性に劣る第
一の転写用キャリア基板21上にドット状の一回目のは
んだ層22をパターン形成した後(a)、転写用キャリ
ア基板21をLD5の電極23上に位置合わせし
(b)、はんだを溶融することにより、転写用キャリア
基板21上のはんだ層22をLD5の電極23上に転写
し、第一段階でのはんだバンプ24を形成する(c)。
さらに、二回目のはんだ層25を形成した第二の転写用
キャリア基板26とはんだバンプ24を形成したLD5
とを位置合わせし(d)、はんだを溶融することによ
り、転写用キャリア基板26上のはんだ層25をLD5
の電極23上に転写し、第二段階でのはんだバンプ27
を形成する(e)。このようにして、発光部15と光フ
ァイバ14の中心が一致する所望のバンプ高さが得られ
る大きさとした後に、第二段階でのはんだバンプ27を
溶融することによりLD5を配線基板12にバンプ接続
するとともに光ファイバ14を搭載する(f)。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, FIG. 1 shows a schematic process for performing optical coupling between an LD and an optical fiber using solder bumps. After patterning the first solder layer 22 on the first transfer carrier substrate 21 having poor wettability with solder (a), the transfer carrier substrate 21 is positioned on the electrode 23 of the LD 5. (B) By melting the solder, the solder layer 22 on the transfer carrier substrate 21 is transferred onto the electrode 23 of the LD 5 to form the solder bump 24 in the first stage (c).
Further, the second transfer carrier substrate 26 on which the second solder layer 25 is formed and the LD5 on which the solder bumps 24 are formed
(D), and by melting the solder, the solder layer 25 on the transfer carrier substrate 26 is
Is transferred onto the electrode 23, and the solder bump 27 in the second stage is
(E). In this manner, after the light emitting portion 15 and the center of the optical fiber 14 are adjusted to have a desired bump height, the LD 5 is bumped onto the wiring board 12 by melting the solder bump 27 in the second stage. Connect and mount the optical fiber 14 (f).

【0012】本発明は、前記のような方法により、前記
はんだ層を転写する工程において、所望のはんだ膜厚が
得られるまで転写用キャリア基板を用い転写する工程を
複数回繰り返すことで所望の形状のはんだバンプを形成
することができることから、高精度な位置合わせでLD
や光導波路形の受光素子と光ファイバや光導波路との光
結合系を実現することができる。
According to the present invention, in the step of transferring the solder layer by the method as described above, the step of transferring using a transfer carrier substrate is repeated a plurality of times until a desired solder film thickness is obtained, thereby obtaining a desired shape. LD bumps with high precision alignment
And an optical waveguide type light receiving element and an optical coupling system between an optical fiber and an optical waveguide.

【0013】[0013]

【実施例】本発明の実施例を図2〜図4の(a)〜
(n)に示す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.
(N).

【0014】はんだとの濡れ性に劣る基板材料として
は、例えばシリコン,チタン,モリブデン等からなる第
一の転写用キャリア基板21の上に、フィルム状の膜厚
レジスト(例えば、デュポン社の商品名「リストン」あ
るいは液状のレジスト(例えば、シプレー社のAZ系レ
ジスト))を用いてパターン形成し、真空蒸着法等によ
りはんだを形成した後、リフトオフ技術により前記レジ
ストを除去し、一回目のはんだ層22を形成する
(a)。前記転写用キャリア基板21に形成した一回目
のはんだ層22とLD5上の電極23を位置合わせし、
若干の加圧により両者を仮止めし、これをキャリア治具
28に載せ、一回目のはんだ層22に浸透するようにフ
ラックス29を塗布する(b)。次に、ホットプレート
30を用いて所望の時間,温度で加熱処理を行い
(c)、はんだバンプ24としてはんだ層22の転写を
完了する(d)。次に、有機溶剤を用いてフラックス2
9を洗浄除去し第一段階でのはんだバンプ24が完成す
る(e)。
As a substrate material having poor wettability with solder, for example, a film-shaped film thickness resist (for example, a product name of DuPont) is formed on a first transfer carrier substrate 21 made of silicon, titanium, molybdenum or the like. A pattern is formed by using "liston" or a liquid resist (for example, AZ-based resist of Shipley), a solder is formed by a vacuum deposition method or the like, and then the resist is removed by a lift-off technique, and the first solder layer is formed. 22 is formed (a). The first solder layer 22 formed on the transfer carrier substrate 21 and the electrode 23 on the LD 5 are aligned,
The two are temporarily fixed by a slight pressure, placed on a carrier jig 28, and a flux 29 is applied so as to penetrate the first solder layer 22 (b). Next, a heating process is performed at a desired time and temperature using the hot plate 30 (c), and the transfer of the solder layer 22 as the solder bump 24 is completed (d). Next, using an organic solvent, flux 2
9 is removed by washing to complete the solder bump 24 in the first stage (e).

【0015】さらに再度、二回目のはんだ層25を形成
した第二の転写用キャリア基板26と前記第一段階での
はんだバンプ24を形成したLD5を位置合わせし、若
干の加圧により両者を仮止めし、これをキャリア治具2
8に載せ、二回目のはんだ層25に浸透するようにフラ
ックス29を塗布する(f)。次に、ホットプレート3
0を用いて所望の時間,温度で加熱処理を行い(g)、
はんだバンプ27としてはんだ層25の転写が完了する
(h)。次に、有機溶剤を用いてフラックス29を洗浄
除去し第二段階でのはんだバンプ27が完成する
(i)。
Further, the second transfer carrier substrate 26 on which the second solder layer 25 has been formed and the LD 5 on which the solder bumps 24 have been formed in the first stage are aligned again, and both are temporarily provisionally pressed by a slight pressure. Stop this and fix it to carrier jig 2
8 and a flux 29 is applied so as to penetrate the second solder layer 25 (f). Next, hot plate 3
Heating is performed at a desired temperature for a desired time using 0 (g),
The transfer of the solder layer 25 as the solder bump 27 is completed (h). Next, the flux 29 is washed away using an organic solvent to complete the solder bump 27 in the second stage (i).

【0016】さらに前記第二段階でのはんだバンプ27
を形成したLD5と光ファイバ14を固定するためのV
溝31を形成した配線基板12上の電極13を位置合わ
せし、若干の加圧により両者を仮止めし、これをキャリ
ア治具28に載せ、第二段階でのはんだバンプ27に浸
透するようにフラックス29を塗布する(j)。次に、
ホットプレート30を用いて所望の時間,温度で加熱処
理を行い(k)、バンプ接続が完了する(l)。次に、
有機溶剤を用いてフラックス29を洗浄除去し、LD5
の配線基板12へのバンプ接続が完成する(m)。最後
に、UV接着剤32を用いて光ファイバ14を接続する
(n)。このようにして、LD5の発光部15を光ファ
イバ14の中心に位置合わせすることができる。
Further, the solder bump 27 in the second stage is used.
V for fixing the optical fiber 14 to the LD 5 formed with
The electrodes 13 on the wiring board 12 in which the grooves 31 are formed are aligned, temporarily fixed by a slight pressure, and placed on a carrier jig 28 so as to penetrate the solder bumps 27 in the second stage. The flux 29 is applied (j). next,
Heat treatment is performed at a desired temperature for a desired time using the hot plate 30 (k), and the bump connection is completed (l). next,
The flux 29 is washed and removed using an organic solvent, and LD5 is removed.
The bump connection to the wiring substrate 12 is completed (m). Finally, the optical fiber 14 is connected using the UV adhesive 32 (n). Thus, the light emitting section 15 of the LD 5 can be aligned with the center of the optical fiber 14.

【0017】上記実施例では二回の転写工程の例を示し
たが、所望のバンプ形状が得られるよう、所定の膜厚の
はんだ層を形成した転写用キャリア基板を二回以上転写
する工程で形成することができるのも自明である。
In the above embodiment, an example of two transfer steps has been described. However, in order to obtain a desired bump shape, a transfer carrier substrate on which a solder layer having a predetermined thickness is formed is transferred twice or more. Obviously, it can be formed.

【0018】また、上記実施例ではLD5の例で示した
が、被はんだ付け部品としてはこれに限定されず、半導
体素子や電子部品にも適用できることも自明である。
In the above embodiment, the example of the LD 5 has been described. However, the parts to be soldered are not limited to this, and it is obvious that the present invention can be applied to semiconductor elements and electronic parts.

【0019】さらに、上記実施例ではLD5側に転写用
のはんだバンプ27を形成する例を示したが、対向する
配線基板12側に所望の形状の転写用のはんだバンプ2
7を形成することもできる。
In the above embodiment, the transfer solder bump 27 is formed on the LD 5 side. However, the transfer solder bump 2 having a desired shape is formed on the opposing wiring board 12 side.
7 can also be formed.

【0020】[0020]

【発明の効果】以上のように、本発明は、はんだ層を転
写する工程において、所定の膜厚のはんだ層を有する転
写用キャリア基板を用い、前記転写する工程を複数回繰
り返すことにより所望の大きさのはんだバンプを形成す
るようにしたので、高精度な位置合わせで被はんだ付け
部品、例えばLDや光導波路形の受光素子と他の被はん
だ付け部品、例えばファイバや光導波路との光結合系を
実現することができる。
As described above, according to the present invention, in the step of transferring the solder layer, the transfer step is repeated a plurality of times using a transfer carrier substrate having a solder layer of a predetermined thickness. Since the size of the solder bump is formed, the component to be soldered, such as an LD or an optical waveguide type light receiving element, and the optical connection between another component to be soldered, such as a fiber or an optical waveguide, with high precision alignment. A system can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態を示す工程図である。FIG. 1 is a process chart showing one embodiment of the present invention.

【図2】本発明の一実施例を示す工程図である。FIG. 2 is a process chart showing one embodiment of the present invention.

【図3】本発明の一実施例を示す図2に続く工程図であ
る。
FIG. 3 is a process drawing following FIG. 2 showing one embodiment of the present invention.

【図4】本発明の一実施例を示す図3に続く工程図であ
る。
FIG. 4 is a process drawing following FIG. 3 showing one embodiment of the present invention.

【図5】従来のはんだバンプを用いた高精度な位置合わ
せ方法を説明する図である。
FIG. 5 is a diagram illustrating a conventional highly accurate alignment method using solder bumps.

【図6】従来の転写形のはんだバンプ接続方法を説明す
る図である。
FIG. 6 is a diagram illustrating a conventional transfer type solder bump connection method.

【図7】図6の接続方法を用いた位置合わせの例を説明
する図である。
FIG. 7 is a diagram illustrating an example of alignment using the connection method of FIG. 6;

【図8】図6の接続方法を用いた位置合わせの例を説明
する図である。
FIG. 8 is a diagram illustrating an example of alignment using the connection method of FIG. 6;

【符号の説明】[Explanation of symbols]

1 基板 2 横方向の位置決めスタンドオフ 3 高さ方向の位置決めスタンドオフ 4 はんだバンプ 5 LD 6 切り欠き部 7 転写用キャリア基板 8 はんだ層 9 半導体素子 10 半導体素子の電極 11 はんだバンプ 12 配線基板 13 配線基板上の電極 14 光ファイバ 15 発光部 16 高さ方向の位置ずれ 21 第一の転写用キャリア基板 22 一回目のはんだ層 23 LDの電極 24 第一段階でのはんだバンプ 25 二回目のはんだ層 26 第二の転写用キャリア基板 27 第二段階でのはんだバンプ 28 キャリア治具 29 フラックス 30 ホットプレート 31 V溝 32 UV接着剤 DESCRIPTION OF SYMBOLS 1 Substrate 2 Horizontal positioning standoff 3 Height positioning standoff 4 Solder bump 5 LD 6 Notch 7 Transfer carrier substrate 8 Solder layer 9 Semiconductor element 10 Electrode of semiconductor element 11 Solder bump 12 Wiring board 13 Wiring Electrode on substrate 14 Optical fiber 15 Light emitting part 16 Position shift in height direction 21 First transfer carrier substrate 22 First solder layer 23 LD electrode 24 Solder bump in first stage 25 Second solder layer 26 Second transfer carrier substrate 27 Solder bump in second stage 28 Carrier jig 29 Flux 30 Hot plate 31 V groove 32 UV adhesive

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 はんだの濡れ性に劣る転写用キャリア基
板上に所定の形状,ピッチからなる複数のドット状のは
んだ層を形成し、当該はんだ層と対向する位置に被はん
だ付け部品の電極部を位置合わせし、前記はんだ層を加
熱溶融して前記はんだ層を前記被はんだ付け部品の電極
部に転写することによりはんだバンプを形成し、さら
に、当該はんだバンプを形成した前記被はんだ付け部品
を、他の被はんだ付け部品の電極部に位置合わせした
後、再度前記はんだバンプを加熱溶融することによりバ
ンプ接続する転写形のはんだバンプの接続方法におい
て、 はんだ層を形成した転写用キャリア基板を用いて転写す
る前記工程を複数回繰り返すことにより所望の大きさの
はんだバンプを形成することを特徴とするはんだバンプ
の接続方法。
1. A plurality of dot-shaped solder layers having a predetermined shape and a predetermined pitch are formed on a transfer carrier substrate having poor solder wettability, and an electrode portion of a component to be soldered is provided at a position facing the solder layer. To form a solder bump by heating and melting the solder layer and transferring the solder layer to the electrode portion of the component to be soldered, and further, the component to be soldered having the solder bump formed thereon. In the transfer type solder bump connection method in which the solder bumps are connected again by heating and melting the solder bumps again after the positioning with the electrode portions of the other parts to be soldered, the method uses a transfer carrier substrate on which a solder layer is formed. A solder bump of a desired size is formed by repeating the above-mentioned step of transferring a plurality of times by soldering.
JP09043632A 1997-02-27 1997-02-27 Solder bump connection method Expired - Fee Related JP3090427B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09043632A JP3090427B2 (en) 1997-02-27 1997-02-27 Solder bump connection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09043632A JP3090427B2 (en) 1997-02-27 1997-02-27 Solder bump connection method

Publications (2)

Publication Number Publication Date
JPH10242149A true JPH10242149A (en) 1998-09-11
JP3090427B2 JP3090427B2 (en) 2000-09-18

Family

ID=12669248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP09043632A Expired - Fee Related JP3090427B2 (en) 1997-02-27 1997-02-27 Solder bump connection method

Country Status (1)

Country Link
JP (1) JP3090427B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107422420A (en) * 2017-08-29 2017-12-01 中国科学院宁波材料技术与工程研究所 A kind of three-dimensional photon device interconnection method based on melting direct write
WO2023153476A1 (en) * 2022-02-10 2023-08-17 京セラ株式会社 Light-emitting device production method and production device, and laser element substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107422420A (en) * 2017-08-29 2017-12-01 中国科学院宁波材料技术与工程研究所 A kind of three-dimensional photon device interconnection method based on melting direct write
CN107422420B (en) * 2017-08-29 2019-10-18 中国科学院宁波材料技术与工程研究所 A kind of three-dimensional photon device interconnection method based on melting direct write
WO2023153476A1 (en) * 2022-02-10 2023-08-17 京セラ株式会社 Light-emitting device production method and production device, and laser element substrate

Also Published As

Publication number Publication date
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