JPH10233940A - Digital synchronous separating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To separate synchronization with high accuracy in a broad temperature range by dividing an inputted synchronizing signal into a horizontal synchronizing signal (HD) and a vertical synchronizing signal (VD) based on a horizontal frequency that is measured by a frequency measuring part. SOLUTION: A polarity discriminating part 1 decides the polarity of an inputted synchronizing signal. A 1st synchronous polarity inverting part 2 inverts an HD or a composite synchronizing signal into a required polarity based on a decision result of the part 1. A 2nd synchronous polarity inverting part 3 inverts a VD into a required polarity based on the decision result of the part 1. A frequency measuring part 4 measures the frequency or cycle of the HD. An HD/VD separating part 5 separates the HD and the VD from the synchronizing signal based on measured data of the part 4. Also, when the part 4 measures a horizontal frequency based on a cycle of a horizontal scan line after a prescribed number that is sufficiently separated from the VD, e.g. the 128th horizontal scan line, a horizontal frequency is accurately detected and it is possible to perform stable synchronous separation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital sync separation circuit for digitally separating a horizontal sync signal and a vertical sync signal from a composite video signal.

[0002]

2. Description of the Related Art For example, a synchronization separation circuit in a television separates a composite video signal from a detection circuit into a horizontal synchronization signal and a vertical synchronization signal. Generally, a horizontal synchronizing signal has many high frequency components because the pulse width is narrow and the repetition frequency is large. Further, the vertical synchronizing signal has a large pulse width and a small repetition frequency, and thus contains many low frequency components. Therefore, conventionally, a horizontal synchronization signal is extracted by removing a low frequency component using a high-pass filter (differential circuit), and a vertical synchronization signal is extracted by removing a high frequency component using a low-pass filter (integrating circuit). ing. Thereafter, horizontal and vertical synchronizing pulses are obtained by performing slicing processing based on a preset slice level for each of the horizontal and vertical synchronizing signals.

The above-described conventional sync separation circuit is realized using an analog circuit such as a filter using a CR and a comparison circuit for obtaining horizontal and vertical sync pulses by comparing with a reference value.

In recent years, televisions have been used not only for reproducing and displaying broadcast programs but also as so-called multimedia displays for viewing various video sources. For example, PDP (Plasma Display P
A flat-panel television using anel) is also useful as a personal computer monitor.

However, the conventional sync separation circuit is constituted by an analog circuit, and when the ambient temperature fluctuates greatly, the phase fluctuation of the horizontal and vertical synchronizing pulses may exceed an allowable range. In addition, PD used for personal computer monitor
NTSC (National Television System)
m Committee) In addition to video signals, various composite video signals are input. Therefore, the polarity of the synchronization signal to be separated, the type of the synchronization signal, and the frequency are also variously processed. Since it is difficult for a conventional fixed-constant analog circuit to perform synchronization separation in response to these various synchronization signals, there has been a problem that another synchronization separation circuit is required.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and provides high-precision synchronous separation over a wide temperature range without depending on the polarity of the input synchronization signal, the type of the synchronization signal, and the frequency. It is an object to provide a digital synchronization separation circuit.

[0007]

In order to achieve the above object, a polarity discriminator for detecting the polarity of an input synchronization signal;
A synchronization polarity inverting unit that inverts the synchronization signal to a required polarity based on the determination result of the polarity determination unit, a frequency measurement unit that measures a horizontal frequency or a cycle, and a horizontal synchronization unit based on the measurement data of the frequency measurement unit. A synchronization separation unit that separates a synchronization signal and a vertical synchronization signal.

A polarity discriminator for discriminating the type and polarity of the synchronizing signal; a first synchronizing polarity inverting unit for inverting the horizontal synchronizing signal and the composite synchronizing signal to required polarities based on the discrimination result of the polarity discriminating unit; A second synchronization polarity inversion unit that inverts the vertical synchronization signal to a required polarity based on the determination result of the polarity determination unit, a frequency measurement unit that measures the frequency or cycle of the horizontal synchronization signal of a predetermined scan number, and the composite synchronization signal , An HD / VD separation unit for extracting a horizontal synchronization signal or a vertical synchronization signal with reference to the frequency or cycle of the frequency measurement unit, a vertical synchronization signal output from the second synchronization polarity inversion unit, and the HD / VD And a switch unit for selectively outputting either one of the vertical synchronizing signal output from the separation unit based on the result of the discrimination by the polarity discrimination unit.

The frequency measuring section measures a horizontal frequency based on a cycle of a predetermined or later horizontal synchronizing signal.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS With the above construction, the polarity discriminating section judges the polarity of the input synchronization signal, and the sync polarity inverting section determines a predetermined polarity, for example, based on the judgment result of the polarity discriminating section. , The synchronization signal is inverted so as to have a negative polarity, the frequency measurement unit measures the frequency or cycle of the horizontal synchronization signal, and the HD / VD separation unit inputs the synchronization signal based on the horizontal frequency measured by the frequency measurement unit. Is separated into a horizontal synchronization signal and a vertical synchronization signal.

In another configuration, the polarity discriminating section discriminates the type and polarity of the input synchronization signal, and the first synchronization polarity inverting section sets the polarity of the synchronization signal to a predetermined polarity based on the discrimination result of the polarity discriminating section. A second synchronization polarity inverting unit sets the polarity of the synchronization signal to a predetermined polarity based on the determination result of the polarity determination unit, and a frequency measurement unit scans the synchronization signal through the first synchronization polarity inversion unit for a predetermined scan. The HD / VD separation unit measures the frequency or cycle of the numbered horizontal synchronization signal, and the HD / VD separation unit refers to the frequency or cycle of the frequency measurement unit from the synchronization signal passed through the first synchronization polarity inversion unit, and Extract the vertical sync signal. On the other hand, the switch section selectively outputs either the vertical synchronization signal from the second synchronization polarity inversion section or the vertical synchronization signal from the HD / VD separation section based on the determination result of the polarity determination section.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital sync separation circuit according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital sync separation circuit according to the present invention. 1
Is a polarity determining unit for determining the type and polarity of the synchronization signal. Reference numeral 2 denotes a first synchronization polarity inversion unit that inverts the horizontal synchronization signal or the composite synchronization signal to a required polarity based on the determination result of the polarity determination unit 1. Reference numeral 3 denotes a second synchronization polarity inversion unit that inverts the vertical synchronization signal to a required polarity based on the result of the determination by the polarity determination unit 1. Reference numeral 4 denotes a frequency measurement unit that measures the frequency or cycle of the horizontal synchronization signal of a predetermined scan number. 5
Is an HD / VD separation unit that extracts a horizontal synchronization signal (HSYNC) or a vertical synchronization signal (VSYNC) from the composite synchronization signal by referring to the frequency or cycle of the frequency measurement unit. Reference numeral 6 denotes a determination result of the polarity determination unit 1 based on a vertical synchronization signal (VD) output from the second synchronization polarity inversion unit 3 and a vertical synchronization signal (VSYNC) output from the HD / VD separation unit. A switch unit for selectively outputting one of the two based on the output.

The operation of the digital sync separation circuit according to the present invention will be described with reference to FIGS. FIG. 2 is a schematic diagram of a signal waveform showing a process of separating the horizontal synchronization signal (b) and the vertical synchronization signal (2) from the composite synchronization signal (a) of the digital synchronization separation circuit according to the present invention. Based on the result of the determination by the polarity discriminating unit 1, the first synchronous polarity inverting unit 2 generates and outputs a negative-polarity composite synchronizing signal (a). The frequency measuring unit 4 measures a period of a predetermined, for example, 128th, horizontal synchronizing signal based on the vertical synchronizing signal, and supplies the numerical value to the HD / VD separating unit 5. On the other hand, the HD / VD separation unit 5 generates a VD-removed composite synchronizing signal (A) ′ obtained by removing VD from the input composite synchronizing signal (A), and generates a pulse from the falling edge of the VD-removed composite synchronizing signal (A) ′. By measuring the low period of
Based on the measured width, a horizontal pulse (a) or an equivalent pulse (c) is detected, and for each horizontal pulse (a) or equivalent pulse (c), for example, 3 / 4H (3/4 of the horizontal synchronization signal)
Generates a sufficiently wide mask pulse (1) such as
An OR operation is performed with the VD removal composite synchronization signal (A) ′.
As a result, the equivalent pulse (c) and the like are removed, and FIG.
Is obtained.

The HD / VD separation section 5 detects the vertical synchronization pulse (b) included in the composite synchronization signal (a) based on the width thereof, and performs a retrigger operation by, for example, falling of the vertical synchronization pulse (b). 2 (2) is generated using a one-shot multivibrator or the like, and a logical AND operation with the original composite synchronization signal (a) is performed. As a result, the cutting pulse is removed, and the pseudo vertical synchronizing signal shown in FIG. Next, the HD / VD separation unit 5 measures a low period from the fall of the pseudo vertical synchronizing signal (c).
A period of 1.75H to 2H or the like is used as a determination reference value (e), and when the low period is larger than the determination reference value (e), the pseudo vertical synchronization signal (c) is determined to be a correct vertical synchronization signal. 2 (d) as a vertical synchronizing signal having a predetermined pulse width.
Is output. The pulse width is used for detection or determination of each pulse since the following relationship is used. That is,
Equivalent pulse width << horizontal synchronization pulse width << vertical synchronization pulse width.

FIG. 3 is a circuit block diagram showing an embodiment of the polarity discriminating unit of the digital sync separation circuit according to the present invention. The general operation will be described below. First negative edge detector
Reference numeral 11 outputs a trigger signal by detecting a fall of the input horizontal synchronizing signal (HD) or composite synchronizing signal (CS). When this trigger signal is input to the low active load terminal, the first up / down counter 12 having a 12-bit configuration connected to the subsequent stage loads a required initial value, for example, “100000000000” (12 bits), and
Count down or count up according to the logic state of the input synchronization signal (horizontal synchronization signal or composite synchronization signal). The horizontal period counter 13 is enabled by the trigger signal and counts a predetermined number, for example, 64 horizontal scanning lines, and performs a low logic output.

On the other hand, an OR gate 14 calculates a logical sum of a predetermined logical output of the horizontal period counter 13 and the trigger signal. An 8-bit second up / down counter 15 loads a required initial value, for example, "10000000" (8 bits) by the low output of the OR gate 14, and is enabled by a trigger signal of the first negative edge detector. And the first up / down counter
Count down or count up according to the logic state of the 12 MSBs (most significant bits). The first D flip-flop 16 for latching the output is enabled when the OR gate 14 outputs a low OR, and latches the state of the MSB (most significant bit) of the second up / down counter. As a result of the operation of each unit described above, for example, when the output of the first D flip-flop 16 provided at the last stage is “1”, the polarity of the input synchronization signal is “negative” and the output is “0”. , The polarity of the input synchronization signal is determined to be “positive”.

The first RS flip-flop 17 inputs the trigger signal of the first negative edge detector 11 to the low active R terminal, and outputs the first up / down signal.
The carry of the down counter 12 is input to the S terminal, and the presence or absence of a horizontal synchronization signal is determined based on the output state of "0" or "1".

The second negative edge detector 18 detects the fall of the vertical synchronizing signal (VD), and the third up / down counter 19 detects the low level of the second negative edge detector 18 provided at the preceding stage. A required initial value is loaded when a logical output is input, and enabled by a trigger signal of the first negative edge detection unit 11,
Count down or count up according to the logical state of the vertical synchronization signal. The second D flip-flop 20 installed at the last stage is enabled by the low logic output of the second negative edge detector 18, and the third D flip-flop 20 is turned on.
The state of the MSB (most significant bit) of the down counter 19 is latched. Therefore, for example, the first D flip-flop 16
Is "1", the polarity of the input synchronization signal is "negative", and when the output is "0", the polarity of the input synchronization signal is determined to be "positive".

The second RS flip-flop 21 receives the trigger signal of the second negative edge detector 18 as an input to a low-active R terminal, and transfers the carry of the third up / down counter 19 to an S terminal. The presence or absence of a vertical synchronization signal is determined based on the output state.

FIG. 4 is a circuit block diagram showing an embodiment of the HD / VD separation section of the digital synchronization separation circuit according to the present invention. The general operation will be described below with reference to FIG. The VD removing unit 31 removes the vertical synchronizing signal from the input composite synchronizing signal (a) and corrects the pulse width of the equivalent pulse (C) so that it becomes equal to the horizontal synchronizing pulse (a). B) Generate '. The L count unit 32 measures the width of the composite synchronization signal (a) during the low period, and the horizontal synchronization pulse determination unit 33 connected to the next stage measures the pulse width reference value stored in advance and the measurement result of the L count unit. To determine whether it is a horizontal synchronization pulse (a) or an equivalent pulse (C). When the determination result of the horizontal synchronization pulse determination unit 33 is, for example, the horizontal synchronization pulse (a) of the composite synchronization signal shown in FIG.
The horizontal mask signal shown in (1) is output, and the OR gate 35
Performs a logical OR operation on the signal output from the VD removing unit 31 and the horizontal mask signal to separate the horizontal synchronizing signal shown in FIG.

The vertical synchronizing pulse determining unit 36
The measurement result of the counting section 32 is compared with the vertical synchronization pulse width reference value to determine the vertical synchronization pulse (b) shown in FIG. If the determination result of the vertical synchronization pulse determination unit 36 is, for example, the vertical synchronization pulse (b), the second mask signal generation unit 37 outputs the vertical mask signal shown in FIG. Numeral 38 performs a logical product operation of the composite synchronization signal and the vertical mask signal (2). Next stage VD determination unit
39 indicates that the “low state” of the output signal of the AND gate 38 is
For example, if the period is equal to or longer than the 2H cycle, the output signal is determined to be a vertical synchronization signal (VD), and the VD generation unit 40 provided at the subsequent stage generates the vertical synchronization signal shown in FIG. I do.

FIG. 5 is a circuit block diagram showing an embodiment of the frequency measuring section of the digital sync separation circuit according to the present invention.
The general operation will be described below. The first edge detection unit 51 receives the input horizontal synchronization signal (HD) or composite synchronization signal (C
For example, the falling edge of S) is detected and a signal is output. When the output of the first edge detection unit 51 is input to the first counter 52, the first counter 52 initializes, for example, `` 00 ... 0
00 ”and the like, and counting is started. Accordingly, the first counter 52 counts the horizontal cycle with a clock for each horizontal synchronization signal (HD).

On the other hand, the second edge detecting section 54 detects, for example, a falling edge of the input vertical synchronizing signal (VD), and the second counter 55 outputs a signal indicating that the output of the first edge detecting section 51 is "low". In this case, when the output is enabled and the output of the second edge detection unit 54 is “low”, an initial value, for example, “00... 000” is loaded and the clock is counted. The decoder 56 decodes the output of the second counter 55, and produces a decoded output when the output of the second counter 55 is "128", for example. The OR gate 57 calculates the logical sum of the output of the decoder 56 and the output of the first edge detection unit 51 as two inputs, and supplies this output to the enable terminal of the D flip-flop 53. From the falling edge of the synchronization signal, for example, the cycle of the 128th horizontal scanning line is counted.

[0024]

As described above, the present invention provides a digital sync separation circuit that performs high-precision sync separation over a wide temperature range without depending on the polarity of the input sync signal, the type of the sync signal, and the frequency. Therefore, when the PDP flat-panel television is used in an environment where the ambient temperature fluctuates greatly, for example, for monitoring personal computers, the NTSC (National Television Sys- tem) is used.
The system can automatically respond to various video signals other than the video signals compliant with the Tem Committee, and has the advantage that the PDP flat-panel television operates stably. In particular, since the frequency measurement unit measures the horizontal frequency based on the period of the horizontal scanning line after a predetermined number sufficiently distant from the vertical synchronization signal (VD), for example, the period of the 128th horizontal scanning line, The horizontal frequency can be accurately detected, and stable synchronization separation is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a digital sync separation circuit according to the present invention.

FIG. 2 is a schematic diagram of a signal waveform showing a process of separating a horizontal synchronization signal (b) and a vertical synchronization signal (2) from a composite synchronization signal (a) of the digital synchronization separation circuit according to the present invention.

FIG. 3 is a circuit block diagram illustrating an embodiment of a polarity discriminating unit of the digital sync separation circuit according to the present invention.

FIG. 4 shows the HD / V of the digital sync separation circuit according to the present invention.
It is a circuit block diagram showing an example of a D separation part.

FIG. 5 is a circuit block diagram showing an embodiment of a frequency measurement unit of the digital synchronization separation circuit according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Polarity discriminating part 2 First synchronous polarity inverting part 3 Second synchronous polarity inverting part 4 Frequency measuring part 5 HD / VD separating part 6 Switch part 11 First negative edge detecting part 12 First up / down counter 13 Horizontal period counter 14 OR gate 15 Second up / down counter 16 First D flip-flop 17 First RS flip-flop 18 Second negative edge detector 19 Third up / down counter 20 Second D flip-flop 21 Second RS flip-flop 31 VD removal Unit 32 L count unit 33 horizontal synchronization pulse determination unit 34 first mask signal generation unit 35 OR gate 36 vertical synchronization pulse determination unit 37 second mask signal generation unit 38 AND gate 39 VD determination unit 40 VD generation unit 51 first edge detection Part 52 first counter 53 D flip-flop Flop 54 second edge detector 55 the second counter 56 decoder 57 OR gates

Claims (6)

[Claims] 1. A polarity discriminator for detecting a polarity of a synchronization signal, a synchronization polarity inverting unit for inverting a synchronization signal to a required polarity based on a discrimination result of the polarity discrimination unit, and a synchronization via the synchronization polarity inversion unit. A digital synchronization separation circuit comprising: a frequency measurement unit that measures a horizontal frequency or a cycle of a signal; and a synchronization separation unit that separates a horizontal synchronization signal and a vertical synchronization signal from a synchronization signal based on measurement data of the frequency measurement unit. 2. A polarity discriminator for discriminating a type and a polarity of a synchronization signal, a first synchronization polarity reversing unit for reversing a horizontal synchronization signal or a composite synchronization signal to a required polarity based on a discrimination result of the polarity discrimination unit, A second synchronization polarity inversion unit that inverts the vertical synchronization signal to a required polarity based on the determination result of the polarity determination unit, a frequency measurement unit that measures the frequency or cycle of the horizontal synchronization signal of a predetermined scan number, and the composite synchronization signal , An HD / VD separation unit for extracting a horizontal synchronization signal or a vertical synchronization signal with reference to the frequency or cycle of the frequency measurement circuit, a vertical synchronization signal output from the second synchronization polarity inversion unit, and the HD / VD A digital synchronization separation circuit comprising: a vertical synchronization signal output from the separation unit; and a switch unit that selectively outputs one of the two based on the determination result of the polarity determination unit. 3. The digital synchronization separation circuit according to claim 2, wherein said frequency measuring section measures a horizontal frequency based on a period of a predetermined number of horizontal scanning lines and thereafter. 4. A method according to claim 1, wherein said polarity discriminating section loads a required initial value by a first negative edge detecting section for detecting a fall of a horizontal synchronizing signal or a composite synchronizing signal, and a trigger signal outputted by said first negative edge detecting section. A first up / down counter that counts down or up according to the logic state of the synchronization signal; a horizontal cycle counter that is enabled by the trigger signal and outputs a predetermined count value as a low logic output; An OR gate for calculating a logical sum of a predetermined logical output of the counter and the trigger signal, a required initial value loaded by a low output of the OR gate, and enabled by a trigger signal of the first negative edge detector; According to the logic state of the MSB (most significant bit) of the first up / down counter A second up / down counter for counting down or up counting, and a first D flip-flop that is enabled when the OR gate outputs a low logical sum and latches the state of the MSB (most significant bit) of the second up / down counter. A first RS flip-flop having a trigger signal of the first negative edge detector as an input to a low active R terminal and a carry of the first up / down counter as an input to an S terminal; A second negative edge detector for detecting a falling edge of the signal, and a required initial value loaded by a low logic output of the second negative edge detector, which is enabled by a trigger signal of the first negative edge detector, and the vertical Count down or count up according to the logic state of the sync signal A third up / down counter, a second D flip-flop which is enabled by a low logic output of the second negative edge detector and latches the state of the MSB (most significant bit) of the third up / down counter; 3. A second RS flip-flop, wherein a trigger signal of the second negative edge detector is input to a low active R terminal and a carry of the third up / down counter is input to an S terminal. Digital sync separation circuit. 5. An HD / VD separation section comprising: a VD removal section for removing a vertical synchronization signal from a composite synchronization signal; an L count section for measuring a low period of the composite synchronization signal; A horizontal synchronization pulse determination unit that determines a horizontal synchronization pulse based on the vertical synchronization pulse based on the measurement result of the L count unit;
A first mask signal generation unit that outputs a predetermined horizontal mask signal based on the determination result of the horizontal synchronization pulse determination unit, and a second mask signal that outputs a predetermined vertical mask signal based on the determination result of the vertical synchronization pulse determination unit A generator, and the VD
An adder (OR gate) for performing a logical OR operation of the signal output by the removing unit and the horizontal mask signal to separate a horizontal synchronization signal, and an integrator (AND gate) for performing a logical AND operation of a composite synchronization signal and the vertical mask signal ) And the integrator (A
3. A VD determining unit for determining whether an output signal of an ND gate is a vertical synchronizing signal (VD), and a VD generating unit for generating a predetermined vertical synchronizing signal from a result of the determination by the VD determining unit. Digital sync separation circuit. 6. The frequency measuring section includes a first edge detecting section for detecting rising or falling of a horizontal synchronizing signal or a composite synchronizing signal, and a second edge detecting section for detecting rising or falling of a vertical synchronizing signal. A first counter for setting an initial value based on an output of the first edge detector, and an enable being set based on an output of the first edge detector and setting an initial value based on an output of the second edge detector. A second counter, a decoder for decoding the output of the second counter, an OR gate for calculating the logical sum of the output of the decoder and the output of the first edge detection unit, and an enable by the output of the OR gate 3. The digital synchronization separation circuit according to claim 2, further comprising a flip-flop for latching an output of said first counter.