JPH10233814A - Automatic frequency control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct a frequency error of a whole packet including a packet termination part by holding the carrier frequency error detection signal value by an amount equivalent to a prescribed symbol right before no receiving signal is detected any more at the packet termination part when the carrier frequency error is corrected by means of plural symbols of a packet tip part. SOLUTION: A subtraction circuit 4 produces a phase rotation signal a5 that is proportional to the carrier frequency error of a receiving phase signal a1 on the basis of a phase angle decision signal a4 outputted from a symbol decision circuit 3. Thereafter, a carrier frequency error detection means reaching a division circuit 9 performs the integrating/averaging processing of plural symbols of a packet tip part to output the carrier frequency error signals a10. A sample hold circuit 13 holds and outputs the signals a10 in number equivalent to a prescribed number of symbols even after a receiving signal detection circuit 14 detects no signal a1 any more.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an automatic frequency control circuit for correcting a carrier frequency error of a signal received from a partner station in a receiver used in a digital radio communication system. In particular, the present invention relates to an automatic frequency control circuit suitable for wireless packet communication in which information is divided into short data packets and transmitted.

[0002]

2. Description of the Related Art Packet communication is a method in which data is converted into short packets and a signal is transmitted only when information is present. Information can be transmitted with higher efficiency than circuit-switched communication. FIG. 4 shows a configuration example of a conventional automatic frequency control circuit used for a demodulation circuit (reference: Onizawa et al.,
"A study of OLRM demodulator using vector average AFC", B-372, IEICE Society Conference, 1996).

In FIG. 1, a delay circuit 1 outputs a delay signal a2 obtained by delaying a reception phase signal a1 by one symbol period. The subtraction circuit 2 calculates the delay signal a2 from the reception phase signal a1.
And outputs a phase difference signal a3 for one symbol section. The symbol determination circuit 3 outputs a phase angle determination signal a4 that is closest to the signal determination angle when there is no noise and carrier frequency error in the phase difference signal a3. The subtraction circuit 4 subtracts the phase angle determination signal a4 from the phase difference signal a3, and outputs a phase rotation signal a5 proportional to the carrier frequency error of the phase difference signal a3.

The multiplication circuit 5 converts the phase rotation signal a5 into N
It multiplies (N is a positive integer) and outputs an N-fold phase rotation signal a6. The vector conversion circuit 6 generates and outputs an in-phase component signal a7 and a quadrature component signal a8 of a vector based on the argument of the N-fold phase rotation signal a6. Integration circuits 7-1 and 7-2
Calculates the in-phase component signal a7 and the quadrature component signal a8 by m
Symbols (m is a positive integer) are integrated and averaged. The phase detection circuit 8 detects a declination (phase) of the vector from the averaged vector and outputs a phase detection signal a9. The division circuit 9 divides the frequency of the phase detection circuit a9 by 1 / N and outputs a carrier frequency error signal a10. The integration circuit 10 is used as a variable frequency oscillating means, and continuously integrates the carrier frequency error signal a10 to output a frequency conversion reference signal a11.

On the other hand, the delay circuit 11 receives the received phase signal a1
Is output as a delayed reception phase signal a12. The subtraction circuit 12 performs frequency conversion by subtracting the frequency conversion reference signal a11 from the delayed reception phase signal a12, and outputs a carrier frequency error correction signal a13. Thereby, the carrier frequency error of the received phase signal a1 is corrected.

[0006]

In a conventional automatic frequency control circuit, when correcting a carrier frequency error of a packet (including a preambleless packet) as shown in FIG. 5, m symbols at the leading end of the packet are used. Detecting the carrier frequency error by the
One carrier frequency error can be corrected. At this time, the carrier frequency error is corrected for the delayed reception phase signal a12 obtained by delaying the reception phase signal a1 by i symbols (i is a positive integer). However, as shown in FIG. 5, when the reception phase signal a1 is not input, the carrier frequency error signal a10 falls, so that the delayed reception phase signal a1
In the case of No. 2, there was a problem that it was not possible to correct the carrier frequency error for the i symbols at the end of the packet indicated by the hatched portion.

SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic frequency control circuit which enables stable correction of a carrier frequency error over an entire packet.

[0008]

According to the conventional configuration, when correcting the carrier frequency error of a packet, the carrier frequency error signal a10 for the i symbol at the end of the packet is corrected.
Has fallen, and the carrier frequency error of the delayed reception phase signal cannot be corrected correctly. The automatic frequency control circuit according to the present invention includes a holding unit that holds the output value of the carrier frequency error detection unit at that time only for the i symbol of the reception signal when the reception signal detection unit stops detecting the reception signal. Thereby, as shown in FIG. 2, even if the received phase signal a1 is delayed by i symbols,
The carrier frequency error can be corrected for the i symbol of the packet termination part in the sample hold period of the carrier frequency error holding signal a14.

[0009]

FIG. 1 shows an embodiment of an automatic frequency control circuit according to the present invention. In the figure, a delay circuit 1 is a delay signal a obtained by delaying a reception phase signal a1 by one symbol section.
2 is output. The subtraction circuit 2 subtracts the delay signal a2 from the reception phase signal a1 to obtain a phase difference signal a for one symbol period.
3 is output. The symbol determination circuit 3 calculates the phase difference signal a
3 and outputs a phase angle determination signal a4 closest to the signal determination angle when there is no carrier frequency error. The subtraction circuit 4 subtracts the phase angle determination signal a4 from the phase difference signal a3, and outputs a phase rotation signal a5 proportional to the carrier frequency error of the phase difference signal a3.

The multiplying circuit 5 converts the phase rotation signal a5 into N
It multiplies (N is a positive integer) and outputs an N-fold phase rotation signal a6. The vector conversion circuit 6 generates and outputs an in-phase component signal a7 and a quadrature component signal a8 of a vector based on the argument of the N-fold phase rotation signal a6. Integration circuits 7-1 and 7-2
Calculates the in-phase component signal a7 and the quadrature component signal a8 by m
Symbols (m is a positive integer) are integrated and averaged. The phase detection circuit 8 detects a declination (phase) of the vector from the averaged vector and outputs a phase detection signal a9. The division circuit 9 divides the frequency of the phase detection circuit a9 by 1 / N and outputs a carrier frequency error signal a10. The configuration from the delay circuit 1 to the division circuit 9 is the carrier frequency error detection means according to the first aspect.

The carrier frequency error signal a10 output from the division circuit 9 is input to a sample and hold circuit 13 corresponding to the holding means according to the first aspect. On the other hand, the reception signal detection circuit 14 detects the reception phase signal a1 and notifies the sample / hold circuit 13 of the detection. The sample hold circuit 13 holds the value of the carrier frequency error signal a10 by i symbols when the reception phase signal a1 is no longer detected by the reception signal detection circuit 14 and the carrier frequency error signal a10 falls, and holds the carrier frequency error. Signal a
14 is output.

The integration circuit 10 used as the variable frequency oscillating means according to the first aspect of the present invention continuously integrates the carrier frequency error holding signal a14 and continues to integrate the frequency conversion reference signal a11.
Is output. On the other hand, the delay circuit 11 used as the delay means according to claim 1 outputs a delayed reception phase signal a12 obtained by delaying the reception phase signal a1 by i symbols. The subtraction circuit 12 performs frequency conversion by subtracting the frequency conversion reference signal a11 from the delayed reception phase signal a12, and outputs a carrier frequency error correction signal a13. Thereby, the carrier frequency error of the received phase signal a1 is corrected.

FIG. 3 shows simulation results of the bit error rate characteristics in the conventional configuration and the configuration of the present invention. The simulation was performed in an AWGN environment. The results are obtained when the π / 4 shift DQPSK modulation method and the synchronous detection method are used and the symbol rate is 192 kHz. From the figure, it can be seen that in the automatic frequency control circuit having the conventional configuration, the code error rate is degraded because the carrier frequency error is no longer detected at the packet termination part. On the other hand, in the automatic frequency control circuit of the present invention, it can be seen that the characteristics are improved by holding the carrier frequency error signal.

[0014]

As described above, in the automatic frequency control circuit according to the present invention, the carrier frequency error signal corresponding to the packet termination part can be held by the holding means. Can be corrected. It is also possible to correct a carrier frequency error for each packet.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an automatic frequency control circuit according to the present invention.

FIG. 2 is a diagram illustrating functions of a sample and hold circuit 13.

FIG. 3 is a diagram showing simulation results of bit error rate characteristics in the conventional configuration and the configuration of the present invention.

FIG. 4 is a block diagram showing a configuration example of a conventional automatic frequency control circuit.

FIG. 5 is a diagram illustrating a problem of a conventional automatic frequency control circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 delay circuit 2 subtraction circuit 3 symbol judgment circuit 4 subtraction circuit 5 multiplication circuit 6 vector conversion circuit 7 integration circuit 8 phase detection circuit 9 division circuit 10 integration circuit 11 delay circuit 12 subtraction circuit 13 sample hold circuit 14 reception signal detection circuit

Claims (1)

[Claims] 1. A reception signal detection unit for detecting a reception signal, a carrier frequency error detection unit for detecting a carrier frequency error from the reception signal, and when a reception signal is no longer detected by the reception signal detection unit, Holding means for holding the output value of the carrier frequency error detecting means at the time of i symbols of the received signal; variable frequency for outputting a signal having a frequency corresponding to the output of the carrier frequency error detecting means and the output of the holding means Oscillating means; delay means for delaying the received phase signal by the i symbol; carrier frequency error correction means for frequency-converting the received signal delayed by the delay means using an output signal of the variable frequency oscillating means; An automatic frequency control circuit comprising: