JP2000188620A - Synchronous detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance processing speed in a synchronization detector in digital mobile communication. SOLUTION: A phase information generator 101 coverts a phase difference which depends on a quadrant, in which a phase discriminated on the basis of an absolute value of an in-phase component and an absolute value of a quadrature component of a received signal is in existence, so as to calculate phase information of the received signal simply and a phase information generator 102 calculates phase information of a pilot symbol similarly, and a subtractor 103 calculates phase fluctuation due to fading by subtracting the phase information of the received signal and a phase of the pilot symbol, and a subtractor 104 calculates a synchronization detecting signal by subtracting phase fluctuation due to fading and the phase information of the received signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous detection device used for digital mobile communication.

[0002]

2. Description of the Related Art The construction and operation of a synchronous detector will now be described with reference to FIG. FIG. 9 is a block diagram showing a configuration of the synchronous detector. The digital multiplier 901 multiplies the input signal by a known pilot symbol. The conjugate complex number generator 903 generates a conjugate complex number of the input signal based on the result of the multiplication. The digital multiplier 902 is
Multiply the conjugate complex number with the input signal.

As shown in FIG. 10, generally, in a frame format, a known pilot symbol is added before a message. In a general synchronous detection method, fading fluctuation is detected using this pilot symbol.

In this synchronous detection, first, in the pilot symbol section, a signal representing fluctuation due to fading is obtained by multiplying the input signal by the pilot symbol.

Here, the input signal In (nT) in the pilot symbol section is expressed as: In (nT) = P (nT) · A (nT) · exp (jΘ)
(NT)). Here, P (nT) is a pilot symbol, A (nT) is amplitude fluctuation due to fading, and exp (jΘ (nT)) is phase fluctuation due to fading.

Also, a signal F representing a change due to fading is shown in FIG.
(NT) is: F (nT) = {P (nT) · A (nT) · exp (jΘ (nT))} · P (nT) = P (nT) ² · A (nT) · exp (jΘ ( nT))-. Here, in a modulation method such as a QPSK modulation method in which the amplitude is constant and only the phase has information, since P (nT) ² = 1, the equation is as follows: F (nT) = A (nT) Exp (jΘ (nT)).

[0007] The conjugate complex number generator 903
Conjugate complex based on the signal F (nT) representing the variation due to
Prime F (nT)^*Generate The generation of conjugate complex numbers is
Performed by inverting the polarity of the Q component of the input signal
It is. Conjugate complex number F (nT) ^*Is represented by the following formula
Can be. F (nT)^*= A (nT) · exp (-jΘ (nT))

Finally, the input signal and the conjugate complex number generator 9
The digital multiplier 902 multiplies the conjugate complex number of the signal representing the fluctuation due to fading, which is the output of 03, to obtain a synchronous detection signal.

Here, assuming that the fading fluctuation is sufficiently slower than the interval between the pilot symbols and the fading fluctuation is constant between the pilot symbol and the pilot symbol.
D _out (nT) representing the synchronous detection signal can be represented by the following equation. D _out (nT) = D _in (nT) · A (nT) · exp (jΘ (nT)) · A (nT) · exp (−jΘ (nT)) = D _in (nT) · A (nT) ² -Here, since A (nT) ² has a constant phase and represents a fluctuation of only the amplitude, the phase information of the synchronous detection signal D _out (nT) is represented only by D _in (nT). Therefore, in the equation, it can be said that the phase of the received signal could be demodulated. Since the QPSK modulation method is a modulation method in which the amplitude is constant and only the phase has information, the synchronous detection is completed by demodulating the phase information in this manner.

[0010] In addition, phase fluctuations due to phase differences between transmission and reception carriers and frequency offsets can be removed in the same manner as fading fluctuations.

In a modulation method such as a 16QAM modulation method, in which both the phase and the amplitude have information, the fading fluctuation is detected by dividing the input signal in the pilot symbol section by the pilot symbol. Is divided by the signal representing the detected fading fluctuation, synchronous detection can be performed.

[0012]

However, the conventional apparatus has the following problems. That is,
Since the processing speed of the synchronous detector is limited by the processing of the multiplier with the slow processing speed, the conventional synchronous detector using the multiplier is:
It is difficult to increase the processing speed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a synchronous detection device that improves the processing speed.

[0014]

The gist of the present invention is to simply convert the phase difference by the quadrant to which the phase belongs based on the absolute value of the in-phase component and the absolute value of the quadrature component of the received signal, and to easily obtain the phase information of the received signal. Is calculated, and the phase information due to fading is calculated by subtracting the phase information of the received signal from the phase of the pilot symbol, and the synchronous detection is performed by subtracting the phase information due to fading from the phase information of the received signal. Calculate the signal.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

According to a first aspect of the present invention, there is provided a synchronous detection apparatus comprising: a phase detection unit configured to detect a phase of a received signal and a known reference signal; a phase detection unit configured to detect a phase of the received signal detected by the phase detection unit; Phase fluctuation detecting means for detecting a phase fluctuation due to fading from a difference from the phase.

According to this configuration, since synchronous detection can be performed without performing multiplication and division, the amount of calculation can be reduced, the apparatus can be simplified, and the signal processing speed of the apparatus can be improved.

In the synchronous detection apparatus according to a second aspect of the present invention, in the first aspect, the phase detection means may include a quadrant determination section for determining a quadrant to which a phase of the received signal belongs, A configuration including a phase determination unit that determines the phase of the received signal from the difference between the absolute value and the absolute value of the orthogonal component and the output of the quadrant determination unit is adopted.

According to this configuration, since the phase can be calculated without multiplication / division, the amount of calculation can be reduced, the apparatus can be simplified, and the signal processing speed of the apparatus can be improved.

In the synchronous detection apparatus according to a third aspect of the present invention, in the synchronous detection apparatus according to the second aspect, the quadrant judging section judges by using a difference between an absolute value of an in-phase component and an absolute value of a quadrature component of the received signal. Is adopted.

According to this configuration, since the quadrant to which the phase of the received signal belongs can be determined without performing multiplication / division, the amount of calculation can be reduced, the apparatus can be simplified, and the signal processing speed of the apparatus can be improved.

According to a fourth aspect of the present invention, in the synchronous detection apparatus according to any one of the first to third aspects, the phase detecting means may include an absolute value of an in-phase component and an absolute value of a quadrature component of the received signal. A first adder for adding a value obtained by multiplying the smaller value by 0.25 and a value obtained by multiplying the smaller value of the absolute value of the in-phase component and the absolute value of the quadrature component of the received signal by 0.125; A second adder for adding the output of the first adder, the larger of the absolute value of the in-phase component and the absolute value of the quadrature component of the received signal, and the amplitude calculated by the second adder And a normalization unit that normalizes the input signal by using.

According to this configuration, the amplitude can be calculated and the normalization process can be performed with a small amount of calculation without calculating the sum of squares of the in-phase component and the quadrature component. Processing speed is improved. In addition, since the synchronous detection device has a normalization processing function, it can support more communication modes.

According to a fifth aspect of the present invention, in the synchronous detection apparatus according to any one of the first to fourth aspects, the phase variation detection section averages the calculated phase variation due to fading and outputs the averaged phase variation. It adopts the configuration to do.

According to this configuration, the accuracy of detecting the fluctuation due to fading is improved, so that the error rate characteristic can be improved and the line quality can be improved.

According to a sixth aspect of the present invention, there is provided a terminal device for a mobile communication system comprising the synchronous detection device according to any one of the first to fifth aspects.

According to this configuration, each communication device used in the mobile communication is simplified and the signal processing speed of the device is improved.

A synchronous detection method according to a seventh aspect of the present invention includes a phase detecting step of detecting the phases of a received signal and a known reference signal, and a phase of the received signal detected by the phase detecting step and a known reference signal. A phase variation detecting step of detecting a phase variation due to fading from a difference from the phase.

According to this method, since synchronous detection can be performed without performing multiplication and division, the amount of calculation can be reduced, the apparatus can be simplified, and the signal processing speed of the apparatus can be improved.

According to an eighth aspect of the present invention, in the synchronous detection method according to the seventh aspect, the phase detecting step includes a quadrant determining step of determining a quadrant to which a phase of the received signal belongs, and a quadrant determining step of the in-phase component of the received signal. A phase determining step of determining the phase of the received signal from the difference between the absolute value and the absolute value of the orthogonal component and the output of the quadrant determining step.

According to this method, since the phase can be calculated without multiplication and division, the amount of calculation can be reduced, the apparatus can be simplified, and the signal processing speed of the apparatus can be improved.

[0032] In a synchronous detection method according to a ninth aspect of the present invention, in the eighth aspect, the quadrant determination step is performed by using a difference between an absolute value of an in-phase component and an absolute value of a quadrature component of the received signal. To do.

According to this method, since the quadrant to which the phase of the received signal belongs can be determined without multiplication and division, the amount of calculation is reduced, the apparatus can be simplified, and the signal processing speed of the apparatus can be improved.

According to a tenth aspect of the present invention, in the synchronous detection method according to any one of the seventh to ninth aspects, the phase detecting step comprises the steps of: detecting an absolute value of an in-phase component of the received signal; A first adding step of adding a value obtained by multiplying the smaller value by 0.25 times and a value obtained by multiplying the smaller value of the absolute value of the in-phase component and the absolute value of the quadrature component of the received signal by 0.125 times A second addition step of adding the output of the first addition step and the larger of the absolute value of the in-phase component and the absolute value of the quadrature component of the received signal; and the amplitude calculated in the second addition step. And a normalization step of normalizing the input signal by using.

According to this method, the amplitude can be calculated and the normalization process can be performed with a small amount of calculation without calculating the sum of squares of the in-phase component and the quadrature component. Processing speed is improved. In addition, since the synchronous detection device has a normalization processing function, it can support more communication modes.

The synchronous detection method according to the eleventh aspect of the present invention is the synchronous detection method according to any one of the seventh to tenth aspects, wherein
In the phase variation detecting step, the calculated phase variation due to fading is averaged and then output.

According to this method, the accuracy of detecting the fluctuation due to fading is improved, so that the error rate characteristic can be improved and the line quality can be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In any of the following embodiments, a case will be described in which the input signal is a QPSK-modulated signal, the input signal has the frame format shown in FIG. 10, and the known reference signal is a pilot symbol.

(Embodiment 1) A synchronous detection apparatus according to Embodiment 1 of the present invention has a reduced circuit scale without using a multiplier and a memory.

Hereinafter, the synchronous detection apparatus according to the present embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of the synchronous detection device according to Embodiment 1 of the present invention.

The phase information generators 101 and 102 calculate the phase by a simple operation without using a multiplier or a memory. Details will be described later.

The subtractor 103 subtracts the phase of the output of the phase information generator 101 from the phase of the pilot symbol output from the phase information generator 102 to obtain a phase variation due to fading.

Next, the subtractor 104 calculates the phase information of the input signal output from the phase information generator 101 and the subtractor 103.
Is subtracted from the phase fluctuation due to fading, which is the output of. Here, if the fading fluctuation of the synchronous detection signal is sufficiently slower than the interval between the pilot symbols and the fading fluctuation is constant between the synchronous detection signal and the pilot symbol, the input which is the output of the phase information generator 101 By calculating the phase difference between the phase information of the signal and the phase fluctuation due to fading detected using the pilot symbol output from the subtractor 103, a synchronous detection signal can be obtained.

Hereinafter, the phase information generator of the synchronous detection apparatus according to the present embodiment will be described with reference to FIG. FIG.
FIG. 3 is a block diagram showing a configuration of a phase information generator of the synchronous detection device according to Embodiment 1 of the present invention. The phase information generator according to the present embodiment reduces the number of operations for obtaining a phase.

The I and Q components of the input signal are subjected to absolute value detection by absolute value detectors 201 and 202, respectively, and output to a subtractor 203.

The I and Q components of the input signal are input to the quadrant determiner 204, where the quadrant is determined. Hereinafter, the quadrant determiner 204 will be described in detail.

When the phase is obtained from the I component and the Q component of the input signal, it is necessary to calculate the phase Θ = arctan (Q / I) of the input signal, and this arctan (Q / I)
Can be approximated based on the following equation: arctan (Q / I) = | I | − | Q | −

FIG. 3 shows arctan (Q / I) and | I |
6 is a graph showing a relationship with − | Q |. Like this
= | I |-| Q |, the error can be kept within 1.8 °.

The quadrant judging unit 204 judges that if | I | − | Q | {−4} / π + 1 is the first quadrant based on the above approximation formula, and similarly, | I | − | Q ｜ {4} /
If π-3, the second quadrant, | I |-| Q | {-4} / π
If -3, the third quadrant, | I |-| Q | {4} / π + 1
If so, it is determined to be the fourth quadrant.

Next, the converter 205 converts the output of the subtractor 203 according to the judgment result of the quadrant judging unit 204 to obtain the phase Θ.

As described above, according to the present embodiment, in the synchronous detector, arctan is used by using the multiplier and the memory.
By performing the subtraction of | I | and | Q | and determining the quadrant to which the phase belongs instead of performing the calculation of (Q / I), it is possible to reduce the required calculation amount and reduce the circuit scale.

As described above, according to the present embodiment, the synchronous detector does not perform the operation using the multiplier and the memory, but performs the synchronous detection using the phase obtained by the simple operation. The amount of operation can be reduced, and the circuit scale can be reduced.

(Second Embodiment) A synchronous detector according to a second embodiment of the present invention has a configuration similar to that of the synchronous detector according to the first embodiment, except that the absolute value of the I component and the Q component is enveloped. The line information is approximately calculated, and the input signal is normalized using the envelope information.

Hereinafter, the phase information generator of the synchronous detection apparatus according to the present embodiment will be described with reference to FIG. FIG.
FIG. 7 is a block diagram showing a configuration of a phase information generator of the synchronous detection device according to Embodiment 2 of the present invention. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted.

The I and Q components of the input signal are input to an envelope generator 401, and envelope information is calculated. Next, the normalization circuit 402 normalizes the input signal using the calculated envelope information. The converter 205 converts the normalized input signal according to the determination result of the quadrant determiner 204,
Obtain phase information.

Hereinafter, the configurations and operations of the envelope generator 401 and the normalization circuit 402 will be described in detail.

The envelope information Z is expressed as follows: Z = √ (| I | ² + | Q
| ² ), but obtaining a sum of squares requires a relatively large amount of calculation. Therefore, it is conceivable to perform an approximate calculation with Z = | I | + | Q | so that only a small amount of calculation is required.
°), an error of 1.414 times the value calculated by the sum of squares √ (| I | ² + | Q | ² ), that is, about 41% occurs, and the error rate characteristic deteriorates.

Therefore, in this embodiment, an approximation formula using multiplication which can be easily performed by bit shifting is used. That is, when | I |> | Q |, Z = | I | +
0.375 × | Q |, when | Q |> | I |, Z = | Q
| + 0.375 × | I | is used as an approximate expression.

FIG. 5 shows that | I |> | Q
FIG. 6 is a graph showing the results obtained by theoretical calculation of the relationship between the phase θ and the estimated radius, that is, the amplitude, in the case of |, that is, in the range of 0 ≦ θ ≦ 45 °. From this graph, it can be seen that the use of the above-described approximate expression enables envelope information to be obtained with an error of 7% or less as compared with the case where the square sum is obtained.

Hereinafter, the envelope generator 401 for obtaining envelope information using the above approximate expression will be described with reference to FIG. FIG. 6 is a block diagram showing a configuration of the envelope generator according to Embodiment 2 of the present invention.

The I and Q components of the input signal are input to absolute value detectors 601 and 602. Absolute value detector 601,
602 takes the absolute value of the input signal and outputs it to the subtractor 605 and the adder 610. Selection of the I component and the Q component is performed by switches 603 and 604. The result of the subtraction by the subtractor 605 is determined by the determiner 606, and the result of the determination is reflected in the control of the switches 603 and 604.

The 2-bit shifter 607 and 3-bit shifter 608 shift the output of the switch 604 by 2 bits and 3 bits, respectively. The outputs of the 2-bit shifter 607 and the 3-bit shifter 608 are added by an adder 609. Thereby, 0.3 in the above approximate expression is obtained.
A multiplication process of 75 is performed. The adder 610 adds the output of the switch 603 and the output of the adder 609, and outputs envelope information.

Next, the operation of the phase information generator of the synchronous detection apparatus according to the present embodiment will be described.

The absolute values of the I component and the Q component are detected by absolute value detectors 601 and 602, respectively.
Q | is obtained.

Next, the outputs (| I | and | Q |) of the absolute value detectors 601 and 602 are subjected to a subtraction process in a subtractor 605, and the output of the subtractor 605 makes a magnitude judgment.
The outputs of the absolute value detectors 601 and 602 (| I | and | Q
|) Is selected and output by switches 603 and 604, respectively. The switches 603 and 604 are connected to the decision unit 6
A signal to be output is selected according to the result of the determination in step 06.

The switch 603 outputs | I | if the output of the decision unit 606 is | I |> | Q |, and | Q |> | I
If |, | Q | is output. The switch 604 outputs | Q | when the output of the decision unit 606 is | I |> | Q |, and outputs | I | when | Q |> | I |. That is, the switch 603 outputs the larger of | I | and | Q |, and the switch 604 outputs the smaller of | I | and | Q |.

Next, the signal | output from the switch 604 is output.
The smaller of I | and | Q | is shifted by 2 bits and 3 bits by 2-bit shifter 607 and 3-bit shifter 608, respectively.

Since the amplitude is halved by the 1-bit shift, the amplitude is 0.25 times for the 2-bit shift and 0.125 times for the 3-bit shift. Therefore, the 2-bit shifter 6
The amplitude of the output signal of 07 is 0.25 times the amplitude of the output signal of the switch 604, and the amplitude of the output signal of the 3-bit shifter 608 is 0.125 times the amplitude of the output signal of the switch 604.

Next, the adder 609 outputs the output signal of the 2-bit shifter 607 (0.25 × | I | or 0.25 × |
Q |) and the output signal of the 3-bit shifter 608 (0.12
5 × | I | or 0.125 × | Q |)
The output signal of the adder 609 is 0.375 × | I | or 0.375 × | Q |.

Finally, the adder 610 sets the switch 603
Output signal (| I | or | Q |) and the output signal of the adder 609 (0.375 × | I | or 0.375 × | Q |).
Are added to obtain envelope information Z based on the approximate expression.

As described above, the envelope information generator according to the present embodiment does not perform the sum-of-squares operation in the calculation of the envelope, and can perform simple multiplication and addition that can be realized by a bit shift on a circuit. Since an approximation formula consisting of only the above is used, a multiplier and a memory are not required, the apparatus can be simplified, and the required amount of calculation can be reduced.

Next, a normalization circuit 402 included in the phase information generator of the synchronous detection apparatus according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 7 is a block diagram illustrating a configuration of the normalization circuit according to the present embodiment.

The determiners 701 to 704 determine whether the phase is larger or smaller than π / 4.
Reference numerals 05 to 707 add the bit-shifted input signal and an envelope signal whose polarity is inverted or not in accordance with the result of the immediately preceding determiner.

By adopting such a configuration, it is possible to remove the information of the envelope from the input signal. The output of the determiner 701 indicates whether the phase of the input signal is greater than or less than π / 4. Similarly, the output of the determiner 702 is greater than or less than π / 8, and the output of the determiner 703 is π / 1.
6 or less, and the output of the decision unit 704 indicates whether it is π / 32 or more.

Here, the case where the output normalized signal is composed of 4 bits has been described. However, an arbitrary number of determiners and arithmetic units can be provided, and the greater the number, the higher the accuracy.
Also, as is clear from FIG. 7, the number of arithmetic units must be equal to the number of decision units minus one.

As described above, according to the present embodiment, by performing normalization in the phase information generator of the synchronous detector, it is possible to cope with more communication modes than in the first embodiment.

(Embodiment 3) A synchronous detection apparatus according to Embodiment 3 of the present invention has the same configuration as that of the synchronous detection apparatus according to Embodiment 1, except that the phase difference between the input signal and the pilot symbol is reduced. By averaging, the error rate characteristics are improved.

Hereinafter, the synchronous detection apparatus according to the present embodiment will be described with reference to FIG. FIG. 8 is a block diagram illustrating a configuration of a synchronous detection apparatus according to Embodiment 3 of the present invention. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted.

In the synchronous detection apparatus according to the present embodiment, the averaging circuit 801 is the subtractor 103, that is, the phase information of the input signal output from the phase information generator 101 and the output of the phase information generator 102. The difference from the pilot symbol phase information is averaged. As a result, it is possible to improve the detection accuracy of the line fluctuation due to fading, so that the error rate characteristics can be improved.

As described above, according to the present embodiment, the synchronous detector does not perform the operation using the multiplier and the memory, but performs the synchronous detection using the phase obtained by the simple operation. The amount of computation can be reduced and the circuit scale can be reduced, and at the same time, the averaging improves the detection accuracy of the line fluctuation due to fading. Therefore, the error rate characteristic is higher than that of the synchronous detection apparatus according to the first embodiment. Can be improved.

In the first to third embodiments, the case where the input signal is a QPSK-modulated signal has been described. However, the present invention is applied to the case where the input signal is processed by the I component and the Q component. Can be. Further, the known reference signal is not limited to the pilot symbol.

In the first to third embodiments,
Although phase detection in a synchronous detector has been described, a similar configuration and method for phase detection can be used for a delay detector. Note that the synchronous detection device of the present invention is used as a transmission / reception device in mobile communication regardless of the communication method, and contributes to miniaturization, cost reduction, and improvement in processing speed of the device.

As described above, according to the present invention,
The processing speed can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a synchronous detection apparatus according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a movement information generator of the synchronous detection device according to the first embodiment of the present invention.

FIG. 3 is a graph showing a theoretical calculation result of an approximate phase calculation used in the synchronous detection device according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a phase information generator of a synchronous detection device according to Embodiment 2 of the present invention.

FIG. 5 is a graph showing a theoretical calculation result of an approximate expression for calculating envelope information used in the synchronous detection device according to the second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of an envelope generator according to Embodiment 2 of the present invention.

FIG. 7 is a block diagram showing a configuration of a normalization circuit according to the present embodiment.

FIG. 8 is a block diagram showing a configuration of a synchronous detection apparatus according to Embodiment 3 of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional synchronous detector.

FIG. 10 is a schematic diagram showing a frame format.

[Explanation of symbols]

 101, 102 Phase information generator 201, 202 Absolute value detector 204 Quadrant discriminator 205 Transformer 401 Envelope generator 402 Normalization circuit 607 2-bit shifter 608 3-bit shifter

Claims (11)

[Claims] 1. A phase detecting means for detecting the phases of a received signal and a known reference signal, and a phase variation due to fading is detected from a difference between the phase of the received signal detected by the phase detecting means and the phase of the known reference signal. And a phase fluctuation detecting means. 2. A quadrant judging unit for judging a quadrant to which a phase of a received signal belongs, a difference between an absolute value of an in-phase component and an absolute value of a quadrature component of the received signal, and an output of the quadrant judging unit. 2. The synchronous detection device according to claim 1, further comprising: a phase determination unit that determines a phase of the reception signal from the received signal. 3. The synchronous detection device according to claim 2, wherein the quadrant determination unit performs the determination using a difference between an absolute value of an in-phase component and an absolute value of a quadrature component of the received signal. 4. The phase detecting means sets the smaller of the absolute value of the in-phase component and the absolute value of the quadrature component of the received signal to 0.2.
A first adder for adding the value multiplied by 5 and a value obtained by multiplying the smaller of the absolute value of the in-phase component and the absolute value of the quadrature component of the received signal by 0.125, and the output of the first adder And a second adder that adds the absolute value of the in-phase component and the greater of the absolute value of the quadrature component of the received signal, and normalizes the input signal using the amplitude calculated by the second adder. A normalization unit to perform;
The synchronous detection device according to any one of claims 1 to 3, further comprising: 5. The synchronous detection apparatus according to claim 1, wherein the phase fluctuation detection section averages and outputs the calculated phase fluctuation due to fading. 6. A terminal device for a mobile communication system, comprising: the synchronous detection device according to claim 1. Description: 7. A phase detecting step for detecting the phases of the received signal and the known reference signal, and detecting a phase variation due to fading from a difference between the phase of the received signal detected by the phase detecting step and the phase of the known reference signal. A synchronous fluctuation detection step. 8. The quadrant judging step for judging a quadrant to which a phase of a received signal belongs, a difference between an absolute value of an in-phase component and an absolute value of a quadrature component of the received signal, and an output of the quadrant judging step. 8. A synchronous detection method according to claim 7, further comprising the step of: 9. The synchronous detection method according to claim 8, wherein in the quadrant determination step, the determination is performed using a difference between an absolute value of an in-phase component and an absolute value of a quadrature component of the received signal. 10. The phase detecting step sets the smaller of the absolute value of the in-phase component and the absolute value of the quadrature component of the received signal to 0.
A first addition step of adding a value multiplied by 25 and a value obtained by multiplying the smaller of the absolute value of the in-phase component and the absolute value of the quadrature component of the received signal by 0.125, and an output of the first addition step When,
A second addition step of adding the absolute value of the in-phase component of the received signal and the larger value of the absolute value of the quadrature component, and normalization of normalizing the input signal using the amplitude calculated in the second addition step. The synchronous detection method according to any one of claims 7 to 9, further comprising: 11. The synchronous detection method according to claim 7, wherein in the phase variation detecting step, the calculated phase variation due to fading is averaged and then output.