JPH10303794A - Known system detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it difficult to be affected by fluctuations of a reception signal level due to phasing and to satisfactorily detect a known system by providing a diversity synthesis means weighting a correlation value, in accordance with a signal level received at every branch and synthesizing weighting results. SOLUTION: Correlation calculation parts 40A and 40B calculate correlations between the in-phase/orthogonal components of the reception signals of respective branches 1 and 2 and the in-phase/orthogonal components in a known system. The correlation value which is an output is inputted to a diversity synthesis part 50. The diversity synthesis part 50 weights and adds the correlation value of the branches 1 and 2 by the signal level, being the outputs of the signal level detectors 60A and 60B. A judgment part 140A compares the synthesized correlation value obtained in the diversity synthesis part 50 with the size of the output of a threshold calculation part 150. Then, the position of the known system in a frame is known, based on the output of a judgment part 140A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a known sequence detector in the field of wireless communication systems.

[0002]

2. Description of the Related Art A conventional known sequence detector is described, for example, in the document "Japanese Patent Laid-Open No. 05-191208, Adaptive Equalizer and Receiver". Hereinafter, the related art will be described with reference to the drawings.

FIG. 2 shows a configuration of a conventional known sequence detector.
This will be described with reference to FIG. Here, a configuration in the case of quaternary PSK will be described as an example of a digital modulation signal. In the figure, reference numeral 10 denotes an antenna unit in the receiving apparatus, 20 denotes a quasi-synchronous detector that converts an RF signal received by the antenna into a baseband signal, and 30 denotes a digital signal that outputs the in-phase component of the received signal output from the quasi-synchronous detector. An A / D converter 31 for converting the signal into an A / D signal;
A converter 100 is a known sequence detector that detects a known sequence in a transmitted frame.

FIG. 23 is a block diagram showing the internal configuration of the quasi-synchronous detector 20 of FIG. 21 is an oscillator having substantially the same frequency as the received signal, 22 is a phase shifter that shifts the phase of the output of the oscillator 21 by -90 degrees, and 23 is a receiver that multiplies the received signal by the output of the oscillator 21 to receive the signal. A multiplier used to extract the in-phase component of the signal, 2
4 is a multiplier used to extract the quadrature component of the received signal by multiplying the received signal by the output of the phase shifter 22; 25 is extracting only the baseband in-phase signal from the output of the multiplier 23 26 is a multiplier 2
4 is a low-pass filter that extracts only a baseband orthogonal signal from the output of the fourth filter.

FIG. 24 shows a known sequence detector 100 shown in FIG.
FIG. 2 is a block diagram showing an internal configuration of the device. Reference numeral 101 denotes a correlator for correlating the in-phase component of the received signal converted to a digital signal with the in-phase component of the known sequence. Reference numeral 102 denotes a correlation for correlating the in-phase component of the received signal to the digital signal with the quadrature component of the known sequence. 103, a correlator for correlating the quadrature component of the received signal converted to a digital signal with the quadrature component of the known sequence; 104, a correlator for calculating the correlation between the quadrature component of the digital signal and the in-phase component of the known sequence Correlator to calculate, 1
Reference numeral 10 denotes an adder that adds the output of the correlator 101 and the output of the correlator 103, and 111 denotes a subtractor that subtracts the output of the correlator 102 and the output of the correlator 104. 120 is a squaring circuit that multiplies the output of the adder 110, 121 is a squaring circuit that multiplies the output of the subtractor 111, 130 is an adder that adds the outputs of the two squaring circuits 120 and 121, and 140 is an adder. The correlation output which is the output of 130 is compared with a preset threshold value, and when the correlation output is equal to or greater than the threshold value, a detection pulse is output as a detection of a known sequence,
If the correlation output is smaller than the threshold value, the determination unit does not output the detection pulse.

Hereinafter, the operation of the known sequence detector will be described with reference to FIGS. 22, 23 and 24. Here, a case of four-level PSK will be described as an example of a digital modulation signal. The received RF signal is subjected to quasi-synchronous detection in the quasi-synchronous detection unit 20 and converted into an in-phase / quadrature-component baseband signal. The baseband signal of the in-phase and quadrature components of the quasi-synchronously detected received signal is represented by the following expression (1) in complex notation. R (t) = A (t) · exp {j (Δωt + θ (t) + Δθ)} = A (t) · {a (t) + jb (t)} · exp {j (Δωt + Δθ)} (1) Here Where A (t) is the amplitude, Δω is the oscillation frequency difference between the center frequency of the received signal and the local oscillator for quasi-synchronous detection, Δθ is the initial phase difference between the received signal and the local oscillator output, and θ (t) is the modulation component. , A (t) and b (t) are baseband signals of in-phase and quadrature components, respectively. For simplicity, assuming that Δω = 0 and A / D converters 30 and 31 are sampled at the Nyquist point at the symbol rate, the outputs of A / D converters 30 and 31 are expressed by the following equation (2). . R (nT) = A (nT) · {a (nT) + j b (nT)} · exp {j (Δθ)} (2)

[0007] R (nT) is input to a known sequence detector. The real part (in-phase component) of R (nT) input to the known sequence detector 100 is a correlator 101 and a correlator 102 shown in FIG.
Is input to On the other hand, the imaginary part (orthogonal component) of R (nT) is input to correlator 103 and correlator 104.

Here, the known sequence K (i) referred to by the correlators 101, 102, 103 and 104 inside the known sequence detector 100 is shown by the following equation. K (i) = K _r (i) −j K _q (i) (3) where i = 1 to N, N is a known sequence length (symbol) where K _r (i) is an in-phase component of the known sequence , K _q (i) indicates a sequence of orthogonal components of a known sequence. Next, at time nT, the data stored in the i-th shift register in the correlators 101, 102, 103, and 104 are shown below. R _n (i) = A _n (i) · {a _n (i) + j b _n (i)} · exp {j (Δθ)} (4)

The known sequence detector 100 performs a process corresponding to the complex correlation operation of the equations (3) and (4). The following equation (5)
Shows the processing.

[0010]

(Equation 1)

Here, Cr _n and Cq _n represent the real part and the imaginary part of the complex correlation output C _n , and X _n and Y _n in equation (5) are expressed by the following equation (6). You.

[0012]

(Equation 2)

Here, the real part (Cr _n ) and the imaginary part (Cq _n ) of C _n
Corresponds to the output of the adder 110 and the output of the subtractor 111. The real part (Cr _n ) and the imaginary part (Cq _n ) of Cn are squared in squaring circuits 120 and 121, respectively. The obtained two square outputs are added in the adder 130. The output Z _n of the adder 130 is given by the following equation. Z _n = (Cr _n ) ² + (Cq _n ) ² = {X _n cos (Δθ) −Y _n sin (Δθ)} ² + {X _n sin (Δθ) + Y _n cos (Δθ)} ² (7)

Here, for the sake of simplicity, it is assumed that the received signal has no noise, and the known sequence K (i) is K _r (i) = ±
1. It is assumed that K _q (i) = 1, i = 1 to N. Also,
That the amplitude of the received signal takes a predetermined value _{A (A n (i) =} A) and to each phase and quadrature _{components, a n (i) = ±} 1, b n (i) =
Assuming that ± 1 and i = 1 to N, the correlation output when the received signal matches the known sequence is Z _nc , and the correlation output Z
_nc is expressed by the following equation (8). Z _nc = {X _n cos (Δθ) −Y _n sin (Δθ)} ² + {X _n sin (Δθ) + Y _n cos (Δθ)} ² = 4N ² A ² (8)

The correlation output Z _n obtained is input to the determination unit 140 whether it has detected the known sequence. In decision 140, it is compared with a preset correlation output Z _n which is the output of the adder 130 threshold D _th (constant). Here, the determiner 140 outputs a detection pulse _DT as a determination result according to the following equation. D _T = 1 (Z _n ≧ D _th ) = 0 (Z _n <D _th ) (9) Based on the output D _T of the decision unit 140 obtained by the above processing, the position of the known sequence in the frame is known. Frame synchronization control is performed.

[0016]

In the case of mobile communication, radio waves are reflected, diffracted, or scattered depending on the surrounding buildings or terrain, and waves (multipath waves) passing through a plurality of transmission paths are transmitted to the mobile station. Rayleigh fading occurs in which the amplitude and phase of the received waves fluctuate randomly because they arrive and interfere with each other. However, if the transmission rate is increased to increase the amount of information to be transmitted, the delay time difference between a plurality of waves arriving at the mobile station is not negligible with respect to the symbol length of the transmission signal, so that the propagation path becomes frequency selective. Is affected by frequency selective fading. The amplitude and phase fluctuations of each frequency component of the received wave affected by this influence are not uniform, and the transmission path characteristics are significantly deteriorated. In the transmission path of frequency selective fading, the signal amplitude of each arriving wave (the ratio between the direct wave and the delayed wave), the delay spread indicating the delay time difference and its standard deviation are greatly affected by surrounding features, It is not uniquely determined. As a measure against frequency selective fading, data demodulation is generally performed using an adaptive equalizer. In the case of an adaptive equalizer, the state of the transmission path is estimated using a known sequence (training sequence) in a frame, and the received signal is equalized. For this reason, the position of the known sequence must be known on the receiving side, and frame synchronization needs to be established in order for the adaptive equalizer to operate normally. However, there is a problem that it is difficult to operate the adaptive equalizer normally because the position of the known sequence is not known at the time of initial acquisition and handoff when frame synchronization is not established.

When frame synchronization is not established (asynchronously), the position of the known sequence (training sequence) is not known, so that the receiving side needs a function to detect the position of the known sequence. However, since it is difficult to demodulate data transmitted without an adaptive equalizer on a transmission path in which the level of a high-speed received signal fluctuates under frequency selective fading, it is difficult to detect a known sequence. There was a problem that it was difficult.

Furthermore, when asynchronous, in order to establish frame synchronization, the receiving side generally adjusts the timing of the position of the received frame while detecting a known sequence using a known sequence detector (such as a digital correlator). Specifically, when a known sequence is detected once by the known sequence detector, control for frame synchronization is performed so that the known sequence can be continuously detected at the same time position as the detection time position in a plurality of subsequent frames. Is performed. During this frame synchronization control, depending on the state of the transmission path and the performance of the known sequence detector for detecting the known sequence, the known sequence may not be detected at the normal position despite the known sequence (the known sequence may not be detected). On the other hand, when a transmission burst has not arrived, or even when a transmission burst has arrived, detection is performed at a position where a known sequence such as a transmission information portion in a frame does not originally exist (known sequence is erroneously detected). There is. In particular, in the case of a frequency selective fading transmission path having a large delay spread, the rate of non-detection of a known sequence (known sequence non-detection rate) increases. There is a problem that the ratio of erroneous detection (known sequence erroneous detection ratio) increases. Therefore, there is a problem that the frame synchronization control cannot be performed normally or that it takes time until the frame synchronization is established because the known sequence cannot be detected at a regular position in the frame.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. In a fading transmission line that collectively includes the Rayleigh fading and the frequency-selective fading, the ratio of a direct wave to a delayed wave and the magnitude of delay spread are large. Accordingly, an object of the present invention is to obtain a known sequence detector that can accurately detect a known sequence without operating an adaptive equalizer even when the state of a transmission path is different.

In the case of mobile communication, the received signal level fluctuates greatly under the influence of fading. Even in such a case, the known sequence non-detection rate is reduced and the known sequence is reduced so that frame synchronization can be normally established. It is an object of the present invention to obtain a known sequence detector with a low false detection rate.

[0021]

A known sequence detector according to a first aspect of the present invention comprises: a correlation calculating means for calculating a correlation between a plurality of received signals obtained by a plurality of antennas and a known sequence;
Diversity combining means for performing diversity combining using the correlation values of a plurality of branches obtained by the correlation calculating means, threshold calculating means for calculating a threshold for detecting a known sequence, and the diversity combining means Determining means for determining whether or not the correlation value after diversity combining obtained by the above is larger than the threshold value obtained by the threshold value calculating means.

The known sequence detector according to the second invention is provided with diversity combining means for selecting a correlation value of a branch having the highest received signal level among a plurality of branches.

The known sequence detector according to the third invention is provided with diversity combining means for weighting the correlation value according to the signal level received for each branch and combining the weighted results.

The known sequence detector according to the fourth invention is provided with diversity combining means for weighting and combining correlation values obtained at fixed time intervals within a preset time range.

The known-sequence detector according to the fifth invention, when the correlation value obtained after the correlation operation between the received signal for each branch and the known sequence is smaller than a preset threshold value, It is provided with a correlation calculating means that does not output.

The known sequence detector according to the sixth invention comprises a threshold value calculating means for using a value proportional to the received signal power for each branch as a threshold value.

The known sequence detector according to a seventh aspect of the present invention includes a determination means for making a determination by adding a fixed amount of offset to the threshold value obtained by the threshold value calculation means.

The known sequence detector according to an eighth aspect of the present invention is configured such that, when the threshold value obtained by the threshold value calculating means is smaller than a predetermined specified value, the specified value is set as the threshold value. It is provided with a judging means for judging by giving.

The known sequence detector according to the ninth aspect of the present invention is configured such that if the threshold value obtained by the threshold value calculating means becomes smaller than a predetermined value, a known sequence is detected. It is provided with determination means for invalidating.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. In this embodiment, BPSK (two-phase PSK) and QPSK (4
In a receiving apparatus using a phase modulated signal represented by phase PSK, etc., a known sequence used for frame synchronization control and the like included in a transmitted signal is detected.

FIG. 1 shows a configuration example of a known sequence detector in a system using a four-phase PSK modulation signal according to the present embodiment. In FIG. 1, reference numerals 10A and 10B denote antenna units of a receiving apparatus for realizing two-branch diversity.
Reference numerals A and 20B denote quasi-synchronous detectors for converting an RF signal received by an antenna into a baseband signal.
B is an A / D converter for converting an in-phase component of a received signal output from the quasi-synchronous detectors 20A and 20B into a digital signal;
31A and 31B convert A to quadrature components of the received signals output from the quasi-synchronous detectors 20A and 20B into digital signals.
/ D converter. 60A is a signal level detector for detecting the signal level received at the branch 1, 60B is a signal level detector for detecting the signal level received at the branch 2, and 100A is for detecting a known sequence from the digital signal. This is a known series detection unit that performs

Further, the known sequence detecting section 100A is configured as follows. Reference numerals 40A and 40B denote correlation calculators for calculating the correlation between the in-phase and quadrature components of the received signal as a digital signal and the in-phase and quadrature components in the known sequence.
Is a diversity combining unit that performs diversity combining using correlation values for two branches. 140A is a detection unit that detects a known sequence when the combined correlation value output from the diversity combining unit 50 is equal to or greater than a threshold. When a pulse is output and the combined correlation value is smaller than the threshold value, the determination unit that does not output the detection pulse, 150 calculates the reception power for two branches to calculate the threshold value, It is a threshold value calculation unit that calculates a threshold value proportional to the power value.

FIG. 2 shows the correlation calculation units 40A and 40A of FIG.
FIG. 2 is a block diagram showing the internal configuration of the OB. 101A is a correlator for correlating the in-phase component of the received signal converted into a digital signal with the in-phase component of the known sequence, and 102A is a correlator for correlating the in-phase component of the received signal as a digital signal with the quadrature component of the known sequence. 103A is a correlator for correlating the quadrature component of the received signal that has become a digital signal with the quadrature component of the known sequence, and 104A is for correlating the quadrature component of the received signal that has become a digital signal with the in-phase component of the known sequence. The correlator 110A to be calculated is the output of the correlator 101A and the correlator 1
An adder for adding the output of the correlator 03A is a subtractor for subtracting the output of the correlator 102A from the output of the correlator 104A. 120A is a squaring circuit that multiplies the output of the adder 110A, 121A is a squaring circuit that multiplies the output of the subtractor 111A, and 130A is two squaring circuits 120A, 1A.
This is an adder for adding the output of 21A. The internal configuration of the correlation calculator 40B is the same as that of the above-described correlation calculator 40A, and a description thereof will be omitted.

FIG. 3 is a block diagram showing the internal configuration of diversity combining section 50 of FIG. 51 is a correlation calculator 4
A multiplier 52 multiplies the correlation value of the branch 1 output from 0A by the signal level of the branch 1 output from the signal level detector 60A, and 52 is the multiplier and the correlation value of the branch 2 output from the correlation calculator 40B. A multiplier 53 performs multiplication with the signal level of the branch 2 output from the level detector 60A, and an adder 53 adds the outputs of the multipliers 51 and 52.

FIG. 4 is a block diagram showing an internal configuration of the threshold value calculation section 150 of FIG. 151A is a squaring circuit for squaring the in-phase component of the digital signal of the branch 1, and 152A is a squaring circuit for squaring the quadrature component of the digital signal of the branch 1.
51B is a squaring circuit for squaring the in-phase component of the received signal of the branch 2 as a digital signal, and 152B is a quadrature circuit of the orthogonal signal of the received signal of the branch 2 as a digital signal of
It is a squaring circuit. 160A is the square circuit 1
The adder 160B adds the output of the squaring circuit 151B and the output of the squaring circuit 152A.
The adder for adding the output of 52B, 170A is an adder 1
A multiplier 170B multiplies the output of the signal level detector 60A by the output of the signal level detector 60A. A multiplier 170B multiplies the output of the adder 160B by the output of the signal level detector 60B.
An adder 80 adds the output of the multiplier 170A and the output of the multiplier 170B. 190 is a moving average circuit for calculating a moving average of the output of the adder 180, and 171 is a multiplier for multiplying the output of the moving average circuit 190 by a preset proportional constant.

FIG. 5 is a block diagram showing the internal configuration of the determination section 140A of FIG. 141 is a correlation value after combining output from the diversity combining unit 50 and the threshold value calculating unit 1
A comparison is made with the threshold value output from 50, and a known sequence detection pulse is output based on the comparison result.

Next, the operation of this embodiment will be described with reference to FIGS. Here, a case of four-level PSK will be described as an example of a digital modulation signal. The RF signals received by the two antennas are quasi-synchronously detected by the quasi-synchronous detectors 20A and 20B, respectively, and are converted into baseband signals of in-phase and quadrature components. The baseband signals R1 (t) and R2 (t) of the in-phase and quadrature components of the quasi-coherently detected two-branch reception signals are represented by complex numbers as follows. R ₁ (t) = A ₁ (t) · exp {j (Δωt + θ (t) + Δθ ₁ )} = A ₁ (t) · {a (t) + j b (t)} · exp {j (Δωt + Δθ ₁ ) } R ₂ (t) = A ₂ (t) · exp {j (Δωt + θ (t) + Δθ ₂ )} = A ₂ (t) · {a (t) + j b (t)} · exp {j (Δωt + Δθ ₂ )} (Ten)

Here, A ₁ (t) and A ₂ (t) are the signal amplitudes of branch 1 and branch 2, Δω is the oscillation frequency difference between the center frequency of the received signal and the local oscillator for quasi-synchronous detection, and Δθ is the reception frequency. Phase difference between signal and local oscillator output, θ (t) is modulation component, a
(t) and b (t) are baseband signals of in-phase and quadrature components, respectively. For simplicity, Δω = 0 and the A / D converter 30
Assuming that A, 30B, 31A, and 31B are sampled at the Nyquist point at the symbol rate, the output of the A / D converter is expressed by the following equation. R ₁ (nT) = A ₁ (nT) · {a (nT) + j b (nT)} · exp {j (Δθ ₁ )} R ₂ (nT) = A ₂ (nT) · {a (nT) + j b (nT)} · exp {j (Δθ ₂ )} (1
1)

The obtained two-branch signal R ₁ (nT),
R ₂ (nT) is input to the correlation calculators 40A and 40B, respectively. The real part (in-phase component) of R ₁ (nT) input to the correlation calculator 40A is the correlator 101A and the correlator 1 shown in FIG.
02A. On the other hand, the imaginary part (orthogonal component) of R ₁ (nT)
Is input to the correlator 103A and the correlator 104A.
Here, the correlator 101A inside the known sequence detector 100,
The known sequence K (i) referred to in 102A, 103A, and 104A is shown in the following equation. _{K (i) = K r (} i) -j K q (i) (12) However, i = 1~N, N is the known sequence length (symbol). In equation (12), K _r (i) indicates a sequence of in-phase components of a known sequence, and K _q (i) indicates a sequence of orthogonal components of a known sequence. Next, at time nT, the correlator 101 of the branch 1
The data stored in the i-th shift register in A, 102A, 103A and 104A are shown below. R _1n (i) = A _1n (i) · {an (i) + j bn (i)} · exp {j (Δθ ₁ )} (13) In the case of branch 2 as well, the data is stored in the i-th shift register. The data is expressed by the following equation as in the case of the branch 1. R _2n (i) = A _2n (i) · {an (i) + j bn (i)} · exp {j (Δθ ₂ )} (14)

In the correlation calculation unit 40A of the branch 1, (12)
The complex correlation operation of Expression (13) and Expression (13) is performed. The following equation shows the processing.

[0041]

(Equation 3)

Here, Cr _1n and Cq _1n indicate the real part and the imaginary part of the complex correlation output C _1n of the branch 1, respectively.
X _1n and Y _1n are represented by the following equations.

[0043]

(Equation 4)

As in the case of the branch 1, the correlation calculator 40B of the branch 2 performs the complex correlation operation of the equations (12) and (14). The following equation shows the processing.

[0045]

(Equation 5)

Here, Cr _2n and Cq _2n indicate the real part and the imaginary part of the complex correlation output C2n of the branch 2, respectively.
X _2n and Y _2n are represented by the following equations.

[0047]

(Equation 6)

[0048] Here, the real part of the C _1n (Cr _1n) and the imaginary part (C
q _1n ) corresponds to the output of the adder 110A and the output of the subtractor 111A. The real part of the C _1n (C _R1n) and the imaginary part (C
q _1n ) are squared in squaring circuits 120A and 121A, respectively. The obtained two square outputs are added to an adder 130.
A is added. The correlation value Z _1n of the branch 1 which is the output of the adder 130A is given by the following equation. Z _1n = (Cr _1n ) ² + (Cq _1n ) ² = {X _1n cos (Δθ ₁ ) −Y _1n sin (Δθ ₁ )} ² + {X _1n sin (Δθ ₁ ) + Y _1n cos (Δθ ₁ )} ² (1
9)

Similarly to the method of calculating the correlation value of branch 1, the correlation value Z _2n of branch 2 is given by the following equation. Z _2n = (Cr _2n ) ² + (Cq _2n ) ² = {X _2n cos (Δθ ₂ ) −Y _2n sin (Δθ ₂ )} ² + {X _2n sin (Δθ ₂ ) + Y _2n cos (Δθ ₂ )} ² (20)

The correlation values Z _1n and Z _2n output from the correlation calculators 40 A and 40 B of the two branches are input to the diversity combining section 50. In the diversity combining unit 50 shown in FIG. 3, the multiplication circuit 51 multiplies the correlation value of branch 1 by the signal level of branch 1. The multiplication circuit 52 multiplies the correlation value of the branch 2 by the signal level of the branch 2. In the adder 53, the output of the multiplication circuit 51 and the output of the multiplication circuit 52 are added. Output A _D1n signal level detector 60A of this time, the output of the signal level detector 60B is assumed to be A _D2n, the correlation value D _vn of a is after combining the output of the diversity combining unit 50 is given by the following formula . D _vn = A _D1n・ Z _1n + A _D2n・ Z _2n (21)

Next, referring to FIG.
Will be described. In order to obtain the power of the received signal of the branch 1, the in-phase and quadrature components of the received signal of the branch 1 that have become digital signals are input to the squaring circuits 151A and 152A, respectively, and are squared. The obtained output of the squaring circuit 151A and the output of the squaring circuit 152A are input to the adder 160A, and the received signal power of the branch 1 is calculated. At time nT, the received signal power of branch 1 is expressed by the following equation. P _1n = | R ₁ (nT) | ² = | A ₁ (nT) · {a (nT) + j b (nT)} · exp {j (Δθ ₁ )} | ² = (A ₁ (nT)) ²・ {(A (nT)) ² + (b (nT)) ² } = 2 ・ (A ₁ (nT)) ² (22) where a (nT) = ± 1 and b (nT) = ± 1 A ₁ (nT) indicates the amplitude in branch 1 that has undergone level fluctuation such as fading.

Similarly, in order to obtain the received signal power for the branch 2, the in-phase and quadrature components of the received signal of the branch 2 which have become digital signals are respectively squared by the squaring circuit 15.
The signals are input to the 1B and squaring circuits 152B and squared.
The obtained output of squaring circuit 151B and squaring circuit 152
The output of B is input to adder 160B, and the received signal power of branch 2 is calculated. At time nT, the received signal power of branch 2 is as follows: P _2n = | R ₂ (nT) | ² = | A ₂ (nT) · {a (nT) + j b (nT)} · exp {j (Δθ ₂ ) } | ² = (A ₂ (nT)) ² · {(a (nT)) ² + (b (nT)) ² } = 2 · (A ₂ (nT)) ² (23) where a ( nT) = ± 1, b (nT) = ± 1, and A ₂
(nT) is branch 2 that has undergone level fluctuation such as fading.
Shows the amplitude at.

Here, the output P _1n of the adder 160A and the output P _2n of the adder 160B at the time nT are output from the signal level detector 60 by the multipliers 170A and 170B, respectively.
The outputs of A and 60B are weighted by the signal levels A _D1n , A _D2n . The output _Pcn of the adder 180, which is the power after the combination, can be expressed by the following equation. P _cn = A _D1n・ P _1n + A _D2n・ P _2n (24)

The obtained output of the adder 180 is input to the moving average circuit 190 and smoothed. Next, at time nT, _assuming that the data P _cn (i) is stored in the i-th shift register of the moving average circuit 190, the moving average output P _mcn
Is given by the following equation.

[0055]

(Equation 7)

However, the number of stages of the moving average is M stages. The output P _mcn of the moving average circuit 190 is input to the multiplier 171 and is multiplied by a preset proportional constant K _th . Therefore, D _th is the output of the threshold value calculation unit 150 is given by the following equation. D _th = K _th · P _mcn (26)

Next, the operation of the determination section 140A will be described with reference to FIG. Threshold D _th is the output of the diversity combining correlation values obtained after synthesis in section D _vn and a threshold calculation unit 150 is input to the determination unit 140A whether it found the known sequence. The determination unit 140A, the magnitude of the output D _th correlation value D _vn and a threshold calculation unit 150 after the synthesis are compared by the comparator 141. Here, the determination unit 14
0A outputs a detection pulse _DT as a determination result according to the following equation. Judgment unit 140A output D _T = 1 (D _vn ≧ D _th ) = 0 (D _vn <D _th ) (27) Based on the output D _T of the judgment unit 140A obtained by the above processing, the known sequence in the frame is Knowing the position, frame synchronization control is performed.

In the present embodiment, the moving average circuit 190 of the threshold value calculation section of FIG.
In the example shown in FIG. 6, the received power after the synthesis and the output of the multiplier 193, that is, the received power obtained up to one sampling cycle before, are smoothed as shown in FIG. An IIR including an adder 191 for adding the value weighted by the forgetting coefficient α, a delay 192 for delaying the smoothed received power by one symbol, and a multiplier 193 for multiplying the output of the delay 191 by the forgetting coefficient α. The structure which performs smoothing by a type filter may be sufficient.

As described above, the present embodiment is provided with diversity combining means for weighting the correlation value according to the signal level received for each branch and combining the weighted results. Since it is hard to be affected by the signal level fluctuation and the non-detection rate of the known sequence can be suppressed, the known sequence can be detected satisfactorily.

Further, since threshold value calculating means for outputting a value proportional to the received signal power for each branch as a threshold value is provided, it is hardly affected by received signal level fluctuation due to fading, and the known sequence non-detection rate is reduced. Can be suppressed, so that a known sequence can be detected satisfactorily.

Embodiment 2 FIG. 7 shows a configuration of a known sequence detector in a system using a four-phase PSK modulation signal according to the present embodiment. In the first embodiment, diversity combining section 50 and threshold value calculating section 150 perform weighting combining based on the signal levels of signal level detectors 60A and 60B, and calculate the correlation value and threshold value after combining. However, in the present embodiment, a threshold value that is proportional to the correlation value of the branch having the highest received signal level and the received signal power of the branch among the two branches is used. Therefore, the present embodiment has the same configuration as that of FIG. 1 of the first embodiment except for the diversity combining unit 50A and the threshold value calculating unit 150A, and the description of the same components will be omitted.

FIG. 8 is a block diagram showing the internal configuration of diversity combining section 50A according to the present embodiment. 54
Is the branch 1 output from the signal level detector 60A.
For comparing the signal level of the branch 2 with the signal level of the branch 2 output from the signal level detector 60B;
55 is a correlation calculation unit 40A based on the output of the comparator 54.
Value of the branch 1 output from the controller and the correlation calculator 40B
Is a selection circuit that selects and outputs one of the correlation values of the branch 2 output from the.

FIG. 9 is a block diagram showing an internal configuration of threshold value calculating section 150A according to the present embodiment.
151C is a squaring circuit for squaring the in-phase component of the digital signal of the branch 1; 152C is a squaring circuit for squaring the quadrature component of the digital signal of the branch 1; 151D is , A squaring circuit for squaring the in-phase component of the digital signal of the branch 2, and a squaring circuit 152 D for squaring the quadrature component of the digital signal of the branch 2. Also,
160C is the output of the squaring circuit 151C and the squaring circuit 152.
An adder for adding the output of C, 160D is a squarer circuit 15
The adder 172 adds the output of 1D and the output of the squaring circuit 152D. The adder 172 calculates the signal level of the branch 1 output from the signal level detector 60A and the signal level of the branch 2 output from the signal level detector 60B. The comparator 181 that compares the magnitudes is one of the received power value of the branch 1 output from the adder 160C and the received power value of the branch 2 output from the adder 160D based on the output of the comparator 172. Is a selection circuit that selects and outputs the selected data. 1
Reference numeral 90 denotes a moving average circuit that calculates a moving average of the output of the selection circuit 181. Reference numeral 171 denotes a multiplier that multiplies the output of the moving average circuit 190 by a preset proportional constant.

Next, diversity combining section 1 will be described with reference to FIG.
The operation of 50A will be described. In the diversity combining unit 50 shown in FIG. 8, the comparator 54 compares the signal level of the branch 1 with the signal level of the branch 2 in the comparator 54. At time nT, assuming that the output of the signal level detector 60A is AD1n and the output of the signal level detector 60B is AD2n, the level comparison result output of the comparator 54 is represented by the following equation. Output C _cn = 0 of comparator 54 (A _D1n ≧ A _D2n ) = 1 (A _D1n <A _D2n ) (28)

Further, the selection circuit 55 selects the correlation value of the branch 1 output from the correlation calculation section 40A and the correlation value of the branch 2 output from the correlation calculation section 40B based on the level comparison result of the comparator 54. Do. Assuming that the output of the correlation value 40A is Z _1n and the output of the correlation value 40B is Z _2n at time nT, the output of the selection circuit 55 is represented by the following equation. Output of selection circuit 55 S _cn = Z _1n (C _cn = 0) = Z _2n (C _cn = 1) (29)

Next, referring to FIG.
The operation of A will be described. Threshold calculator 1 shown in FIG.
At 50A, the comparator 172 compares the signal level of the branch 1 with the signal level of the branch 2. At time nT, the output of signal level detector 60A is
_Assuming that A _D1n and the output of the signal level detector 60B are A _D2n , the level comparison result output of the comparator 172 is represented by the following equation. Output C _Ln = 0 of comparator 172 (A _D1n ≧ A _D2n ) = 1 (A _D1n <A _D2n ) (30)

Next, in order to obtain the power of the received signal of the branch 1, the in-phase and quadrature components of the received signal of the branch 1, which have become digital signals, are input to the squaring circuit 151C and the squaring circuit 152C, respectively, and are squared. You. The obtained output of the squaring circuit 151C and the output of the squaring circuit 152C are input to the adder 160C, and the received signal power P _1n of the branch 1 at the time nT is calculated. Further, in order to obtain the power of the received signal of the branch 2, the in-phase and quadrature components of the received signal of the branch 1 which have become digital signals are input to the squaring circuits 151D and 152D, respectively, and are squared. The obtained output of the squaring circuit 151D and the output of the squaring circuit 152D are input to the adder 160D, and the received signal power P _2n of the branch 2 at the time nT is calculated.

Further, in the selection circuit 181, the comparator 17
Based on the level comparison result of 2, the received signal power P _1n of the branch 1 output from the adder 160C and the received signal power P _2n of the branch 2 output from the adder 160D are selected. At time nT, the output of the selection circuit 181 is represented by the following equation. Output of selection circuit 181 S _Ln = Z _1n (C _Ln = 0) = Z _2n (C _Ln = 1) (31)

The obtained output of the selection circuit 181 is input to the moving average circuit 190, and is smoothed as in the first embodiment. Then, the smoothed reception power is calculated by the multiplier 17.
1 is input. Then, a predetermined proportional constant K _th
Is multiplied to calculate _Dth, which is the output of the threshold value calculation unit.

In the present embodiment, the moving average circuit 190 of the threshold value calculation section of FIG.
In the example shown in FIG. 6, the received power after the synthesis and the output of the multiplier 193, that is, the received power obtained up to one sampling cycle before, are smoothed as shown in FIG. An IIR including an adder 191 for adding the value weighted by the forgetting coefficient α, a delay 192 for delaying the smoothed received power by one symbol, and a multiplier 193 for multiplying the output of the delay 191 by the forgetting coefficient α. The structure which performs smoothing by a type filter may be sufficient.

As described above, in the present embodiment, the diversity combining section 50A and the threshold value calculating section 150A do not need to perform weighting combining unlike the first embodiment, so that simplification can be achieved. Furthermore, since a known sequence is detected by selecting a branch having a large received signal level, the influence of the received signal level fluctuation due to fading is hardly affected, and the non-detection rate of the known sequence can be suppressed. Detection can be performed well.

Embodiment 3 FIG. 10 shows a configuration of a known sequence detector of a system using a four-phase PSK modulation signal according to the present embodiment. In the first embodiment, the diversity combining unit 50 performs weighted combining based on the signal levels of the signal level detectors 60A and 60B, and calculates the correlation value after the combining. Are combined within a predetermined time range. In the present embodiment,
Except for diversity combining section 50B, the configuration is the same as that of the first embodiment, and the description of the same configuration will be omitted.

FIG. 11 is a diagram showing the diversity synthesizing unit 5 shown in FIG.
FIG. 2 is a block diagram showing the internal configuration of the OB. Embodiment 1
Similarly, the multiplier 51 multiplies the correlation value of the branch 1 output from the correlation calculator 40A by the signal level of the branch 1 output from the signal level detector 60A, and the multiplier 52 is output from the correlation calculator 40B. This is a multiplier that multiplies the correlation value of the branch 2 and the signal level of the branch 2 output from the signal level detector 60A. Reference numeral 56 denotes a shift register, and 57 denotes an adder for calculating the sum of the values of the shift register 56.

Next, the operation of diversity combining section 50B will be described with reference to FIG. In the diversity combining section 50B shown in FIG. 11, the multiplication circuit 51 multiplies the correlation value Z _1n of the branch 1 by the signal level A _D1n of the branch 1. The multiplication circuit 52 multiplies the correlation value Z _2n of the branch 2 by the signal level A _D2n of the branch 2. In the adder 53, the output of the output the multiplication circuit 52 of the multiplier circuit 51 is added, the correlation value Dv _n after branch combining is calculated. The resulting correlation value Dv _n is input to the shift register 56 of the MR stage for each sampling time interval T.
In the adder 57, the values of the shift register are synthesized,
The correlation value after the combination is calculated. Here, at time nT, _assuming that the data Sv _n (i) is stored in the i-th shift register of the shift register 56, the combined correlation value S _Mn output from the adder 57 is given by the following equation. .

[0075]

(Equation 8)

As described above, in the present embodiment, after the correlation values obtained in the two branches are weighted and synthesized at the signal level, the diversity synthesis is further performed within a preset time range. The non-detection rate of a known sequence can be suppressed in a transmission path having a large delay spread under frequency selective fading, and the known sequence can be detected satisfactorily.

Embodiment 4 FIG. 12 shows a configuration of a known sequence detector in a system using a four-phase PSK modulation signal according to the present embodiment. In the second embodiment, diversity combining section 50A includes signal level detectors 60A and 60A.
The correlation values of the two branches are selected based on the signal level of B, and the selected correlation values are output. In the present embodiment, the correlation values after combination obtained for each branch for each sampling time are calculated. Synthesize within a preset time range,
The selection of the correlation value of the two branches is performed based on the signal levels of the signal level detectors 60A and 60B. The present embodiment has the same configuration as that of FIG. 7 of the second embodiment except for diversity combining section 50C, and a description of the same components will be omitted.

FIG. 13 shows the diversity synthesizing unit 5 of FIG.
It is a figure showing the internal configuration of OC. A comparator 54A compares the signal level of the branch 1 output from the signal level detector 60A with the signal level of the branch 2 output from the signal level detector 60B, and 56A and 56B.
Is a shift register, 57A and 57B are shift registers 5
This is an adder that calculates the sum of the values of 6A and 56B. 55
A is a selection circuit that selects and outputs one of the correlation value of the branch 1 output from the adder 57A and the correlation value of the branch 2 output from the adder 57B based on the output of the comparator 54A. .

Next, the operation of diversity combining section 50C will be described with reference to FIG. In the diversity combining unit 50C shown in FIG. 13, the comparator 54A compares the signal levels of the branch 1 and the branch 2 with each other. At time nT, the signal level detector 60A
Is A _D1n and the output of the signal level detector 60B is A _D2n
, The level comparison result output of the comparator 54A is expressed by the following equation. Output C _cn = 0 of comparator 54A (A _D1n ≧ A _D2n ) = 1 (A _D1n <A _D2n ) (33)

The correlation value of the branch 1, which is the output of the correlation calculation circuit 40A, is input to the shift register 56A of the MR stage at every sampling time interval T. In the adder 57A, the values of the shift register are combined, and the combined correlation value is calculated. Here, assuming that at time nT, the data Sv _1n (i) stored in the i-th shift register of the shift register 56A, the combined correlation value S _M1n output from the adder 57A is given by the following equation. .

[0081]

(Equation 9)

The correlation value of the branch 2, which is the output of the correlation calculation circuit 40B, is obtained at each sampling time interval T by MR.
It is input to the shift register 56B of the stage. Adder 57B
In, the values in the shift register are combined, and the combined correlation value is calculated. Here, at time nT, assuming that the data Sv _2n (i) is stored in the i-th shift register of the shift register 56B, the combined correlation value S _M2n output from the adder 57B is given by the following equation. .

[0083]

(Equation 10)

Further, in the selection circuit 55A, the comparator 54
Based on the level comparison result of A, the correlation value of the branch 1 output from the adder 57A and the correlation value of the branch 2 output from the adder 57B are selected. The output of the selection circuit 55A at time nT is represented by the following equation. Output of selection circuit 55A S _cn = S _M1n (C _cn = 0) = S _M2n (C _cn = 1) (36)

As described above, the diversity combining circuit according to the present embodiment combines within the preset time range,
Furthermore, since diversity combining for selecting a correlation value of two branches according to the received signal level is performed, it is possible to suppress the non-detection rate of a known sequence particularly in a transmission path with a large delay spread under frequency selective fading. Can,
A known sequence can be detected satisfactorily.

Embodiment 5 FIG. 14 shows a configuration of a known sequence detector in a system using a four-phase PSK modulation signal according to the present embodiment. In the fourth embodiment, the correlation calculators 40A and 40B calculate the correlation values using the equations (15) to (20) and output the correlation values as they are. However, the correlation calculators 41A and 41B according to the present embodiment. In the above, a threshold value is set in advance, and if the correlation value calculated for each sampling is smaller than the threshold value, no correlation value is output. The other configuration is the same as that of FIG. 12 of the fourth embodiment, and the description is omitted.

Next, the operation will be described with reference to FIG. FIG. 15 is an example in which the correlation value calculated based on the equations (15) to (20) is calculated under a frequency selective fading transmission path. FIG. 15 shows a correlation value in the case where there is no noise in the transmission path, in order to consider only the influence of the delayed wave. Under the condition of frequency selective fading, a radio wave enters the antenna via various paths, and thus involves a plurality of delayed waves. Therefore, the correlation value calculated based on the equations (15) to (20) has a spread due to the delayed wave over the time of several sampling periods. In an actual environment, noise is also added. In a state where the noise is added, a small correlation value due to the delayed wave is buried in the noise. Here, diversity combining section 50C of the present embodiment has the same configuration as that of the fourth embodiment, and in diversity combining section 50C, a correlation value obtained at a constant time interval for each branch is used as the number MR of shift register stages. The composition is performed within a corresponding preset time range.
Now, in the diversity calculating section 50C, the threshold value Zth is set in advance in the correlation calculating section 41A of the branch 1 as shown in FIG. 15 so that the correlation value buried in the noise is not synthesized in the diversity combining section 50C. Control the output. Output of correlation calculating section 41A = Z _1n (Z _1n > Z _th ) = 0 (Z _1n ≦ Z _th ) (37)

The same output control as that of the correlation calculation unit 41A of the branch 1 is also performed for the correlation calculation unit 41B of the branch 2.

As described above, according to the present embodiment, if the correlation value obtained after the correlation operation between the received signal and the known sequence for each branch is smaller than a preset threshold value,
Since a correlation calculation unit that does not output a correlation value is provided, it is possible to suppress erroneous detection of a known sequence caused by adding a correlation value or noise power buried in noise in a diversity combining unit at a subsequent stage. , A known sequence can be detected satisfactorily.

Embodiment 6 FIG. FIG. 16 shows a configuration example of a known sequence detector in a system using a four-phase PSK modulation signal according to the present embodiment. In the first embodiment, a value proportional to the received signal power is used as the threshold value of determination section 140A. However, in determination section 140B of the present embodiment, the output value of threshold value calculation section 150 is A value to which a certain offset is added is used as a threshold value for detecting a known sequence. The other configuration is the same as that of FIG. 1 of the first embodiment, and the description is omitted.

FIG. 17 is a block diagram showing the internal configuration of the determination section 140B of FIG. 141 is a comparator that outputs a detection pulse indicating that a known sequence has been detected when the combined correlation value is equal to or greater than a threshold, and 142 compares the output value of the threshold calculator with a fixed offset value. It is an adder for adding.

Next, the operation of the determination unit of this embodiment will be described with reference to FIG.
This will be described with reference to FIG. Output Dth of threshold calculating section 150
Is a determination unit 140 for determining whether a known sequence has been detected.
B is input. The adder 142 adds the output D _th of the threshold value calculation unit 150 and a preset constant offset value α _th . Then, the output value of the adder 142 becomes the correlation value Dv _n and the final threshold after synthesis comparator 14
Compared by 1. Here, the determination unit 140B outputs a detection pulse _DT as a determination result according to the following equation. Output of decision section 140B D _T = 1 (Dv _n ≧ (D _th + α _th )) = 0 (Dv _n <(D _th + α _th )) (38)

As described above, in the present embodiment, since a constant offset value is added to the output value of the threshold value calculation unit, the level of the received signal decreases due to the occurrence of fading. Received signal has no significant information, and the output value of the threshold value calculation unit becomes almost 0,
The erroneous detection rate of the known series can be suppressed, and the known series can be detected satisfactorily.

Embodiment 7 FIG. FIG. 18 shows a configuration example of a known sequence detector in a system using a four-phase PSK modulation signal according to the present embodiment. In the first embodiment, a value proportional to the received signal power is used as the threshold value of determination section 140A. However, in determination section 140C of the present embodiment, the output value of threshold value calculation section 150 is When the predetermined value is smaller than a predetermined value, the specified value is used as a threshold for detecting a known sequence. Others
The configuration is the same as that of FIG. 1 of the first embodiment, and the description is omitted.

FIG. 19 is a block diagram showing the internal configuration of the determination section 140C of FIG. 141, when the correlation value after synthesis is not less than the threshold value, the comparator outputs a detection pulse indicating the detection of a known sequence, 143, the output of the threshold calculation section than the prescribed value alpha _th This is a non-linear circuit that outputs the specified value α _th as a threshold for detecting a known sequence when the value becomes smaller.

Next, the operation of the determination unit of this embodiment will be described with reference to FIG.
This will be described with reference to FIG. Output D of threshold calculator 150
_th is a determination unit 14 for determining whether a known sequence has been detected
0C is input. Nonlinear circuit 143 outputs the specified value as a threshold for detecting a known sequence when output D _th of threshold value calculating section 150 is smaller than specified value α _th . The output value of the nonlinear circuit 143 is shown in the following equation. (Output of the nonlinear circuit 143) = α _th (D _th <α _th ) = D _th (D _th ≧ α _th ) (39)

[0097] Then, the output value of the nonlinear circuit 143 is a correlation value Dv _n and the final threshold after synthesis, which is the output value of the diversity combining unit 50 are compared by the comparator 141. The decision unit 140C, if the correlation value Dv _n after synthesis is an output value or magnitude of the nonlinear circuit 143 outputs a known sequence detection pulse, known sequence detection pulse in other cases does not output.

As described above, in the present embodiment, when the output value of the threshold value calculation unit is smaller than a predetermined value, this specified value is used as a threshold value for detecting a known sequence. Even if the received signal level decreases due to fading, the received signal after A / D conversion has no significant information and the output value of the threshold value calculation unit becomes almost 0, the known sequence is erroneously detected. Rate can be reduced,
A known sequence can be detected satisfactorily.

Embodiment 8 FIG. FIG. 20 shows a configuration example of a known sequence detector in a system using a four-phase PSK modulation signal according to the present embodiment. In the first embodiment, a value proportional to the received signal power is used as the threshold value of determination section 140A, but determination section 140D of the present embodiment
If the output value of the threshold value calculation unit 150 is smaller than a preset specified value, even if a known sequence is detected, it is invalid and no known sequence detection pulse is output. The other configuration is the same as that of FIG. 1 of the first embodiment, and the description is omitted.

FIG. 21 is a block diagram showing the internal configuration of the determination section 140D of FIG. 141A is a comparator that outputs a detection pulse indicating that a known sequence has been detected when the combined correlation value is equal to or greater than a threshold value, and 144 is a comparator that outputs the threshold value calculation unit output and the specified value α _th . The comparator 145 for comparing the magnitudes is an AND circuit that calculates the logical product of the output of the comparator 141A and the output of the comparator 144.

Next, the operation of the determination unit of this embodiment will be described with reference to FIG.
This will be described with reference to FIG. Output D of threshold calculator 150
_th is a determination unit 14 for determining whether a known sequence has been detected
0D is input. The comparator 141A compares the magnitude of the correlation value Dv _n after the output value of the output D _th and diversity combining section 50 of the threshold value calculation unit 150 synthesis, and outputs the comparison result given by: . (Output of the comparator _{141A) = L (Dv n <} D th) = H (Dv n ≧ D th) (40) In addition, the comparator 144, the output D of the threshold value calculation unit 150
The magnitude of _th and the specified value α _th are compared, and a comparison result given by the following equation is output. (Output of comparator 144) = L (D _th <α _th ) = H (D _th ≧ α _th ) (41)

Further, the obtained output of the comparator 141A and the output of the comparator 144 are input to an AND circuit 145,
When the output of the comparator 144 is “H”, the AND circuit 14
5 can output a pulse "H" indicating that a known sequence has been detected. On the other hand, the output of the comparator 144 is “L”.
, The output of the AND circuit 145 is output to the comparator 141A.
Can output only "L" regardless of whether the output is "L" or "H", it becomes impossible to output the pulse "H" indicating that a known sequence is detected.

As described above, in the present embodiment, when the output value of the threshold value calculation unit is smaller than a predetermined value, even if a known sequence is detected, the known sequence detection pulse is output as invalid. Therefore, even if the received signal level after A / D conversion has no significant information and the output value of the threshold value calculation unit becomes almost 0, the received signal level decreases due to the occurrence of fading. In addition, the erroneous detection rate of the known series can be suppressed, and the known series can be detected satisfactorily.

[0104]

According to the first aspect of the present invention, there is provided a correlation calculating means for calculating a correlation between a plurality of received signals obtained by a plurality of antennas and a known sequence, and a correlation between a plurality of branches obtained by the correlation calculating means. Diversity combining means for performing diversity combining using values, threshold calculating means for calculating a threshold for detecting a known sequence, and a correlation value after diversity combining obtained by the diversity combining means, Since there is provided a determination unit that determines whether the threshold value is larger than the threshold value obtained by the threshold value calculation unit,
Even in a transmission path where fading occurs, the non-detection rate of the known sequence can be suppressed, and the known sequence can be detected satisfactorily.

According to the second aspect of the present invention, since the diversity combining means for selecting the correlation value of the branch having the highest received signal level among the plurality of branches is provided, it is hardly affected by the received signal level fluctuation due to fading. ,
Since the non-detection rate of the known sequence can be suppressed, the known sequence can be detected satisfactorily.

In the third invention, the correlation value is weighted according to the signal level received for each branch,
Since diversity combining means for combining these weighting results is provided, it is less susceptible to received signal level fluctuation due to fading, and a known sequence non-detection rate can be suppressed, so that known sequence detection can be performed well. it can.

According to the fourth aspect of the present invention, since the diversity combining means for weighting and combining the correlation values obtained at fixed time intervals within a predetermined time range is provided, especially the delay spread under frequency selective fading is provided. The non-detection rate of the known sequence can be suppressed in a large transmission path, and the known sequence can be detected satisfactorily.

In the fifth invention, when the correlation value obtained after the correlation operation between the received signal and the known sequence for each branch is smaller than a preset threshold value, the correlation calculating means that does not output the correlation value Is provided, the erroneous detection rate of the known sequence can be suppressed, and the known sequence can be detected satisfactorily.

According to the sixth aspect of the present invention, since the threshold value calculating means for outputting a value proportional to the received signal power for each branch as a threshold value is provided, it is hardly affected by received signal level fluctuation due to fading. Since the sequence non-detection rate can be suppressed, the known sequence can be detected satisfactorily.

According to the seventh aspect of the present invention, the determination means for performing the determination by adding a fixed amount of offset to the threshold value obtained by the threshold value calculation means is provided. Thus, the known sequence can be detected satisfactorily.

In the eighth invention, when the threshold value obtained by the threshold value calculating means is smaller than a predetermined specified value, a determination is made by giving a specified value as the threshold value. Since the means is provided, the erroneous detection rate of the known series can be suppressed, and the known series can be detected satisfactorily.

In the ninth aspect, when the threshold value obtained by the threshold value calculation means is smaller than a predetermined value, the determination means invalidates the known sequence even if it is detected. Is provided, the erroneous detection rate of the known sequence can be suppressed, and the known sequence can be detected satisfactorily.

[0113]

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a known sequence detector according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating a configuration of a correlation calculating unit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of a diversity combining unit according to Embodiment 1 of the present invention.

FIG. 4 is a diagram illustrating a configuration of a threshold value calculation unit according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a determination unit according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating another configuration example related to a smoothing method of a moving average circuit or the like of the threshold value calculation unit according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a known sequence detector according to a second embodiment of the present invention.

FIG. 8 is a diagram illustrating a configuration of a diversity combining unit according to Embodiment 2 of the present invention.

FIG. 9 is a diagram showing a configuration of a threshold value calculation unit according to Embodiment 2 of the present invention.

FIG. 10 is a diagram showing a configuration of a known sequence detector according to Embodiment 3 of the present invention.

FIG. 11 is a diagram illustrating a configuration of a diversity combining unit according to Embodiment 3 of the present invention.

FIG. 12 is a diagram showing a configuration of a known sequence detector according to Embodiment 4 of the present invention.

FIG. 13 is a diagram illustrating a configuration of a diversity combining unit according to Embodiment 4 of the present invention.

FIG. 14 is a diagram showing a configuration of a known sequence detector according to a fifth embodiment of the present invention.

FIG. 15 is a diagram illustrating an example of an output of a correlation calculator when it is assumed that there is no noise under frequency selective fading.

FIG. 16 is a diagram showing a configuration of a known sequence detector according to Embodiment 6 of the present invention.

FIG. 17 is a diagram illustrating a configuration of a determination unit according to Embodiment 6 of the present invention.

FIG. 18 is a diagram showing a configuration of a known sequence detector according to Embodiment 7 of the present invention.

FIG. 19 is a diagram illustrating a configuration of a determination unit according to Embodiment 7 of the present invention.

FIG. 20 is a diagram showing a configuration of a known sequence detector according to Embodiment 8 of the present invention.

FIG. 21 is a diagram illustrating a configuration of a determination unit according to Embodiment 8 of the present invention.

FIG. 22 is a diagram showing a configuration of a known sequence detector of the related art.

FIG. 23 is a diagram illustrating a configuration of a quasi-synchronous detection unit in a conventional known sequence detector.

FIG. 24 is a diagram illustrating a configuration of a known sequence detection unit in a known sequence detector of the related art.

[Explanation of symbols]

10, 10A, 10B Antenna 20, 20A, 20B Quasi-synchronous detector 21 Local oscillator 22 90-degree phase shifter 23, 24 Multiplier 30, 30A, 30B, 31, 31A, 31B A / D
Converters 40A, 40B, 41A, 41B Correlation calculators 50, 50A, 50B, 50C Diversity synthesizers 51, 52 Multipliers 53 Adders 54, 54A Comparators 55, 55A Selection circuits 56, 56A, 56B Shift registers 57, 57A , 57B Adder 60A, 60B Signal level detector 100 Known sequence calculator 101, 101A, 102, 102A, 103, 103
A, 104, 104A Correlator 110, 110A Adder 111, 111A Subtractor 120, 121, 120A, 121A Multiplier 130, 130A Adder 140 Judge 140A, 140B, 140C, 140D Judge 141, 141A Comparator 142 Addition 143 Non-linear circuit 144 Comparator 145 AND circuit 150, 150A Threshold calculator 151A, 151B, 151C, 151D Square circuit 152A, 152B, 152C, 152D Square circuit 160A, 160B, 160C, 160D Adder 170A, 170B Multiplier 171 Multiplier 172 Comparator 180 Adder 181 Selection circuit 190 Moving average circuit 191 Adder 192 Delayer 193 Multiplier

Claims (9)

[Claims] 1. A correlation calculating means for calculating a correlation between a plurality of received signals obtained by a plurality of antennas and a known sequence; and diversity combining using correlation values of a plurality of branches obtained by the correlation calculating means. Diversity combining means for performing, a threshold value calculating means for calculating a threshold value for detecting a known sequence, and a correlation value after diversity combining obtained by the diversity combining means is obtained by the threshold value calculating means. A known sequence detector, comprising: determination means for determining whether the value is larger than a threshold value. 2. The known sequence detector according to claim 1, wherein said diversity combining means selects a correlation value of a branch having the highest received signal level among a plurality of branches. 3. The known sequence detector according to claim 1, wherein said diversity combining means weights the correlation values according to the signal level received for each branch and combines the weighted results. . 4. The known sequence detector according to claim 1, wherein said diversity combining means weights and combines correlation values obtained at predetermined time intervals within a preset time range. 5. The method according to claim 1, wherein the correlation calculating means does not output a correlation value when a correlation value obtained after a correlation operation between the received signal and the known sequence for each branch is smaller than a preset threshold value. The known sequence detector according to claim 1, wherein: 6. The known sequence detector according to claim 1, wherein said threshold value calculating means calculates a value proportional to the received signal power for each branch as a threshold value. 7. The known-sequence detector according to claim 1, wherein said determination means performs the determination by adding a fixed amount of offset to the threshold value obtained by said threshold value calculation means. 8. When the threshold value obtained by the threshold value calculating means is smaller than a predetermined specified value, the determining means gives a specified value as the threshold value to make the determination. 2. The known sequence detector according to claim 1, wherein: 9. When the threshold value obtained by the threshold value calculating means becomes smaller than a predetermined value, the determining means invalidates a known sequence even if it is detected. The known sequence detector according to claim 1, wherein: