JPH10229173A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method for a semiconductor device, which enables a fine platinum electrode such as a stacked capacitive electric or the like, using platinum to be manufactory with high productivity and moreover easily, in a superfine electric device. SOLUTION: A mold 2 consisting of a recess is made by selectively etching an insulating film 2 as a capacitive insulating film, and this mold 4 is filled up with platinum 5. Next, the platinum 5 is etched back, leaving it only in the mold 4, and after that, the insulating film 2 is etched back to a required thickness, leaving platinum 5 in the mold, whereby a platinum capacitive electrode 6 is selectively made. It is easy to form a fine and highly accurate mold 4 by anisotropically etching back the insulating film 2, and it becomes possible to easily form a fine and highly accurate platinum electrode, so as to form the platinum electrode 6 in a self-aligned manner, making use of this mold 4, and integration and fine processability of an electronic device can be greatly improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a platinum electrode, and more particularly, to a method for manufacturing a semiconductor device realizing the manufacture of a fine platinum electrode.

[0002]

2. Description of the Related Art With the recent miniaturization of semiconductor devices and further miniaturization of semiconductor devices, it is necessary to miniaturize electrodes formed on semiconductor devices. For example, at present, a dynamic random access memory (DRA) is used as a semiconductor memory device.
M), etc., are widely applied to DR.
As the degree of integration of AM has dramatically increased, the element area has become smaller, and the area in which a capacitance portion can be formed has become very narrow. For this reason, various measures for increasing the capacitance of the capacitor have been proposed. As a countermeasure, a method of increasing the capacitance surface area and a method of using a material having a high relative dielectric constant of an insulating film used for the capacitor are used. is there.

As a method of increasing the capacitance surface area, a method of using silicon as an electrode material and forming irregularities due to grain growth on the surface is disclosed in the Journal of Applied Physics in 1992.
Applied Physics, Volume 71, 3540
This is shown in FIG. 3 of the page. According to this document, to achieve this, low pressure chemical vapor deposition (LPCVD) is used.
Method), a silicon film is deposited at a temperature at which a transition is made from amorphous to polycrystalline, and a hemispherical grain (Hemisphere) is formed.
ica1-Grained-Si (HSG-Si) is formed on the electrode surface. However, a method of increasing the surface area using a silicon material is technically difficult for a gigabit DRAM or a DRAM having an electrode width of 0.25 μm or less. The reason is that a silicon oxide film or a silicon nitride film is used for the capacitor insulating film, and their relative dielectric constant is 4 to 5, and a capacitance exceeding 1 μm is required in order to obtain an estimated accumulated charge of 25 fF or more. An electrode height is required. This causes a difficulty in a process technology for manufacturing a DRAM.

Accordingly, in recent years, an example in which a material having a relative dielectric constant of 100 or more is used for a capacitive insulating film is disclosed in the International Electron Device Meeting (Int.
erial Electron Device
e Meeting (IEDM) Proceedings, page 831. In this method, strontium titanate (STO) is used as a ferroelectric material.
When forming a capacitor using a ferroelectric material, conventional silicon cannot be used for a capacitor electrode. Therefore, noble metals such as platinum have been studied as electrode materials.
As a technique for finely processing platinum, an ion beam sputtering method using an inert gas such as argon using a resist mask or a metal mask formed on platinum is used. For example, according to JP-A-5-89662, platinum is processed by ion beam sputtering using titanium as an etching mask.

[0005]

In the above-described platinum processing technique, titanium is used as an etching mask because the etching rate ratio of platinum to titanium (platinum rate / titanium rate) is four times, and This is because it is difficult for platinum to re-adhere at the time of platinum etching into a projection shape. However, since the titanium mask is eroded at the time of platinum etching, the erosion speed of the mask edge is usually twice or more as compared with the center of the mask. There is a problem that it is difficult to form a desired pattern. In addition, ion beam etching causes the platinum to have a forward taper, so that it is difficult to form a highly anisotropic pattern with a fine pattern.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of easily producing a fine platinum electrode such as a stack-type capacitance electrode using platinum in an ultra-fine electronic device with high productivity. It is to provide a method of manufacturing the device.

[0007]

According to the present invention, there is provided a method for forming an insulating film on a semiconductor substrate, forming a desired resist pattern on the insulating film, and using the resist pattern as a mask. Anisotropically etching the insulating film to form a mold having concave portions shallower than the thickness of the insulating film; And a step of etching back the platinum and leaving it only in the mold,
Removing the insulating film to the depth of the mold by etching back to leave platinum in the mold as an electrode.

Further, according to the manufacturing method of the present invention, a step of forming a capacitance insulating film on a semiconductor substrate, and a metal film containing at least one of titanium, titanium nitride, tungsten and titanium tungsten on the capacitance insulating film Forming an insulating film on the metal film, forming a desired resist pattern on the insulating film, and anisotropically dry-etching the insulating film using the resist pattern as a mask. Forming a mold having an opening until reaching the metal film, and embedding platinum to a thickness for embedding the mold on the insulating film, and etching back the platinum to form only the mold. Leaving step, etching back the insulating film, and anisotropically dry etching the exposed metal film using the remaining platinum as a mask. Characterized in that it comprises a step of forming a stacked electrode of platinum.

Here, the platinum electrode formed by the manufacturing method of the present invention may be not only a stack capacitor electrode but also an electrode connected to a capacitor. In addition, the capacitor insulating film, the insulating film for forming the template, and the metal film may have a stacked structure as well as a single layer.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are cross-sectional views showing a first embodiment of the present invention in the order of manufacturing steps. Here, an example of forming a platinum capacitor electrode using a silicon oxide film on a silicon substrate as a dielectric film according to the present invention will be described. Is shown. First, FIG.
As shown in (a), a silicon oxide film 2 formed by thermal oxidation is formed on a silicon substrate 1 to a thickness of 500 nm, a resist 3 is applied on the silicon oxide film 2, and the silicon oxide film 2 is formed by photolithography. A pattern having a diameter of .35 μm is formed. Next, as shown in FIG.
The silicon oxide film 2 is etched to a required depth using the resist 3 as a mask by using (reactive ion etching). Here, the etching conditions used were C ₄ F ₈
6 sccm, CO 60 sccm, Ar 180 sc
cm and the pressure was maintained at 40 mTorr.
The RF power was 650 W. The etching rate at that time is 300 nm / min. The etching depth was 100 nm. Then, as shown in FIG. 1C, the unnecessary resist 3 is completely removed by the oxygen plasma ashing method, whereby a vertically etched mold 4 having a depth of 100 nm is formed in the silicon oxide film 2. You.

Next, as shown in FIG. 2A, a platinum metal target is sputtered using an argon gas by a sputtering method using a DC magnetron discharge. Sputter deposition was performed until platinum 5 was buried in the mold 4 having a depth of 100 nm formed in the silicon oxide film 2.
The pressure during sputtering was several mTorr, and the film formation temperature was 1 mTorr.
00 ° C. Next, as shown in FIG. 2B, the platinum film was etched back using a dry etching apparatus using plasma discharge (ECR) by electron cyclotron resonance. The gas used at the time of the etch back is a mixed gas of chlorine and SF ₆ . Adjust the addition rate of chlorine gas to 30%,
The total gas flow rate was 240 sccm. The pressure at that time is 1
5 mTorr, microwave power was 300 W, high frequency power of 2 MHz applied to the substrate electrode supporting the silicon substrate 1 was 250 W, and substrate electrode temperature was 60 ° C. The etch-back speed of platinum 5 obtained at that time is 50 nm / m
became in. When platinum 5 is completely etched back,
As shown in the figure, the platinum 5 is left only in the mold 4. Subsequently, as shown in FIG.
Etch back. The etching conditions used were S
F ₆ gas flow rate 200sccm, pressure 20mTorr
r, microwave power is 300W, high frequency power is 10
0 W. At that time, the etch rate of the silicon oxide film 2 was 300 nm / min. As a result, the silicon oxide film 2 was completely etched away in about 20 seconds, but the erosion of the platinum 5 was negligible. As a result, a stack capacitor electrode 6 having a height of 100 nm was formed.

As described above, a fine mold 4 is formed by anisotropically etching the silicon oxide film 2, platinum 5 is buried in the mold, and then the silicon oxide film 2 constituting the mold 4 is removed. By doing so, it is possible to form a fine and highly anisotropic platinum electrode. In particular, in this manufacturing method, the platinum electrode is formed by a self-alignment method and is not etched by a mask using titanium or the like, so that it can be formed in an extremely fine pattern. Accordingly, it is possible to form a stack capacitor electrode using platinum, and it is possible to dramatically improve the degree of integration and fine workability of an electronic device.

FIG. 3 is a cross-sectional view of the main steps of the second embodiment of the present invention, and shows an example of forming a platinum stack capacitor electrode as in the first embodiment. However, here, a two-layer film made of a silicon oxide film and a silicon nitride film is used as the material of the capacitor insulating film. That is, as shown in FIG. 3A, a silicon oxide film 2 was formed to a thickness of 500 nm on the silicon substrate 1 by ripening.
Further, a silicon nitride film 7 having a thickness of 25 nm was formed on the silicon oxide film 2 by a plasma CVD method. Continued
A silicon oxide film 8 having a thickness of 100 nm was formed on the silicon nitride 7 by a plasma CVD method. Then, a resist 3 is applied on the silicon oxide film 8 and a pattern having a diameter of 0.35 μm is formed by photolithography. Next, FIG.
As shown in (b), the silicon oxide film 8 and the silicon nitride 7 are etched under the anisotropic etching conditions for forming the mold 4 used in the first embodiment to form the mold 4. Then, platinum 5 is buried in the mold 4,
Steps up to the etch back of FIG.
2 (b) to FIG. 2 (f). Then, by removing the silicon oxide film 8 by wet etching with a diluted hydrofluoric acid solution (HF: H ₂ O = 1: 30), as shown in FIG. 3C, the stack capacitor electrode 6 having a height of 100 nm is formed. It is formed. That is, since platinum is insoluble only in aqua regia, it is easy to selectively remove only the silicon oxide film using a hydrofluoric acid solution.

In this embodiment, similarly to the first embodiment, it is possible to form a fine and high-precision stacked capacitor electrode using platinum, thereby greatly improving the degree of integration and fine processing of an electronic device. Can be improved.

FIG. 4 is a cross-sectional view showing main steps of a third embodiment of the present invention. Here, an example of manufacturing a capacitor electrode having a two-layer structure of titanium and platinum is shown. First, FIG.
As shown in (a), a silicon oxide film 2 was formed on a silicon substrate 1 by a mature oxidation to a thickness of 500 nm. Next, titanium 9 was formed to a thickness of 25 nm on the silicon oxide film 2 by using a film forming method similar to the sputtering method of the first embodiment. Subsequently, a 100 nm thick silicon oxide film 8 was formed on the titanium 9 by a plasma CVD method. Then, a resist 3 is applied on the silicon oxide film 8 and a pattern having a diameter of 0.35 μm is formed by photolithography.
Next, the silicon oxide film 8 is etched under the same anisotropic etching conditions as those for forming the mold 4 of the second embodiment,
Further, the platinum 5 is embedded in the formed mold 4, and the platinum 5
The steps up to the etching back of the silicon oxide film 8 and the etching back of the silicon oxide film 8 were performed in the same manner as in the above-described embodiments.
As shown in (b), a platinum electrode 5 is formed, and titanium 9 is exposed as a base thereof. Thereafter, as shown in FIG. 4C, under the conditions of 100 sccm of chlorine gas, 10 mTorr of pressure, 200 W of microwave power, 50 W of high frequency power, and 60 ° C. of substrate temperature, the titanium 9 is used with the platinum capacitance electrode 6 as a mask.
Was performed. At this time, the platinum capacitance electrode 6
Erosion is slight. As a result, a stack capacitor electrode 10 having a height of 125 nm and having a multilayer structure of titanium 9 and platinum 5 was formed.

In this embodiment, similarly to the above embodiments, it is possible to form a fine and high-precision stacked capacitor electrode using platinum, and to greatly improve the integration degree and the fine workability of an electronic device. It is possible to do. Further, in this embodiment, when the silicon oxide film 8 is etched, the titanium 9 functions as a stopper, so that the depth control of the mold 4 is facilitated, and the height accuracy of the platinum electrode is improved like a flying goose. Become.

In the third embodiment, tungsten, titanium nitride, titanium tungsten, or a multilayer film of these metals can be used instead of titanium. Needless to say, these metals can be easily etched by reactive ion etching with halogen gas.

FIGS. 5 and 6 are sectional views showing a fourth embodiment in which the present invention is applied to a platinum electrode of a semiconductor device having a diffusion capacitance configuration in the order of steps. That is, as shown in FIG. 5A, a silicon oxide film 12 for element isolation is formed on a silicon substrate 11, and a gate oxide film 13, a word line 14 as a gate electrode, and a source / drain diffusion layer are formed. . Here, the source / drain diffusion layers are configured as a capacitance diffusion layer 15 and a bit line diffusion layer 16. A bit line 17 is formed on the bit line diffusion layer 16. Further, an interlayer insulating film 18 such as a CVD silicon oxide film is deposited on the entire surface, and a contact hole is opened on the capacitance diffusion layer 15, and a metal is buried in the contact hole to form a capacitance contact plug 19. . Then, a silicon oxide film 20 is formed on the interlayer insulating film 18.

Next, as shown in FIG. 5B, an opening is formed by selectively etching the silicon oxide film 20 using a resist (not shown) on the contact plug 19, and an opening is formed as a mold 21. Then, FIG.
As shown in (c), the mold 21 is embedded with platinum 22.
Thereafter, as shown in FIG. 6A, the platinum 22 is selectively etched back by leaving the platinum 22 only in the mold 21 and then removing the silicon oxide film 20 by etching. You. The platinum electrode 23 is formed in a self-aligned manner by the mold 21 formed on the silicon oxide film 20, and the mold 21 is formed finely and with high precision by anisotropic etching. As in the above embodiments, it is possible to realize an ultrafine semiconductor device.

Each of the above embodiments is merely an example of the present invention, and an insulating film for forming a mold or a metal laminated with platinum to form an electrode is made of a material other than those described above. It is also possible to use. In particular, a polyimide film can be used as the insulating film.

[0021]

As described above, according to the present invention, a mold is formed from an insulating film, the mold is buried with platinum, the platinum is etched back, only the inside of the mold is left, and then the insulating film is etched back. Because a platinum electrode is formed, it is possible to form a fine and highly accurate mold by anisotropically etching back the insulating film. Can be formed. As a result, a fine and high-precision platinum electrode can be easily formed, and the degree of integration and fine workability of an electronic device can be greatly improved. In addition, the semiconductor device can be easily manufactured under high productivity. Can be produced.

[Brief description of the drawings]

FIG. 1 is a first cross-sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a second sectional view showing the first embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view illustrating main steps of a second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a third embodiment of the present invention in the order of steps.

FIG. 5 is a first cross-sectional view showing a fourth embodiment of the present invention in the order of steps.

FIG. 6 is a second sectional view showing the fourth embodiment of the present invention in the order of steps;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Silicon oxide film 3 Resist 4 Template 5 Platinum 6 Platinum capacity electrode 7 Silicon nitride film 8 Silicon oxide film 9 Titanium 10 Titanium / Platinum capacity electrode

Claims (4)

[Claims] A step of forming an insulating film on the semiconductor substrate, a step of forming a desired resist pattern on the insulating film, and anisotropically etching the insulating film using the resist pattern as a mask. A step of forming a mold having a concave portion shallower than the thickness of the film, a step of embedding the mold with platinum while emphasizing platinum on a thickness of embedding the mold on the insulating film, and etching back the platinum. A method of forming the electrode as an electrode while etching back the insulating film to the depth of the mold to leave platinum in the mold. . 2. The method according to claim 1, wherein the insulating film is a capacitance insulating film, and the formed platinum electrode is a stack capacitance electrode. A step of forming a capacitor insulating film on the semiconductor substrate; a step of forming a metal film containing at least one of titanium, titanium nitride, tungsten, and titanium tungsten on the capacitor insulating film; A step of forming an insulating film on the metal film, a step of forming a desired resist pattern on the insulating film, and anisotropically dry-etching the insulating film using the resist pattern as a mask to reach the metal film A step of forming a mold having openings up to, a step of embedding platinum to a thickness for embedding the mold on the insulating film, a step of etching back the platinum and leaving only in the mold, and the insulating film Etch-back removal, the exposed metal film is anisotropically dry-etched using the remaining platinum as a mask to form an electrode on which the metal film and platinum are laminated. Forming a semiconductor device. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film forming the mold includes at least one material selected from a silicon oxide film, a silicon nitride film, and a polyimide film.