JPH10229103A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the heat dissipation property of a semiconductor device and to enable a stable ground of the device from backside of a semiconductor element, by a method wherein the backside of the element is connected with a board through conductive members. SOLUTION: Heat, which is generated with the operation of a semiconductor element 15, is transferred to a ground electrode 21 via solder bumps 27 and is further transferred to a ground plate 23 from through holes 25. Moreover, as paths, which dissipates the heat from the backside of the element 15 to the electrode 21 on a board 13 through Au wires 31 which are conductive members, are formed, the heat dissipation property of a semiconductor device 11 can be raised and these Au wires 31 serve as electrical paths for connecting a ground potential point (ground) on the backside of the element 15 with a ground potential point on the board 13. Thereby, as the ground (a metal layer 29 for heat dissipation and grounding use) on the backside of the element 15 can be made to connect with a ground (the ground electrode 21) on the surface of the board 13 through the conductive members (such as the Au wires 13), a package and the element 15 can be mounted on the device 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor device in which a semiconductor element is flip-chip connected on a substrate and a method of manufacturing the semiconductor device.

[0002]

2. Description of the Related Art Semiconductor devices (hereinafter referred to as chips).
The method of connecting the active element surface of
This is called chip connection. Usually, solder bumps are formed on a chip, the chip is turned upside down, aligned with the position of the substrate, and then the solder is melted and connected at a time to manufacture. Here, Document 1
According to (Reference 1: VLSI packaging technology (below), author Naruse Kayama, pp. 175-176, pp. 200-209, pp. 228-229), it occurs with the increase in power consumption of chips. Since it is important how heat is dissipated, the number of solder bumps must be reduced for a flip-chip connected semiconductor device as described above to ensure a sufficient heat dissipation path to the substrate side. Increase or provide thermal vias in the substrate. Also, thermal bumps are formed on the chip to radiate heat from the back of the chip, and PHS (plat
A heat sink called an ed heat sink was provided to reduce the thermal resistance of the device.

[0003]

However, in the above-described flip-chip connection semiconductor device,
The lowering of the thermal resistance is not sufficient, and therefore, Reference 2 (Reference 2: JP-A-7-106477) and Reference 3 (Reference 3:
1994 IEICE Spring Conference, Sekiguchi et al., B-5
46) As shown in 46), a solder or a heat conductive plate TAB is provided on a heat sink portion formed inside the package.
Attempts are made to lower the thermal resistance and ground the back surface of the chip by connecting the back surface of the chip using the method described above. However, these methods are very difficult to implement because the positional relationship between the package and the chip is limited, and the package must be mounted in consideration of the width between the package and the chip.

Further, a structure has been sought to stably connect the ground potential point on the back surface of the semiconductor element to the ground potential point on the substrate.

For this reason, there has been a demand for a semiconductor device which is excellent in heat dissipation and which can stably ground from the back surface of the semiconductor element.

[0006]

Therefore, according to the present invention, in a semiconductor device having at least a substrate and a semiconductor element flip-chip connected on the substrate, a back surface of the semiconductor element and a substrate are provided. Are connected by a conductive member.

The semiconductor element of the semiconductor device described here is a chip-shaped semiconductor element in which all the semiconductor components are contained on a semiconductor substrate such as a GaAs substrate.
The substrate refers to a substrate on which the semiconductor element is mounted.
The semiconductor element and the substrate are flip-chip connected, and the surface of the semiconductor element and the substrate surface are bonded by bumps. A grounding electrode is further provided on the surface of the substrate, and this electrode is electrically connected to the heat dissipation and grounding plate on the back side through a metal-plated through hole. Also, PHS (Plated Heat)
A heat sink called Sink) is formed.

In the above-described semiconductor device, heat generated from the semiconductor element is transmitted to the substrate from bumps, which are connecting portions between the surface of the semiconductor element and the substrate, and the ground plate provided on the substrate serves as a heat sink. Therefore, the thermal resistance of the entire device is reduced. When the back surface of the semiconductor element of this device and the substrate are newly connected using a conductive member, the heat generated by the operation of the semiconductor element is generally From the heat sink on the back of the semiconductor element,
It is transmitted to the substrate via this conductive material. Therefore, since the number of heat conduction paths of the device can be increased, the heat dissipation can be further improved.

Conventionally, the grounding of the back surface of the semiconductor element has been performed by conducting to a solder layer or the like formed inside the package, so that the positional relationship between the package and the semiconductor element is limited, and mounting is performed. Was difficult. However, according to the present invention, since the back surface of the semiconductor element and the substrate are connected by the conductive member, the ground potential point on the back surface of the semiconductor element and the ground potential point of the substrate can be conducted. . For this reason, connection for grounding between the package and the semiconductor element is not required, and mounting work is facilitated.

In the present invention, preferably, the length of the conductive member from the contact point between the back surface of the semiconductor element and the conductive member to the point where the conductive member reaches the substrate is determined by the operation of the semiconductor element. It is preferable that the length be half the wavelength at the frequency.

In a semiconductor device operated in a high-frequency region, the ground potential point on the back surface of the semiconductor element has an inductance component corresponding to the length of the conductive member added to the ground potential point on the back surface of the semiconductor element. It is stable. Normal,
The inductance of such wiring is 0.7-1.0 nH
/ Mm. When an inductance component is added, there is a possibility that the frequency characteristics may be degraded or parasitic oscillation may occur. Therefore, as described above, the length of the conductive member from the contact point between the back surface of the semiconductor and the conductive member to the point where the conductive member reaches the substrate is set to be 倍 times the wavelength at the operating frequency of the semiconductor element. If the length of the conductive member is adjusted, the same state as when the length of the conductive member is 0, that is, a short-circuited state can be created.
(Reference 4: Yoshiyuki Naito, 1986 (first edition), Corona,
IEICE, Microwave / Millimeter Wave Engineering, p. 1 to
p. See 12). ). Therefore, the effect of the inductance component is substantially eliminated, and stable grounding can be performed.

Preferably, the conductive member is a metal wire.

When the substrate and the back surface of the semiconductor element are connected by wire bonding or ribbon bonding, a heat conduction path for releasing heat generated in the semiconductor element from the back surface side of the semiconductor element to the substrate can be created, thereby improving the heat dissipation of the device. Can be improved. Further, when the length of the wire or ribbon is set to be a half of the wavelength at the operating frequency of the semiconductor element and connected, the inductance component generated by the metal wire is substantially present on the ground on the back surface of the semiconductor element. Since a state in which the semiconductor element is not added can be created, the ground on the back surface of the semiconductor element and the ground on the substrate can be stably connected.

In the present invention, preferably, the conductive member is a conductive heat radiating plate formed in contact with the back surface of the semiconductor element, and the contact point is an edge on the back side of the semiconductor element. The points may be bumps provided on the substrate and around the semiconductor element.

The heat radiating plate is formed in contact with the back surface of the semiconductor element, and is provided with a protruding portion that protrudes from an edge on the back surface side of the semiconductor element. By connecting the overhang portion and the substrate with bumps, the back surface of the semiconductor element and the substrate are connected. Here, the length from the edge on the back side of the semiconductor element to the bump for connecting the overhang on the substrate, that is, the length of the overhang is の 長 times the wavelength at the operating frequency of the semiconductor element. With such adjustment, the grounding of the back surface of the semiconductor element can be stabilized as described above. Furthermore, since the conductive member is a conductive heat radiating plate, the area for conducting heat is larger than that of the metal wire, so that the heat radiating property can be further improved.

Preferably, the conductive member is constituted by a strip-shaped dielectric and a metal layer formed on the dielectric, and the conductive member is formed from a contact point between the back surface of the semiconductor element and the conductive member. The length D of the conductive member up to the point at which the member reaches the substrate is determined by setting the wavelength at the operating frequency of the semiconductor element to λ.
When the effective permittivity of the dielectric is ε _eff , D = λ
/ 2 表 ε _eff .

The conductive member composed of the strip-shaped dielectric and the metal layer formed thereon is a member having a certain degree of flexibility or flexibility. Connect so that the upper metal layer is conductive. Then, from the contact point between the back surface of the semiconductor element and the conductive member,
When the length D of the conductive member up to the point where the conductive member reaches the substrate is set to be a half of the wavelength λ at the operating frequency of the semiconductor element so that the ground on the back surface of the semiconductor element is stabilized. Considering that the wavelength of a wave passing through a metal layer (also referred to as a line) on a dielectric as in the present invention is reduced to 1 / √ε _eff of the wavelength of a wave passing through a normal wire or the like, The length D of the conductive member is D = λ / 2√ε
It can be the length represented by _eff .

The wavelength of a wave passing through a line on a dielectric
1 / √ε of the wavelength of the wave passing through the wire etc. _eff Why
And will be described briefly. Wavelength of wave passing through ordinary wire etc.
Is the wavelength of light λ, λ = 2π / β (β is a phase constant
You. ). Focusing on the phase of the wave,
Phase velocity (how the phase shifts over time
Or v)_p Is v_p = Ω / β (ω is angular velocity
Every time). Next, consider a plane wave, which is a wave passing through a line on a dielectric.
Then, the phase constant β is β = ω√ (εμ) (ε is the permittivity,
where μ is the magnetic permeability)_p Is v_p = Ω /
β = 1 / √ (εμ). At this time, the wavelength λ is λ = 2π
/ Β = 2π / ω√ (εμ). That is, of ordinary light
1/２ (εμ) times the wavelength of 2π / ω.
You. Assuming that the magnetic permeability (μ) is approximately 1, 1 / √ε is obtained.
You. Therefore, it consists of a dielectric and a metal layer on this dielectric.
From the point of contact of the conductive member formed on the backside of the semiconductor element
The operating frequency of the semiconductor device is determined by the distance to the substrate
When the length is set to 1/2 of the wavelength in
Assuming that the wavelength at the frequency is λ, λ / 2√ε_eff When
The length can be shortened.

Preferably, in a semiconductor device in which a conductive member for connecting the back surface of the semiconductor element and the substrate is composed of a dielectric and a metal layer formed on the surface,
A substrate connection bump and a back surface connection bump of the semiconductor element, each of which is provided in conduction with the metal layer, wherein a contact point of the conductive member with the back surface of the semiconductor element is used as a back surface connection bump of the semiconductor element; It is preferable that the point of reaching to be a substrate connection bump.

The bump for connecting the back surface and the bump for connecting the substrate of the semiconductor element are formed in advance on a conductive member. The positions at which these bumps are formed are the positions that are the above-mentioned contact points and arrival points. Therefore, the distance between the bump for connecting the back surface of the semiconductor element and the bump for connecting the substrate is 1 / 2√ε _eff times the wavelength at the operating frequency of the semiconductor element. The aligned bumps are bonded to the metal layer by applying pressure and ultrasonic vibration or by a method such as thermocompression bonding.

In the method of manufacturing a semiconductor device as described above, preferably, a step of forming a large number of semiconductor elements on a common board, and a step of applying a resist on the board so as to embed the semiconductor elements, A step of etching back the resist until reaching the upper surface of the semiconductor element, a step of forming a metal layer for heat dissipation and grounding on the semiconductor element and the resist, and a step of cutting the metal layer and the resist between the semiconductor elements And removing the board and the resist to leave the semiconductor element and the metal layer.

These steps are performed, for example, in the above-described semiconductor device in which the conductive member is a conductive heat radiating plate formed in contact with the back surface of the semiconductor element. This is a process used for manufacturing a structure in which a radiating plate having an overhanging portion is attached to the back surface of the semiconductor element. After connecting the semiconductor element to the substrate by flip-chip bonding, when connecting the back surface of the semiconductor element to the substrate with a conductive member, for example, a wire or the like, a plurality of bumps connecting the semiconductor element and the substrate. When the semiconductor element is not horizontal with respect to the substrate due to distortion or size deviation, it may be difficult to crimp the wire to the back surface of the semiconductor element. According to the above-described manufacturing method, it is possible to manufacture a structure in which a heat sink (a metal layer for heat dissipation and grounding), which is a conductive member, is securely and easily bonded in advance to a semiconductor element.

[0023]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention; Each drawing merely schematically shows the shape, size, and arrangement relationship of each component so that the present invention can be understood. In the following description, specific materials and conditions will be used, but these materials and conditions are merely examples of preferred embodiments, and therefore, the present invention is not limited thereto. Further, hatching (hatched lines) used in drawings other than the cross-sectional view does not indicate a cross-section, but is used to partially emphasize or distinguish it from other portions.

<First Embodiment> As a first embodiment, in a semiconductor device having a semiconductor element which is flip-chip connected on a substrate, the back surface of the semiconductor element and the substrate are connected by metal wires. An example of connection will be described with reference to FIGS. FIG. 1A is a schematic plan view of the semiconductor device according to the first embodiment viewed from above.
FIG. 1B is a diagram showing a cross section taken along line XX of FIG. 1A, and FIG. 1C is a cross section taken along line YY of FIG. 1A. FIG. FIG. 2 is a schematic enlarged view of a main part of the present invention.

First, reference is made to FIG. This semiconductor device 1
1 includes a substrate 13 and a semiconductor element 15. The substrate 13 is formed by depositing Ni on a ceramic substrate 17 having a thickness of 0.254 mm, plating Au on the Ni, and forming a signal line 19 on the Ni. And a grounding electrode 21 (FIG. 1A). Under the grounding electrode 21, the ceramic substrate 2 penetrates through the ceramic substrate 17.
1 is provided with a through-hole 25 reaching the ground plate 23 formed on the entire back surface (see FIGS. 1A and 1C). The inner wall of the through hole 25 is metal-plated, and electrically connects the ground electrode 21 and the ground plate 23. Here, the semiconductor element 15 is a HEMT element 15 using a GaAs substrate having a thickness of 0.2 mm.
The ground electrode 21 and the signal line 19 of the substrate 13 are connected to each other by different solder bumps 27 on the surface of the semiconductor element 15. In addition, the semiconductor element 1
5 has a metal layer 29 (PHS: Plate) for heat dissipation and grounding.
d Heat Sink) and a conductive member such as A
This metal layer 29 is formed by ribbon bonding using the u-line 31.
And the ground electrode 21 on the substrate 13 are connected.

Here, paying attention to the heat conduction path for heat radiation of the device 11, heat generated by the operation of the semiconductor element 15 is transmitted to the grounding electrode 21 via the solder bump 27 and further to the through hole 25. To the ground plate 23. Further, in the present invention, there is a new path for releasing heat from the back surface side of the semiconductor element 15 to the grounding electrode 21 on the substrate 13 through the Au wire 31 which is a conductive member here. Can be improved.

The Au line 31 is also an electrical path connecting the ground potential point (ground) on the back surface of the semiconductor element 15 to the ground potential point on the substrate 13. Conventionally, the ground on the back surface of the semiconductor element was connected to a heat sink portion provided inside the package of the semiconductor device, so that the positional relationship between the package and the semiconductor element was limited, and mounting work was difficult. According to the configuration of the present invention, the ground (metal layer 2 for heat dissipation and grounding) on the back surface of semiconductor element 15 is formed.
9) the substrate 1 with a conductive member (for example, Au wire 31).
3 can be connected to the ground (electrode 21 for grounding) on the surface, so that the above-described restrictions between the package and the semiconductor element can be avoided, and the package can be easily mounted.

Next, referring to FIG. 2, the length of the conductive member,
That is, determination of the length of the conductive member from the contact point between the back surface of the semiconductor element 15 and the conductive member to the point where the conductive member reaches the substrate will be described.

In this example, an Au wire (wire or ribbon) 31 is used as the conductive member. The length of the Au wire 31 from the contact point O to the arrival point Q (the arrival point Q is on the ground electrode 21) is determined by the length of the semiconductor element 15
動作 of the wavelength of the operating frequency.
Assuming that the length is D and the operating frequency is f, D = C / 2f (C is the speed of light). Further, as shown in FIG. 2, the Au line 31 is composed of an arc length having a radius of curvature r as a radius of curvature and a length y of a straight line portion. Therefore, the length D of the Au line 31 is D = ｛2πr × ( 90 + θ) / 360 ° + y (θ is the angle between the Au line and the substrate). Here, when a straight line is drawn on the substrate 13 from the edge 15a of the semiconductor element 15 vertically, a point Q where the Au line 31 reaches the substrate 13 from a point P where the straight line intersects the substrate 13
Assuming that the shortest linear distance on the substrate 13 (here, the grounding electrode 21) is A, the relationship between the distance A and the length y of the linear portion of the Au line 31 is represented by the following equation: ycos θ = A−rsin θ It is represented by Therefore, the distance A is represented by the following equation: A = {(C / 2f) −2πr × (90 + θ) / 360} cos θ + rsin θ Thereby, the Au line 31 is a distance A from the intersection P between the straight line and the substrate 13 when the straight line is drawn on the substrate 13 from the edge 15a of the semiconductor element 15 vertically.
If a point separated by a distance is formed as the arrival point Q to the substrate, A
The length of the u-line 31 can be set to １ ／ of the wavelength at the operating frequency of the semiconductor element 15.

As a result, as described above, the Au wire 3
The same state as when the length of 1 is 0, that is, a short-circuited state can be created.
P. 1 to p. See 12). ). Therefore, the influence of the inductance component due to the Au wire 31 substantially disappears on the ground on the back surface of the semiconductor element, and stable grounding to the ground electrode 21 of the substrate 13 can be performed.

<Second Embodiment> As a second embodiment, the semiconductor device has almost the same structure as the semiconductor device used in the first embodiment, and a conductive member is provided on the back surface of the semiconductor element. A conductive heat sink formed in contact with the
An example in which a contact point between a conductive member and a semiconductor element is an edge on the back side of the semiconductor element, and a point where the conductive member reaches the substrate is a bump provided on the substrate and around the semiconductor element is shown in FIG. This will be described with reference to 3 to 5.

FIGS. 3A to 3C and FIGS.
(C) is a schematic manufacturing process view of part of the semiconductor device of the second embodiment; Each drawing in FIGS. 3 and 4 is shown by a cross section of the structure obtained in the main process step. FIG. 5A is a schematic plan view of the semiconductor device according to the second embodiment as viewed from above, and FIG. 5B is a cross-sectional view taken along line XX of FIG. 5A. It is a figure which shows the cut surface of the cross section which shows schematically.

First, reference is made to FIG. 3 and FIG. A heat radiating plate formed in contact with the back surface of the semiconductor element and having an overhang portion protruding from the edge on the back surface side of the semiconductor element is provided on the back surface of the semiconductor element in advance. Therefore, first, in the step of forming a large number of semiconductor elements 15 on the common board 41, the quartz board 41 is used here as the common board 41, and the quartz board 41 and the many semiconductor elements 15 are formed. Wafer 45 is attached to the front side of the wafer. Thereafter, a resist pattern is formed on the back surface of the wafer so that a region other than the semiconductor element 15 is opened, and the opening region is removed by etching. Thereafter, the resist is removed to leave many semiconductor elements 15 on the quartz disk 41 (FIG. 3).
(A)).

Next, as shown in FIG.
A resist 47 is applied on the board 41 (FIG. 3B).

Next, the resist 47 is etched back until it reaches the upper surface of the semiconductor element 15. Here, the upper surface refers to the back surface of the semiconductor element 15. In this example, the resist 47 is preferably etched back by dry etching using oxygen (FIG. 3).
(C)).

Next, a metal layer 49 for heat dissipation and grounding is formed on the semiconductor element 15 and the resist 47. here,
Preferably, for example, Ti / Au is converted to EB (Electron Beam).
After the layers are stacked by using a method such as vapor deposition, gold plating is preferably performed. The thickness of the gold film was 20 μm. The metal layer 49a for heat dissipation and grounding is used later as a heat dissipation plate 49b (FIG. 4A).

Next, the metal layer 49a and the resist 47 between the semiconductor elements 15 are cut. In this example, preferably
Cutting using a laser cutter (also called dicing)
(FIG. 4B).

Next, the board 41 and the resist 47 are removed,
The semiconductor element 15 and the metal layer 49a are left. In this example, the razor blade is preferably connected to the semiconductor element 15 and the quartz disk 4.
It is preferable that the quartz disc 41 be inserted between the plates 1 and 1 to be peeled off. Then, the semiconductor element 15 on which the metal layer 49a is formed is cleaned with an organic solvent and an ultrasonic wave,
7 as well as other waste (see FIG. 4).
(C)).

Through the above steps, a heat sink 49 having an overhang 49x is formed on the back surface of the semiconductor element 15.
The semiconductor element 15 to which b is bonded can be formed (FIG. 4C).

Thereafter, solder bumps 27 are formed on the surface side of the semiconductor element 15, while the heat dissipation plate 49 b is provided on the ground electrode 21 of the substrate 13 on which the semiconductor element 15 is mounted.
Is formed at a position where the overhang portion 49x is connected. Thereafter, the surface of the semiconductor element 15 and the substrate 13 are flip-chip connected using a flip-chip bonder. Then, on the hot plate, the overhanging portion 49x of the heat sink 49b and the grounding electrode 21 of the substrate 13 are connected via the overhanging portion connection bump 51 by using a bonding tool using ultrasonic waves (FIG. 5). (B)).

As a result, the structure of the semiconductor device 11 shown in FIGS. 5A and 5B is obtained. According to the above-described manufacturing method, the heat dissipation plate 49b (a metal layer for heat dissipation and grounding), which is a conductive member, can be securely and easily bonded to the semiconductor element 15.

Here, the edge 1 on the back side of the semiconductor element 15
When the length from 5a to the overhanging portion connection bump 51, that is, the length of the overhanging portion 49x is adjusted to の 長 the wavelength at the operating frequency of the semiconductor element 15,
As described above, the ground on the back surface of the semiconductor element 15 can be stabilized. Further, since the conductive member is a conductive heat radiating plate 49b, the heat transfer area is larger than that of the metal wire, so that the heat radiating property can be further improved.

<Third Embodiment> As a third embodiment, the structure of the semiconductor device according to the first and second embodiments is almost the same, but the conductive member is made of a dielectric and this dielectric. An example of a structure including the metal layer formed above will be described with reference to FIGS.

FIG. 6 is a plan view (FIG. 6A) schematically showing the structure of a dielectric such as polyimide which is a conductive member in this example and a metal layer formed thereon. A)
FIG. 6B is a view schematically showing a cut surface of a cross section cut along the line ZZ of FIG. FIG.
FIG. 7 schematically shows a plan view (FIG. 7A) of the structure of the semiconductor device of this example viewed from above and a cut surface cut along the line XX of FIG. 7A. It is a figure (FIG. 7 (B)) which shows the cut surface of a cross section.

Referring to FIG. 6A and FIG. 6B, in this example, the width of the conductive member on the surface of the TAB tape 61 having a thickness of (h) and made of polyimide which is a dielectric material. A metal layer 63 shown in FIG. 3 (w) is formed, and a microstrip-type band-shaped structure 67 having a ground conductor 65 formed on the entire back surface of the TAB tape 61 is used. In this example, a thin dielectric film 69 is formed on the surface of the belt-shaped structure 67.
Are formed (FIG. 6B). In addition, bumps are formed in advance at positions of contact points between the metal layer 63 of the band-shaped structure 67 and the back surface of the semiconductor element 15 and positions of points where the metal layer 63 reaches the ground electrode 21 of the substrate 13. (See FIGS. 6 and 7B). These bumps are used as a back surface connection bump 71a and a substrate connection bump 71b of the semiconductor element, respectively. The bump is bonded to the surface side of the band-shaped structure 67 by applying pressure and ultrasonic vibration or by a method such as thermocompression bonding (FIG. 6B). At this time, a hole is opened in the thin dielectric 69 at the bonding portion, and the dielectric 69 is electrically connected to the metal layer 63 of the band-shaped structure 67. Further, the distance D between the back surface connection bump 71a and the substrate connection bump 71b of this semiconductor element is determined.
Is λ / 2, where λ is the wavelength at the operating frequency of the semiconductor element 15 and ε _eff is the effective dielectric constant of the polyimide.
Let と す る ε _eff be the length.

As already described in the first and second embodiments, the length D between the contact point of the conductive member with the semiconductor element 15 and the arrival point on the substrate 13 is defined as the length of the back surface of the semiconductor element 15. The length is set to 倍 of the wavelength λ at the operating frequency of the semiconductor element 15 so that the ground is stabilized.

In this example, a microstrip-type band-shaped structure 67 is used as a conductive member. Considering that the wavelength of the wave passing through the metal layer 63 (also referred to as a line) on the dielectric is reduced to 1 / √ε _eff of the wavelength of the wave passing through a normal wire or the like, the point from the contact point to the arrival point The length D can be a length represented by D = λ / 2√ε _eff .

In this example, the dielectric constant ε of the polyimide
_r is 3.5. Reference 5 (Reference: Brian C. Wadell, Art
ech House, Inc., 1991, Transmission Line Design Handb
ook, p.93-94), the effective permittivity ε _eff is approximately: ε _eff = (ε _r +1) / 2 + {(ε _r -1) / 2} {1+ (12.0 × h / w )} ^-0.5 ... Here, h is the thickness of the dielectric (polyimide), and w is the width of the metal layer 63.

In this example, when h is set to 0.127 mm and w is set to 0.277 mm, ε _eff = 2.74 is obtained. Therefore, the length D from the contact point to the arrival point is calculated by using a normal wire. As compared with the length set to be half the wavelength at the operating frequency of the semiconductor element 15 by about 0.1 mm or more,
It could be reduced by 60 times.

When the length D is defined as the distance between the bump 71a for connecting the back surface of the semiconductor element and the bump 71b for connecting the substrate, the length of the metal layer 63 which is a conductive member is substantially reduced. In other words, the length of the semiconductor element 15 at the operating frequency is 倍 times the wavelength, so that the ground on the back surface of the semiconductor element 15 can be stabilized.

Further, polyimide may be formed as an upper layer and a lower layer in contact with the upper and lower surfaces of the metal layer, respectively. In this case, the bump for connecting the back surface and the bump for connecting the substrate of the semiconductor element are formed on the upper surface side. In addition, the effective permittivity ε _{eff, buried}
Is represented by the following equation (see Document 5, pages 113 to 114).

Ε _{eff, buried} = ε _eff [e ^{(−2.0b / h)} ] + ε _r [1.0−e ^{(−2.0b / h)} ] where b is the thickness of the upper layer and h is the lower layer Is the thickness. For example, when the thickness b of the upper layer is 0.051 mm, the thickness h of the lower layer is 0.127 mm, and other conditions are the same as those of the above-mentioned band-shaped structure, ε _{eff, buried} is 3.16, and from the contact point, The length up to the arrival point can be reduced to about 0.56 times as compared with a length set by a normal wire or the like so as to be half the wavelength at the operating frequency of the semiconductor element 15.

The belt-shaped structure 67 formed as described above
Are connected to the substrate 13 and the semiconductor element 15 flip-chip connected to the substrate 13 by bumps 71 for connecting the back surface of the semiconductor element.
a and the connection via the board connection bump 71b,
A semiconductor device 11 as shown in FIGS. 7A and 7B is obtained. The heat generated in the semiconductor element 15 can be transmitted from the back surface side of the semiconductor element 15 to the ground electrode of the substrate 13 through the metal layer 63. For this reason, heat dissipation can be improved.

Further, since the length of the belt-shaped structure 67 can be reduced, the size of the device to be mounted can be reduced.

[0055]

As described above, in a semiconductor device having at least a substrate and a semiconductor element flip-chip connected to the substrate, the back surface of the semiconductor element and the substrate are electrically connected by a conductive member. By the connection, a heat conduction path from the back surface of the semiconductor element to the substrate is formed, so that the heat dissipation of the device is improved.

Further, since the ground on the back surface of the semiconductor element can be conducted to the ground of the substrate, restrictions on the positional relationship between the semiconductor element and the package can be avoided, and mounting can be facilitated.

Further, the length of the conductive member from the contact point between the conductive member and the back surface of the semiconductor element and the point at which the conductive member reaches the substrate is set to の of the wavelength at the operating frequency of the semiconductor element. By connecting the conductive member to twice the length, a state in which the inductance component from the conductive member is not substantially added to the ground on the back surface of the semiconductor element operating at a high frequency, that is, the semiconductor back surface Since a state in which the ground potential point and the ground potential point of the substrate are short-circuited can be created, the ground on the back surface of the semiconductor element can be stably connected to the ground of the substrate.

Further, the conductive member may be a metal layer for heat dissipation and grounding which is formed in contact with the back surface of the semiconductor element. In this case, it is necessary to use a metal layer having an overhanging portion that overhangs from the edge of the semiconductor element. By manufacturing a semiconductor element having a metal layer having an overhang in advance, the connection of the conductive member becomes easy and reliable.
Further, since the heat conduction area is wider than using a metal wire or the like for the conductive member, higher heat dissipation can be expected.

Further, if a strip-shaped structure having a dielectric and a metal layer thereon is used as the conductive member, the conductive member can reach the substrate from the contact point between the conductive member and the back surface of the semiconductor element. Since the length up to the point can be reduced to 1 / 2√ε _eff of the wavelength at the operating frequency of the semiconductor element, the size of the mounting can be further reduced.

[Brief description of the drawings]

FIG. 1A is a schematic structural plan view for explaining a semiconductor device according to a first embodiment, and FIGS. 1B and 1C are for explanation of the first embodiment; FIG.

FIG. 2 is an enlarged view of a main part, which is used for describing the first embodiment.

FIGS. 3A to 3C are schematic process cross-sectional views for explaining a second embodiment.

FIGS. 4A to 4C are schematic process cross-sectional views subsequent to FIG. 3 for describing a second embodiment;

FIG. 5 (A) is provided for explanation of a second embodiment.
It is a schematic structure top view, (B) is a schematic structure sectional drawing used for description of 2nd Embodiment.

FIG. 6A is a schematic structural plan view of a conductive member according to a third embodiment, and FIG. 6B is a schematic structural cross-sectional view of a conductive member.

FIG. 7 (A) is provided for explanation of a third embodiment.
It is a schematic structure top view, (B) is a schematic structure sectional drawing used for description of 3rd Embodiment.

[Explanation of symbols]

 11: Semiconductor device 13: Substrate 15: Semiconductor element, HEMT element 15a: Edge 17: Ceramic substrate 19: Signal line 21: Grounding electrode 23: Grounding plate 25: Through hole 27: Solder bump 29: For heat dissipation and grounding Metal layer 31: Au wire, conductive member 41: Board, quartz board 45: Wax 47: Resist 49a: Metal layer for heat dissipation and grounding 49b: Heat sink 49x: Overhang portion 51: Overhang portion connection bump 61: TAB Tape 63: Metal layer 65: Ground conductor 67: Band-like structure 69: Thin dielectric film 71a: Bump for connecting back surface of semiconductor element 71b: Bump for connecting board

Claims (7)

[Claims] At least a substrate and a flip-flop on the substrate.
A semiconductor device comprising a semiconductor element connected to a chip, wherein a back surface of the semiconductor element and the substrate are connected by a conductive member. 2. The semiconductor device according to claim 1, wherein the conductive member has a shape ranging from a contact point between the back surface of the semiconductor element and the conductive member to a point at which the conductive member reaches the substrate. A semiconductor device, wherein the length is set to half the wavelength at the operating frequency of the semiconductor element. 3. The semiconductor device according to claim 2, wherein said conductive member is a metal wire. 4. The semiconductor device according to claim 2, wherein the conductive member is a conductive heat radiating plate formed in contact with a back surface of the semiconductor element, and the contact point is defined as a contact point of the semiconductor element. A semiconductor device, wherein the bump is provided on the substrate and is a bump around the semiconductor element. 5. The semiconductor device according to claim 1, wherein the conductive member includes a strip-shaped dielectric and a metal layer formed on a surface of the dielectric, and a back surface of the semiconductor element. The length D of the conductive member from the contact point between the conductive member and the conductive member to the point at which the conductive member reaches the substrate is defined as the wavelength of the operating frequency of the semiconductor element as λ. When the effective permittivity is ε _eff , the semiconductor device has a length represented by D = λ / 2√ε _eff . 6. The semiconductor device according to claim 5, further comprising: a bump for connecting a substrate and a bump for connecting a back surface of a semiconductor element, which are provided on the front surface side of the dielectric so as to be electrically connected to the metal layer, respectively. The semiconductor device, wherein the contact point is a bump for connecting the back surface of the semiconductor element, and the reaching point is a bump for connecting the substrate. 7. A step of forming a large number of semiconductor elements on a common board, a step of applying a resist on the board so as to embed the semiconductor elements, and a step of reaching a surface of the semiconductor element. A step of etching back the resist; a step of forming a metal layer for heat dissipation and grounding on the semiconductor element and the resist; a step of cutting the metal layer and the resist between the semiconductor elements; and Removing the resist to leave the semiconductor element and the metal layer.