JPH102248A - Current-carrying control device for electric load - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve control responsiveness in the case of duty control a current of an electric load. SOLUTION: A microcomputer 4 outputting a drive signal Po controlling duty ratio in order to control a current of a solenoid L is provided with a CPU 14 calculating duty ratio of the drive signal Po in each prescribed period to store a count value showing a high level time TON during 1 period TS of the drive signal in a register RON in the inside and a PWM output circuit 16 performing action such as repeatedly counting 1 period TS of the drive signal by a counter also starting counting of a new 1 period TS, at each low outputting the drive signal Po, transmitting a count value from the register RON of the CPU 14 to a self register R2, when a value of the counter leads to a count value in the register R2, inverting the drive signal Po to a high level. Accordingly, the PWM output circuit 16, when the count value in the register RON is changed, is constituted so as to instantaneously transmit the latest count value to the register R2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric load for controlling a current flowing through an electric load by outputting a pulse-shaped driving signal with a controlled duty ratio to a driving means for flowing a current to the electric load. The present invention relates to an energization control device.

[0002]

2. Description of the Related Art Conventionally, for example, in a vehicle, an electromagnetic solenoid type solenoid valve (idle control valve) is provided in a bypass passage which bypasses a throttle valve of an internal combustion engine, and the opening amount of the solenoid valve is adjusted. And controls the idle speed of the internal combustion engine. Further, a shift valve of the automatic transmission is controlled by providing an electromagnetic valve similar to the above in the hydraulic path of the automatic transmission and adjusting the opening amount of the electromagnetic valve.

A control device for performing such idle speed control and shift control is disclosed in Japanese Patent Application Laid-Open No. 61-65048.
As disclosed in Japanese Unexamined Patent Publication (Kokai) No. Hei 4-232360, a pulse-like drive signal with a controlled duty ratio is output to a drive circuit for flowing a current to an electromagnetic solenoid of a solenoid valve. The current flowing through the solenoid is controlled to adjust the opening amount of the solenoid valve.

That is, the average value of the current flowing to the electromagnetic solenoid by the drive circuit can be controlled in accordance with the ratio (duty ratio) of the high level time or the low level time in one cycle of the drive signal. The opening amount of the solenoid valve can be adjusted by the duty ratio of the drive signal. Therefore, in a control device for controlling this type of solenoid valve, a calculation unit such as a CPU (central processing unit) calculates a duty ratio of a drive signal according to a target opening amount of the solenoid valve at every predetermined calculation cycle. Then, a drive signal output logic circuit provided separately from the operation unit outputs the drive signal to the drive circuit at the duty ratio calculated by the operation unit.

More specifically, an arithmetic unit including a CPU and the like, based on the calculated duty ratio, uses the inversion timing in one cycle of the drive signal (that is, starting from the start of one cycle of the drive signal as a starting point). The time until the signal level is inverted is obtained, and data indicating the inversion timing is stored at a specific address of the RAM. On the other hand, the logic circuit for outputting the drive signal has the drive signal 1
A counter for repeatedly counting the period; and a register for storing data indicating the inversion timing during one period of the drive signal, wherein each of the periods of the drive signal detected based on the value of the counter is provided. At the start,
The drive signal is output at either the high level or the low level, and the data stored in the specific address of the RAM is transferred to the register by the arithmetic unit. Thereafter, the counter value is changed to the data value stored in the register. The operation of inverting the output level of the drive signal when they become equal is repeated.

[0006] With such a configuration, it is possible to output a drive signal having a desired duty ratio to the drive circuit without having to execute complicated processing for outputting a drive signal by the arithmetic unit.

[0007]

However, in the above-mentioned conventional control device, it takes a maximum of one cycle of the drive signal before the duty ratio calculated by the arithmetic unit is reflected on the actual output. Thus, there is a problem that there is a limit in improving the control response.

That is, in the above-described conventional control device, as described above, the arithmetic unit and the drive signal output logic circuit operate asynchronously, and the logic circuit operates at the start of one cycle of the drive signal. Since the data stored in the RAM is transferred to its own register, the arithmetic unit calculates the latest duty ratio during one cycle of the drive signal and stores the corresponding data in the RAM. Even
The latest data is reflected on the output only in the cycle of the next drive signal.

[0009] Such a problem is not limited to the case where the electromagnetic valve (electromagnetic solenoid) is controlled, but also applies to the case where the energization to other electric loads is controlled by the duty ratio of the drive signal. Further, the above-mentioned Japanese Patent Application Laid-Open No. 4-232
In Japanese Patent Publication No. 360, an arithmetic unit such as a CPU includes a drive signal 1
It has been proposed that the calculation result of the duty ratio and the output processing of the drive signal are performed at a time interval shorter than the cycle, so that the calculation result is promptly reflected in the output of the drive signal. The processing load on the unit becomes enormous, and other control processes cannot be performed.

The present invention has been made in view of such a problem, and improves control responsiveness when controlling a current to an electric load without increasing a processing load of an arithmetic unit including a CPU and the like. It is an object of the present invention to provide an electric load energization control device that can perform the control.

[0011]

Means for Solving the Problems and Effects of the Invention In order to achieve the above object, an electric load energization control device according to claim 1, wherein a drive means for flowing a current to the electric load has a duty cycle. By outputting a pulse-shaped drive signal whose ratio is controlled, the current flowing through the electric load is controlled, and it includes a calculation unit and a drive signal output unit.

[0012] Then, the arithmetic unit, for each predetermined arithmetic cycle,
Data indicating the duty ratio of the drive signal based on information from the outside and indicating the time from the start of one cycle of the drive signal until the signal level of the drive signal is inverted from the first level to the second level Is stored in a specific storage area.

[0013] On the other hand, the drive signal output unit stores time data that is clocked by repeating one cycle of the drive signal without synchronizing with the calculation cycle of the calculation unit, and data stored in the specific storage area. Storage means for reading the data stored in the specific storage area at that time and storing the data in the storage means each time the timing means starts timing of a new cycle of the drive signal Transfer means, determination means for determining whether or not the time measured by the time measurement means has exceeded the time indicated by the data stored in the storage means, and wherein the time measurement means determines a new cycle of the drive signal. The signal level for setting the signal level of the drive signal to the first level and setting the signal level of the drive signal to the second level when the determination unit makes an affirmative determination each time the time measurement is started. A constant section, in response to a signal level set by the signal level setting means, and said drive signals have an output means for outputting to said driving means.

That is, in the drive signal output unit, the time measuring means
One cycle of the drive signal is repeated and clocked without being synchronized with the calculation cycle of the calculation unit. Each time the timing means starts timing of a new cycle of the drive signal, the data transfer means reads the data stored in the specific storage area at that time, and reads the read data. The signal level setting means sets the signal level of the drive signal to the first level while storing the signal in the storage means.

The determination means determines whether or not the time measured by the time measurement means has exceeded the time indicated by the data stored in the storage means. If the determination means makes an affirmative determination (ie, If it is determined that the time measured by the timer means has elapsed the time indicated by the data stored in the storage means), the signal level setting means sets the signal level of the drive signal to the second level.

The output means outputs a drive signal to the drive means in accordance with the signal level set by the signal level setting means. Is a new driving signal
Each time the timing of the cycle is started, the level becomes the first level, and when the time measured by the timing means elapses the time indicated by the data stored in the storage means, the level is inverted to the second level.

Thus, by the operation of the drive signal output section, the arithmetic section does not execute a special process for outputting the drive signal, and the drive section stores the drive signal in a specific storage area by the arithmetic section. The drive signal is output at a duty ratio according to the data.

Here, if the drive signal output section is simply constructed as described above, as described in the section "Problems to be Solved by the Invention", during one cycle of the drive signal (that is, when Even if the arithmetic unit stores the latest data in a specific storage area between the start of the timing of a new cycle of the drive signal and the start of the timing of the next cycle, the latest data is The output is reflected only in the next cycle of the drive signal.

Therefore, in the power supply control device according to the first aspect, the drive signal output unit is further provided with monitoring means and data changing means. Then, the monitoring means starts the next one after the timing means starts the timing of a new one cycle of the drive signal.
It is monitored whether or not the data stored in the specific storage area has changed from the data stored in the storage means until the timing of the cycle is started, and a change in the data is detected by the monitoring means. Then, the data change means reads the data stored in the specific storage area,
The read data is newly stored in the storage means.

According to the energization control device of the first aspect, the time counting means starts the timing of the new one cycle of the drive signal and starts the timing of the next one cycle.
When the operation cycle of the operation unit arrives and the operation unit stores the latest data different from the previous data in the specific storage area, this is detected by the monitoring unit in the drive signal output unit, and The latest data stored in the storage area is transferred to the storage means by the data change means.

Therefore, at the time of this transfer, the signal level of the drive signal output to the drive means (hereinafter also referred to as the output level of the drive signal) is still the first level (in other words, the time is counted by the timekeeping means). Time has not passed the time indicated by the previous data stored in the storage means),
If the time measured by the time counting means has not passed the time indicated by the latest data newly stored in the storage means, then when the determination means makes a positive determination (that is, the time counting means (When it is determined that the time indicated by the latest data newly stored in the storage means has elapsed), the output level of the driving means is inverted from the first level to the second level.

At the time of the transfer, the output level of the drive signal is still the first level, and the time measured by the timer means has already passed the time indicated by the latest data newly stored in the storage means. If so, an affirmative determination is immediately made by the determining means, and the output level of the driving means is immediately inverted from the first level to the second level.

As described above, according to the power supply control device of the first aspect, the data stored in the specific storage area by the arithmetic unit can be reflected in the current cycle of the drive signal. Without increasing the processing load of the arithmetic unit at all
Control responsiveness when controlling the current to the electric load can be improved.

By the way, in the power supply control device according to the first aspect, when the latest data is transferred to the storage means by the data change means as described above, the output level of the drive signal has already been inverted to the second level. In this case (that is, when the time measured by the clock means has elapsed the time indicated by the previous data stored in the storage means), the time indicated by the latest data newly stored in the storage means has Even if the time has not yet elapsed, the output level of the drive signal remains at the second level until the timing means starts timing of the next one cycle.

Therefore, in the energization control device according to a second aspect, the signal level setting means sets the signal level of the drive signal to the first level while the determination means makes a negative determination. . According to the energization control device of the second aspect, when the latest data is transferred to the storage unit by the data change unit, even if the output level of the drive signal has already been inverted to the second level, the time is measured. If the time measured by the means has not passed the time indicated by the latest data, and the determination means makes a negative determination, the output level of the drive signal returns from the second level to the first level. Then, after that, the time measured by the timer means elapses the time indicated by the latest data, and when the determination means makes an affirmative determination, the output level of the drive signal is again set to the first level.
It will be inverted from the level to the second level.

Therefore, according to the power supply control device of the second aspect, of the output levels of the drive signal, the response of shortening the output time of the second level can be further improved. According to a third aspect of the present invention, in the energization control device for an electric load according to the first or second aspect, the driving unit receives the power supply from a battery mounted on the vehicle and receives the electric power. The arithmetic unit is configured to flow a current to a load, and the calculation unit is configured to detect a voltage of the battery, and, according to a value of the voltage detected by the voltage detection unit, the lower the voltage value, Correction means for correcting the data stored in the specific storage area so that the current flowing to the electric load becomes large.

Further, in the power supply control device according to claim 3, the data change unit of the drive signal output unit converts the data stored in the specific storage area to the data stored in the storage unit. On the other hand, the data stored in the specific storage area is newly stored in the storage unit only when the current flowing to the electric load changes so as to increase.

That is, in the power supply control device according to the third aspect, the drive means is configured to receive the power supply from the battery mounted on the vehicle and to flow the current to the electric load. Even if the duty ratio of the drive signal to be output is the same, if the battery voltage is high, the current that actually flows to the electric load increases, and if the battery voltage is low, the current that actually flows to the electric load decreases. Become.

Therefore, in the power supply control device according to the third aspect of the present invention, in the operation unit, the voltage detecting means detects the voltage of the battery, and the correcting means responds to the value of the battery voltage detected by the voltage detecting means. The lower the voltage value,
The data stored in the specific storage area is corrected so that the current flowing to the electric load becomes large. The voltage correction operation of the arithmetic unit allows a desired current to flow to the electric load even if the battery voltage fluctuates.

However, in a vehicle, although the battery voltage drops for a relatively long time, the battery voltage often rises only momentarily. That is, a decrease in the battery voltage occurs when, for example, an electric device such as an air conditioner or a power window is operated. However, it takes time to return the battery voltage to the normal value by controlling the output of the generator (alternator). . In contrast, a rise in battery voltage only occurs momentarily when an electric device such as an air conditioner or a power window is stopped.

Therefore, when the arithmetic unit detects a rise in the battery voltage and corrects the data stored in the specific storage area so that the current flowing through the electric load becomes small, the corrected data is sent to the driving means. By the time the duty ratio of the output drive signal is reflected, the battery voltage has returned to the normal value. Therefore, the corrected data is converted to the duty ratio of the drive signal output to the drive means. If reflected immediately, the current flowing to the electric load by the driving means may be lower than the original value.

Therefore, in particular, in the energization control device according to the third aspect, the data stored in the specific storage area has a larger current flowing through the electric load than the data stored in the storage means. The data changing means of the drive signal output unit causes the data stored in the specific storage area to be newly stored in the storage means only when the data is changed to the above. By adopting the configuration of the third aspect, it is possible to obtain both the effect of voltage correction in the calculation unit and the high responsiveness of current control.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. It is needless to say that the embodiments of the present invention are not limited to the following examples, and can take various forms as long as they belong to the technical scope of the present invention.

First Embodiment FIG. 1 is a configuration diagram showing the configuration of a vehicle control device 2 according to a first embodiment. The vehicle control device 2 of the present embodiment changes the gear position of the automatic transmission mounted on the vehicle and the electromagnetic solenoid type solenoid valve for switching the lock-up clutch on and off to the operating state of the vehicle. Control according to. The vehicle control device 2 changes the opening amount of the solenoid valve by performing duty control (so-called PWM control) on the current flowing through the solenoid L of the solenoid valve.

As shown in FIG. 1, the vehicle control device 2 includes a microcomputer (hereinafter, simply referred to as a microcomputer) 4 for performing various processing operations and the like for controlling the solenoid valve.
A drive circuit 6 as drive means for receiving a power supply from a battery and flowing a current to an electromagnetic solenoid (hereinafter simply referred to as a solenoid) L of the solenoid valve according to a pulsed drive signal Po output from the microcomputer 4; Based on a current detecting resistor R provided in series with the current path of the solenoid L and a potential difference generated at both ends of the resistor R, the solenoid L
And a current detector 8 that outputs a voltage signal according to a current (hereinafter, referred to as a solenoid current) I actually flowing.

Here, the drive circuit 6 is configured to supply a current to the solenoid L when the signal level of the drive signal Po output from the microcomputer 4 is at a high level higher than a predetermined reference voltage Vref. ing. Thus, the drive signal P is sent from the drive circuit 6 to the solenoid L.
A current corresponding to the duty ratio o flows.
In this embodiment, the reference voltage Vref is set to the center voltage (= 2.5 V) between the ground potential (= 0 V) and the power supply voltage (= 5 V) of the microcomputer 4.
Outputs the drive signal Po as a low level of 0V as a first level and a high level of 5V as a second level. In addition, the duty ratio referred to in the present embodiment is, as shown in FIG. 1, one cycle of the drive signal Po (hereinafter, referred to as a duty cycle).
It indicates the ratio of the high-level time (hereinafter referred to as the on-time) TON in the pulse period TS.

On the other hand, the microcomputer 4 is an I / O for inputting signals from various sensors and switches provided in the vehicle.
A buffer 10; an A / D converter 12 for converting (A / D converting) the voltage signal from the current detector 8 and the battery voltage VB applied to the driving circuit 6 into a digital signal; / O buffer 10 and A / D converter 12
The CPU 14 as an arithmetic unit for calculating the duty ratio of the drive signal Po to be output to the drive circuit 6 at each predetermined calculation cycle based on the information obtained through the CPU, and the drive signal based on the duty ratio calculated by the CPU 14. A PWM output circuit 16 as a drive signal output unit that outputs Po to the drive circuit 6.

Next, the CP provided inside the microcomputer 4
The solenoid control processing executed by U14 and the operation of the PWM output circuit 16 also provided inside the microcomputer 4 will be described. First, FIG. 2 is a flowchart showing a solenoid control process executed by the CPU 14. This process is performed at predetermined time intervals (for example, 4 ms).
Is executed.

As shown in FIG. 2, when the CPU 14 starts the execution of the solenoid control processing, first, in step (hereinafter simply referred to as “S”) 110, the voltage signal from the current detector 8 is A / D A / D conversion is performed by the converter 12 to detect the current solenoid current I.
In the same manner, the battery voltage VB is detected based on the digital signal from the A / D converter 12.

Then, in S130, a target current to be passed to the solenoid L is set according to the driving state of the vehicle based on a sensor signal or the like input via the I / O buffer 10, and detected in S110. Solenoid current I
The duty ratio of the drive signal Po is calculated so that the target current becomes the set target current. The duty ratio is calculated as follows:
This is performed by calculating the pulse period TS and the ON time TON of the drive signal Po. In this embodiment, the pulse period TS is a fixed value, and only the ON time TON is actually calculated. Further, in S130, the count value NON corresponding to the calculated ON time TON is calculated.
And a count value NS corresponding to the pulse period TS.

As described above, the pulse period TS and the ON time T
When the count values NS and NON corresponding to ON are obtained, at S140, the count value NON obtained at S130 is corrected based on the battery voltage VB detected at S120.
In the correction in S140, the count value NON is increased according to the battery voltage VB so that the ON time TON increases (that is, the solenoid current I increases) as the value decreases. to correct.

In S150, the count value NS obtained in S130 is stored in the period register RS, and the count value NON corrected in S140 is stored in the ON time register RON as a specific storage area. S1
After performing the process of 50, the solenoid control process is temporarily terminated. The period register RS and the ON time register RON are RAMs (not shown) accessed by the CPU 14.
In this embodiment, a register provided as hardware inside the CPU 14 is used, as shown in FIG.

FIG. 3 is a flowchart for explaining the operation of the PWM output circuit 16. The PWM output circuit 1
6 is actually configured by hardware using a logic circuit, but here, for convenience of explanation, the operation will be described along a flowchart. First, the PWM output circuit 16 outputs C
It is configured to operate when a command (PWM output command) is received from the PU 14, and as shown in FIG.
4, a first register R1 for storing the count value NS stored in the cycle register RS, and a second register R2 as storage means for storing the count value NON stored in the on-time register RON of the CPU 14. And Further, the PWM output circuit 16 sets the count value NS transferred from the period register RS to the first register R1 as described later, and every time a predetermined reference clock generated in the microcomputer 4 is input once. The counter CNT performs a down-counting operation, and S28 in FIG.
There is also provided an output buffer (not shown) as output means for outputting a drive signal Po to the drive circuit 6 in accordance with a high level or low level output level internally set by an operation such as 0 or S290.

The PWM output circuit 16 has a CPU
3 when no PWM output command is received from
, The drive signal Po to the drive circuit 6 is continuously output at a low level. Then, upon receiving a PWM output command from the CPU 14, the operation shown in FIG. 3 is started, and first, as shown in S210, the CPU 1
4 to read the count values NS and NON stored in the period register RS and the ON time register RON, respectively, and store the count value NS in the first register R1.
The count value NON is stored in the second register R2. That is, the count value NS in the period register RS is transferred to the first register R1, and the count value NON in the on-time register RON is transferred to the second register R2. Further, in the operation of S210, as described above, the first register R1
Is transferred to the counter CNT described above.
Set to.

Next, as shown in S220, the magnitude relationship between the value of the first register R1 and the value of the second register R2 is determined, and the value of the first register R1 is larger than the value of the second register R2. If it is larger (R1> R2), it is determined that it is in the normal state, and the operation proceeds to S230. That is, the first register R1 stores the count value NS corresponding to the pulse period TS of the drive signal Po, and the second register R2 stores the count value NON corresponding to the ON time TON of the drive signal Po. Therefore, in a normal state, the value of the first register R1 is larger.

Then, in the operation of S230, the CPU 14
Current value of the ON time register RON (that is, the current CPU
And the current value of the second register R2 (that is, the count value NON transferred from the on-time register RON to the second register R2 at the time of execution of S210). Are determined to be equal to each other, and if the values of both registers RON and R2 are equal, the operation directly proceeds to the operation of S250. In contrast,
If it is determined in S230 that the values of the two registers RON and R2 are not equal, the subsequent operation of S240 determines that the current CP
The latest count value NON stored in the ON time register RON of U14 is newly transferred to the second register R2, and thereafter, the operation proceeds to S250.

Next, in the operation of S250, the counter CNT
And the value of the second register R2 is determined, and if the value of the counter CNT is larger than the value of the second register R2 (CNT> R2), the process directly proceeds to the operation of S260, and The value of CNT is counted down by one. This down-counting is performed by inputting the reference clock in the microcomputer 4 to the PWM output circuit 16 as described above.

Then, in the subsequent operation of S270, the CPU
It is determined whether or not the output operation of the drive signal Po (PWM output in FIG. 3) is stopped based on whether or not the PWM output command from 14 is continued. If it is determined that the PWM output is not stopped, Then, the operation returns to the operation of S230 described above. If it is determined to stop the PWM output,
The output level of the drive signal Po is forcibly set to the low level, all operations are terminated, and the process waits until a PWM output command from the CPU 14 is received again.

On the other hand, if the count down of the counter CNT in S260 proceeds, and if the value of the counter CNT is determined to be equal to or less than the value of the second register R2 by the determination operation in S250 (CNT ≦ R2), S280 is performed. Then, the output level of the drive signal Po is set to the high level. Then, the drive signal Po output from the output buffer to the drive circuit 6 is inverted from a low level to a high level. Then, after that, S260 and S
Operation 270 is performed.

After that, the counter CNT is further counted down in S260, and if the value of the counter CNT is determined to be “0” by the determination operation in S250 (CNT = 0), the process proceeds to S290. In the operation, the output level of the drive signal Po is set to the low level. Then, the drive signal Po output from the output buffer to the drive circuit 6 returns from the high level to the low level.

Then, in the subsequent operation of S300, S27
As in the case of 0, it is determined whether or not to stop the PWM output. If it is determined that the PWM output is not to be stopped, the process returns to the above-described step S210, and at that time, the period register RS of the CPU 14 and the on-time The count values NS and NON stored in the register RON are transferred to the first register R1 and the second register R2, respectively, and the count value NS transferred to the first register R1 is set in the counter CNT. Then, the operation after S220 is repeated. If it is determined in step S300 that the PWM output is to be stopped, the output level of the drive signal Po is forcibly set to the low level, all the operations are terminated, and the PWM output command from the CPU 14 is received again. Wait until.

On the other hand, in the determination operation of S220, the first
Whether the value of the register R1 is equal to or less than the value of the second register R2 (R1 ≦ R2), whether the value of the first register R1 is “0” (R1 = 0), or the value of the second register R2 is “0” "
(R2 = 0), it is determined that the state is not the normal state, and the operation shifts to S310.

Then, in S310, the second register R2
It is determined whether or not the value of “0” is “0”.
The ON time TON of the drive signal Po calculated by the CPU 14 is "0" and the count value NON stored in the ON time register RON is "0".
In step 90, the output level of the drive signal Po is set to the low level, the drive signal Po output from the output buffer to the drive circuit 6 is forced to the low level, and then the determination operation of S300 is performed.

When the value of the second register R2 is determined not to be "0" in the determination operation of S310, that is,
When the value of the first register R1 is equal to or less than the value of the second register R2, or when the value of the first register R1 is "0", the CPU 14 is not in a normal setting state,
It is determined that the ON time TON of the drive signal Po calculated by the above is not “0” but a current should be passed to the solenoid L, and the operation proceeds to S320. Then, by setting the output level of the drive signal Po to the high level in the operation of S320, the drive signal Po output from the output buffer to the drive circuit 6 is forcibly set to the high level, and then the determination operation of S300 is performed. I do.

That is, in the PWM output circuit 16, the CPU
When a PWM output command is received from the
The count value NS corresponding to the pulse cycle Ts stored in the cycle register Rs of U14 is transferred to the first register R1 and set in the counter CNT. At the same time, the count value NS is stored in the on-time register RON of the CPU 14. The count value NON corresponding to the ON time TON is transferred to the second register R2 (S210).

Then, the count value N to the counter CNT is obtained.
After the setting of S and the transfer of the count value NON to the second register R2, the counter CNT is down-counted every time the reference clock in the microcomputer 4 is input (S260). The time until the value becomes “0” (S250: CNT = 0) is measured as the pulse period TON of the drive signal Po. During the time measurement, the value of the counter CNT is stored in the second register R2. Value (that is, the count value NON) or less (S250: CN
T ≦ R2), the output level of the drive signal Po is inverted from the low level to the high level (S280), and thereafter, when the value of the counter CNT becomes “0” (S250: CNT)
= 0), assuming that the current pulse period TS has elapsed, the output level of the drive signal Po is returned from the high level to the low level (S290).

Then, when the value of the counter CNT becomes "0" and the clocking of the current pulse period Ts ends, S
The operation of the CPU 210 is performed, and the count value NS stored in the cycle register RS of the CPU 14 at that time is set in the counter CNT.
The count value NON stored in the ON time register RON of No. 4 is transferred to the second register R2 to start measuring the next pulse period TS of the drive signal Po, and the above operation is repeated.

Therefore, in this PWM output circuit 16, C
The pulse cycle TS of the drive signal Po is repeatedly measured by the counter CNT without being synchronized with the execution cycle of the solenoid control processing by the PU 14. And the counter C
Each time the value of NT becomes "0" and the timing of a new next pulse period TS of the drive signal Po is started, CP at that time is started.
The count value NON corresponding to the ON time TON stored in the ON time register RON of U14 is transferred to the second register R2, the output level of the drive signal Po becomes low level, and the value of the counter CNT becomes the second register R2. When the count value is less than or equal to the count value NON, the operation of inverting the output level of the drive signal Po to a high level is repeated.

As a result, the pulse period TS of the drive signal Po output from the PWM output circuit 16 to the drive circuit 6
Is the time obtained by multiplying the count value NS stored in the cycle register RS of the CPU 14 by the cycle of the reference clock.
Similarly, the ON time TON of the drive signal Po during the pulse period TS is determined by the ON time register RON of the CPU 14.
Is multiplied by the period of the reference clock, and the drive signal Po has a pulse period TS.
When the time obtained by multiplying the value obtained by subtracting the count value NON from the count value NS (NS-NON) by the period of the reference clock has elapsed from the start of the operation, the output level is inverted from the low level to the high level. . That is, in the present embodiment, the count value NON is used as data indicating the time from the start of one cycle of the drive signal to the inversion of the signal level of the drive signal.

In particular, the PWM output circuit 1 of this embodiment
In step 6, after the counter CNT starts measuring a new pulse period TS of the drive signal Po, the next pulse period T
By the operation of S230, it is determined whether the count value NON stored in the on-time register RON of the CPU 14 has changed from the count value NON stored in the second register R2 before the time measurement of S is started. When monitoring is performed constantly and a change in the count value NON is detected (S230: NO),
At this time, the latest count value NON stored in the ON time register RON of the CPU 14 is read out and newly stored in the second register R2 (S240).

In the first embodiment, S210 and S260 correspond to the operation as the time measuring means.
Corresponds to the operation as the data transfer unit, S250 corresponds to the operation as the determination unit, and S280 and S290 correspond to the operation as the signal level setting unit. Further, S230 corresponds to the operation as the monitoring means,
240 corresponds to the operation as data changing means.

Next, the basic operation of the microcomputer 4 including the CPU 14 for executing the solenoid control processing of FIG. 2 and the PWM output circuit 16 for performing the operation of FIG. S23 shown in FIG.
A description will be given with reference to the time chart of FIG. 4 showing the operation of the microcomputer 4 when the operations of 0 and S240 are not performed.
Note that in FIG. 4 and FIGS.
The output Po ”indicates the output level of the drive signal Po.

As shown in FIG. 4, first, the CPU 14 executes the solenoid control processing of FIG. 2 at the timing of time t1, and accordingly, the cycle register RS and the on-time register RON correspond to the pulse cycle TS, respectively. Count value N
It is assumed that S and a count value NON1 corresponding to the ON time TON1 are stored.

Then, in the PWM output circuit 16, the value of the counter CNT becomes “0” after that, and at the time t 2 when the drive signal Po becomes low level, the CPU 14
The count value NS stored in the period register RS of the first
The value is transferred to the register R1 and set in the counter CNT.
ON1 is transferred to the second register R2 to start counting down the counter CNT.

Then, the PWM output circuit 16 changes the drive signal Po from the low level to the high level at the time t3 when the value of the counter CNT to be counted down and the value of the second register R2 (ie, the count value NON1) match. After that, at the time t4 when the value of the counter CNT becomes “0”, the drive signal Po is again inverted from the high level to the low level. At the same time, the count value NS stored in the cycle register RS of the CPU 14 is set again in the counter CNT, and
The count value NON1 stored in the ON time register RON of the PU 14 is transferred to the second register R2, and the counter CNT starts counting down again. Therefore, time t
The time from 2 to time t4 is the pulse period TS corresponding to the count value NS, and the time from time 3 to time t4 is the ON time TON1 corresponding to the count value NON1.

In this embodiment, as described above, the CP
The pulse period Ts calculated by U14 is a fixed value, and a constant count value NS is always stored in the period register RS. Therefore, in the following, the operation in which the CPU 14 stores the count value NS in the period register RS will be described. , PWM
The description of the operation of the output circuit 16 for setting the count value NS to the counter CNT will be omitted.

Next, for example, as shown at time t5, the drive signal Po is inverted from high level to low level and PWM
Immediately after the output circuit 16 starts measuring a new pulse period T S, the CPU 14 executes the solenoid control processing of FIG. 2 and stores the count value N ON2 corresponding to the latest on-time T ON2 in the on-time register R ON. I do.

At this time, if the PWM output circuit 16 does not perform the operations of S230 and S240 shown in FIG.
The value of the second register R2 remains the count value NON1 transferred from the on-time register RON at the timing of the time t4 (that is, the count value NON1 stored in the on-time register RON by the CPU 14 at the time t1).

Therefore, the PWM output circuit 16
At the time t6 when the value of the counter CNT matches the value of the second register R2 (that is, the count value NON1), the drive signal Po is inverted from the low level to the high level, and thereafter, the value of the counter CNT becomes "0". , The drive signal Po is inverted from the high level to the low level. Only at the timing of time t7, the latest count value NON2 stored in the ON time register RON of the CPU 14 is stored in the second register RON.
2 and the counter CNT starts counting down again.

Then, the PWM output circuit 16 outputs the signal at time t7.
After starting time measurement of the next pulse period TS, the counter C
NT and the value of the second register R2 (that is, the count value N
ON2), the driving signal Po is inverted from the low level to the high level at the timing of time t8, and thereafter,
At the timing of time t9 when the value of the counter CNT becomes “0”, the drive signal Po is again inverted from the high level to the low level.

Therefore, in the pulse cycle (pulse cycle TS from time t7 to time t9) subsequent to time t5 when the CPU 14 executes the solenoid control processing, the time from time t8 to time t9 corresponds to the count value NON2. The ON time TON2 is reached. Thereafter, for example, before time t9, if the CPU 14 stores the count value NON3 corresponding to the next ON time TON3 in the ON time register RON,
At this time t9, the PWM output circuit 16
The count value NON3 is transferred to the second register R2, and the counter CNT starts counting down again.

As described above, the PWM output circuit 16
In the case where the operations of S230 and S240 shown in (1) are not performed, as shown at time t5, during one cycle (pulse cycle) TS of the drive signal Po, the CPU 14 makes the latest ON time TON2
Is calculated and the corresponding count value NON2 is stored in the on-time register RON, the count value NON2 is reflected on the output of the drive signal Po only in the next pulse period TS.

Therefore, in the PWM output circuit 16 provided in the microcomputer 4 of this embodiment, S230 and S24 in FIG.
By the operation of 0, it is constantly monitored whether or not the count value NON stored in the on-time register RON of the CPU 14 has changed from the count value NON currently stored in the second register R2. Upon detection, the latest count value NON stored in the on-time register RON at that time is newly transferred to the second register R2.

The operation of the PWM output circuit 16 by performing the operations of S230 and S240 shown in FIG. 3 will be described below with reference to FIGS. Times t3, t4, and t7 shown in FIGS. 5 and 6 correspond to time t3 shown in FIG.
3, the same timings as t4 and t7 are shown. FIG. 5 shows a pulse cycle T from time t4 to time t7.
During the period S, the CPU 14 executes the solenoid control processing to count the count value NON stored in the on-time register RON.
Is changed from "NON1" to "NON2", which is a larger value. FIG. 6 shows that the CPU 14 executes the solenoid control process during the pulse period TS from time t4 to time t7. This shows a case where the count value NON stored in the on-time register RON has been changed from "NON1" to "NON2" which is a smaller value. Also,
The dotted lines in FIG. 5 and FIG. 6 show the state when the PWM output circuit 16 does not perform the operations of S230 and S240 shown in FIG.

First, as shown in FIG. 5A, at time t4
, The PWM output circuit 16 starts measuring a new pulse period Ts, and when the output level of the drive signal Po is still at the low level (in other words, the count of the counter CNT is stored in the second register R2). When the value NON1 has not yet been reached), as shown at time t5, the CPU 14
Executes the solenoid control process and turns on the ON time register RON.
The count value NON in the range from “NON1” to “NON2 (> NON
1), the PWM output circuit 16 detects that the count value NON has been changed by the operation of S230 in FIG. 3, and by the operation of S240 in FIG. 3, the changed latest count value NON2. Is immediately transferred to the second register R2.

Then, as illustrated in FIG. 5A, at time t5 when the latest count value NON2 is transferred to the second register R2, the value of the counter CNT is still larger than the latest count value NON2. For example, the output level of the drive signal Po is then changed to the count value N
At time t6 ', which coincides with ON2, the signal is inverted from low level to high level, and the value of the counter CNT becomes "0".
At time t7, the high level returns to the low level.

Therefore, in this case, the time from time t6 ′ to time t7 is the ON time TON2 corresponding to the latest count value NON2, and the latest count value NON2 changed at time t5 is The driving signal Po is faithfully reflected in the cycle TS (pulse cycle TS from time t4 to time t7).

As shown in FIG. 5B, when the output level of the drive signal Po is still at the low level,
As shown at time t5 ', the CPU 14 changes the count value NON in the on-time register RON from "NON1" to "NON2 (>
NON1) ", and when the PWM output circuit 16 transfers the changed latest count value NON2 to the second register R2, the value of the counter CNT is already less than the latest count value NON2. Is the output level of the drive signal Po, the latest count value NON2 is the second register R2
At time t5 ', the signal is immediately inverted from low level to high level.
At the time t7 when the value of the data becomes "0", the level returns from the high level to the low level.

Accordingly, in this case, the ON time TON becomes the time TON2 'from the time t5' to the time t7, which is shorter than the ON time TON2 corresponding to the latest count value NON2. Is the previous count value N
The ON time TON1 corresponding to ON1 is longer than the ON time. As a result, the latest count value NON2 (>) changed at time t5.
NON1) to the drive signal P in the current pulse cycle TS.
o can be reflected in the output.

On the other hand, as shown in FIG. 6A, when the output level of the drive signal Po is still at the low level, as shown at time t5, the CPU 14 sets the count value NON in the on-time register RON to "NON1". To “NON2 (<NON1
) ", The PWM output circuit 16 immediately transfers the updated latest count value NON2 to the second register R2, as in the case of FIG. Then, the output level of the drive signal Po is thereafter changed at the timing of time t6 ″ when the value of the counter CNT matches the count value NON2.
The signal is inverted from the low level to the high level, and returns from the high level to the low level at the time t7 when the value of the counter CNT becomes “0”.

In this case, the time from time t6 ″ to time t7 is the ON time TON2 corresponding to the latest count value NON2, and the latest count value NON2 changed at time t5 is the current pulse value NON2. Drive signal P with period TS
This will be faithfully reflected in the output of o.

As shown in FIG. 6B, the drive signal P
After the output level of the counter o is inverted to the high level (in other words, after the value of the counter CNT becomes equal to or less than the count value NON1 stored in the second register R2), the time t
As in 5 ", the CPU 14 changes the count value NON in the on-time register RON from" NON1 "to" NON2 (<NON1) ".
, The ON time TON becomes the time TON1 corresponding to the previous count value NON1 in the current pulse cycle TS.
And the count value NON after the change in the next pulse cycle TS
2 is the time TON2 corresponding to 2. Such an operation is performed when the count value NON in the on-time register RON is “N
ON1 ”to a larger value“ NON2 (> NON1
The same applies to the case where ")" has been changed.

As described in detail above, according to the microcomputer 4 provided in the vehicle control device 2 of the first embodiment, when the output level of the drive signal Po is still low, the CPU 14
Is the count value N corresponding to the ON time TON of the drive signal Po.
When ON is changed, the count value NON after the change is reflected in the output in the current pulse cycle TS of the drive signal Po.
Therefore, according to the microcomputer 4 of the first embodiment, the CPU 1
The control responsiveness when controlling the current to the solenoid L can be improved without increasing the processing load of No. 4 at all.

[Second Embodiment] By the way, in the microcomputer 4 of the first embodiment, as shown in FIG.
14 changes the count value NON in the on-time register RON, the PWM output circuit 16
, The output level of the drive signal Po has already been inverted to a high level (that is, the value of the counter CNT has been stored in the second register R2). If the previous count value NON is less than or equal to), even if the value of the counter CNT at that time is larger than the latest count value NON, the output level of the drive signal Po is such that the value of the counter CNT is "0". Until it reaches "".

Therefore, in the vehicle control device according to the second embodiment described below, the PWM output circuit 16 in the microcomputer 4 is configured to perform the operation shown in FIG. 7 instead of the operation shown in FIG. ing. That is, the PWM output circuit 1 of the second embodiment
In FIG. 6, as shown in FIG. 7, when it is determined that the value of the counter CNT is larger than the value of the second register R2 by the determination operation of S250 (CNT> R2), the operation of S255 is additionally performed. , The output level of the drive signal Po is set to a low level, and thereafter, the operation shifts to S260. That is, the counter CN is determined in the determination operation of S250.
While it is determined that the value of T is larger than the value of the second register R2, the output level of the drive signal Po is set to the low level. Operations other than S255 are exactly the same as those in the first embodiment.

In the first embodiment, the additional steps S255, S280 and S290 correspond to the operation as signal level setting means. According to the microcomputer 4 of the second embodiment, after the output level of the drive signal Po is inverted to the high level as shown in FIG. 8 showing the same situation as that of FIG. For example, after the value of the counter CNT becomes equal to or less than the count value NON1 already stored in the second register R2), the CPU 14 sets the count value NON in the on-time register RON at time t5 ″.
From “NON1” to a smaller value of “NON2 (<N
ON1) ", if the value of the counter CNT at that time is larger than the latest count value NON2, the output level of the drive signal Po returns from the high level to the low level. Then, the output level of the drive signal Po is thereafter inverted from the low level to the high level again at the time ta at which the value of the counter CNT becomes equal to or less than the latest count value NON2, and thereafter, the value of the counter CNT becomes "0". At the time t7, the level returns from the high level to the low level.

Therefore, according to the microcomputer 4 of the second embodiment, of the output levels of the drive signal Po, the responsiveness of shortening the high-level output time (ON time TON) is further improved. be able to. Third Embodiment Next, a vehicle control device according to a third embodiment will be described. The vehicle control device of the third embodiment differs from the vehicle control device 2 of the first embodiment in that the PWM output circuit 16
However, it is configured to perform the operation shown in FIG. 9 instead of the operation shown in FIG.

That is, in the PWM output circuit 16 of the third embodiment, as shown in FIG. 9, it is determined by the determination operation of S230 that the current value of the on-time register RON and the current value of the second register R2 are not equal. In this case, the determination operation in S235 is additionally performed. Then, in the operation of S235,
It is determined whether or not the current value of the on-time register RON is greater than the current value of the second register R2.
If the current value of ON is larger than the current value of the second register R2, the operation of the following S240 is performed, and the latest count value NON stored in the on-time register RON at that time is stored in the second register R2. When the current value of the on-time register RON is not larger than the current value of the second register R2, the transfer to S2 is performed without performing the transfer operation of S240.
Proceed to operation 250. Operations other than S235 are exactly the same as those in the first embodiment.

That is, the PWM output circuit 16 of the third embodiment
Now, the count value N stored in the on-time register RON
ON is the count value N stored in the second register R2.
Only when the ON time TON changes with respect to ON so that the ON time TON becomes longer (in other words, the current flowing through the solenoid L increases), the operation of S240 is executed, and the ON time TON is stored in the ON time register RON. Latest count value NON
Is immediately transferred to the second register R2.

Here, the PWM output circuit 16 operates in step S23.
The reason for adding the operation 5 will be described. First,
In the vehicle control device of the present embodiment, the drive circuit 6 is configured to receive the power supply from the battery and flow the current to the solenoid L, so that the duty ratio of the drive signal Po output to the drive circuit 6 is Even if they are the same, the solenoid current I increases when the battery voltage VB is high, and conversely, the solenoid current I decreases when the battery voltage VB is low.

For this reason, in the vehicle control device of this embodiment,
The CPU 14 executes S120 in the solenoid control process (FIG. 2).
, The battery voltage VB is detected, and in S140 of the same process, based on the battery voltage VB detected in S120, the ON time TON of the drive signal Po decreases as the voltage value decreases.
Is made longer (that is, the solenoid current I becomes larger), the count value NON obtained in S130 is corrected to a larger value. By performing such a voltage correction, even if the battery voltage VB fluctuates,
A desired current can be supplied to the solenoid L.

However, “means for solving the problem,
As described in the section “Effects of the Invention”, in a vehicle, the decrease in battery voltage VB continues for a relatively long time, but the increase in battery voltage VB often occurs only momentarily. Therefore, when the CPU 14 detects the rise in the battery voltage VB and corrects the count value NON stored in the on-time register RON so that the solenoid current I becomes small (that is, when the CPU 14 corrects the count value NON to a small value). ) By the time the corrected count value NON is reflected in the duty ratio of the drive signal Po output to the drive circuit 6, the battery voltage VB has returned to the normal value. Later count value NON
Is immediately reflected in the duty ratio of the drive signal Po output to the drive circuit 6, the drive circuit 6
There is a possibility that the current flowing to the lower side becomes lower than the original target current.

In particular, in the third embodiment, the count value NON stored in the on-time register RON changes so that the on-time TON becomes longer than the count value NON stored in the second register R2. S24 only if
0, the latest count value NON stored in the on-time register RON is immediately updated to the second register R2.
To be transferred to

According to the vehicle control apparatus of the third embodiment, the effect of the voltage correction processing executed by the CPU 14 in S120 and S140 of the solenoid control processing, and the high responsiveness of the current control to the solenoid L, To
You will be able to get both.

In the third embodiment, the additional steps S235 and S240 correspond to the operation as data changing means. On the CPU 14 side, in the solenoid control processing of FIG. 2, S120 corresponds to processing as voltage detection means, and S140 corresponds to processing as correction means.

[Others] When the value of the counter CNT becomes “0”, the PWM output circuit 16 of each of the above embodiments
The output level of the drive signal Po is set to the low level, and the value of the counter CNT is changed to the count value N stored in the second register R2.
The output level of the drive signal Po is inverted from a low level to a high level when it becomes lower than ON. That is, the first
Although the level is a low level and the second level is a high level, the low level and the high level may be reversed.

For example, in the case of the third embodiment, the CPU 14
(1), (2)
And the PWM output circuit 16 may be changed as shown in (3) and (4) below. (1) In S130 of the solenoid control process (FIG. 2), a low level time (off time) TOFF during the pulse period TS of the drive signal Po is calculated, and a count value NOFF corresponding to the off time TOFF is obtained.

(2) Then, S1 of the solenoid control processing
At 40, the count value NOFF obtained at S130 is corrected so that the OFF time TOFF becomes shorter as the battery voltage VB becomes lower. At S150, the count value NOFF after the correction is changed to the above-mentioned ON time. Register RON
To be stored.

(3) On the other hand, in the PWM output circuit 16, the output level of the drive signal Po is set to the high level by the operation of S290 in FIG. 9, and S280 and S320 in FIG.
With the operation described above, the output level of the drive signal Po is set to the low level. (4) Further, in the PWM output circuit 16, S in FIG.
In the determination operation at 235, only when the current value of the on-time register RON (that is, in this case, the count value NOFF corresponding to the latest off-time TOFF) is smaller than the current value of the second register R2. , S240.

[0100] Even with this configuration, the same effect as that of the third embodiment can be obtained. Note that the concept of reversing the low level and the high level is exactly the same for the first embodiment and the second embodiment. The microcomputer 4 of each of the above embodiments is used to control an electromagnetic valve for an automatic transmission. For example, the microcomputer 4 is an electromagnetic solenoid type idle that is interposed in an auxiliary air passage that bypasses a throttle valve of an internal combustion engine. Control valve (ISCV)
For example, the present invention can be similarly used for duty control of another electromagnetic valve requiring high control responsiveness or another electric load such as a lamp.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a configuration of a vehicle control device according to a first embodiment.

FIG. 2 is a flowchart illustrating a solenoid control process executed by a CPU according to the first embodiment.

FIG. 3 is a flowchart illustrating an operation of the PWM output circuit according to the first embodiment.

FIG. 4 is a block diagram showing a PWM output circuit according to the first embodiment;
6 is a time chart for explaining the operation of the microcomputer when the operations of 0 and S240 are not performed.

FIG. 5 is a time chart illustrating an operation when the CPU changes the count value corresponding to the ON time to a large value in the microcomputer of the first embodiment.

FIG. 6 is a time chart illustrating an operation when the CPU changes the count value corresponding to the ON time to a small value in the microcomputer of the first embodiment.

FIG. 7 is a flowchart illustrating an operation of the PWM output circuit according to the second embodiment.

FIG. 8 is a time chart for explaining the operation of the second embodiment.

FIG. 9 is a flowchart illustrating an operation of the PWM output circuit according to the third embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 2 ... Vehicle control apparatus 4 ... Microcomputer (microcomputer) 6 ... Drive circuit 8 ... Current detector 10 ... I / O buffer 12 ... A / D converter 14 ... CPU 16 ... PWM
Output circuit L: Electromagnetic solenoid R: Resistor RON: ON time register RS: Period register R1: First register R2 ...
Second register

Claims (3)

[Claims] 1. An electric load energization control device for controlling a current flowing through an electric load by outputting a pulse-shaped driving signal having a controlled duty ratio to a driving means for flowing a current to the electric load. Calculating a duty ratio of the drive signal based on information from outside for each predetermined calculation cycle, and starting from one cycle of the drive signal as a starting point, changing the signal level of the drive signal from the first level to the first level; An arithmetic unit for storing data indicating a time required for inversion to two levels in a specific storage area; and 1 of the drive signal without being synchronized with the arithmetic cycle of the arithmetic unit.
Clocking means for repeating a cycle, and storage means for storing data stored in the specific storage area,
A data transfer unit that reads data stored in the specific storage area at that time and stores the read data in the storage unit each time the timing unit starts timing of a new cycle of the drive signal; Determining means for determining whether or not the time measured by the means has exceeded the time indicated by the data stored in the storage means; and each time the time measuring means starts measuring a new cycle of the drive signal. Signal level setting means for setting the signal level of the drive signal to the first level, and when the determination means makes a positive determination, setting the signal level of the drive signal to the second level; An output unit that outputs the drive signal to the drive unit in accordance with the signal level set by the setting unit; and a drive signal output unit that further comprises: The data stored in the specific storage area is stored in the storage unit during a period from when the timing unit starts measuring a new cycle of the drive signal to when the next one cycle starts counting. Monitoring means for monitoring whether there has been a change from the data being read, and when a change in the data is detected by the monitoring means, the data stored in the specific storage area is read, and the read data is read. And a data changing means for newly storing the data in the storage means. 2. The control apparatus according to claim 1, wherein the signal level setting unit sets the signal level of the drive signal to the first level while the determination unit makes a negative determination. And a power supply control device for an electric load. 3. The current supply control device for an electric load according to claim 1, wherein the drive unit receives a power supply from a battery mounted on a vehicle and causes a current to flow to the electric load. The arithmetic unit is configured to: store the voltage in the specific storage area as the voltage value is lower according to the voltage value detected by the voltage detecting means, and the voltage value detected by the voltage detecting means. Correction means for correcting the data to be processed so that the current flowing through the electric load is large.The data change means further stores the data stored in the specific storage area in the storage means. Only when the current flowing through the electric load changes with respect to the stored data, the data stored in the specific storage area is newly stored in the storage unit. A power supply control device for an electric load.