KR930000259B1 - Source supplying method for stepping motor - Google Patents

Abstract

The method is for providing uniform power to a stepping motor regardless of input power variation. The method comprises: (A) starting count action of period of oscillated frequency when oscillated frequency is generated; (B) stopping the count action when oscillated frequency generation is stopped, and analyzing counter data; (C) calculating variation interval of a first power by comparing counter data and reference data; (D) setting output period of power control signal to provide uniform power to a stepping motor; (E) transmitting power control signal to a power selection unit and phase signal of step driving data to a motor driving unit.

Description

Uniform power supply method of stepping motor

1 is a conventional stepping motor driving circuit diagram.

2 is a conventional stepping motor driving circuit diagram.

3 is a driving power waveform diagram of the step motor according to the step drive data.

4 is a uniform power supply waveform diagram according to the state of the first power supply.

5 is a drive circuit diagram of a stepping motor for carrying out the present invention.

6 is an operational waveform diagram of FIG.

7 is a flow chart of the present invention.

8 is an interrupt processing flow diagram.

* Explanation of symbols for main parts of the drawings

10: CPU 20: voltage detector

30: voltage controlled oscillator 40: end gate

50: power selector 60: motor drive

The present invention relates to a method of driving a stepping motor. In particular, the present invention relates to a method for supplying a uniform driving voltage to a stepping motor regardless of a change in power supply.

In general, a stepping motor uses a dual power supply (dua1 vo1tage). When a change in power supply voltage occurs due to a regional difference or a change in the surrounding power environment, the power supplied to the stepping motor according to the change ) Changes accordingly, which greatly affects the life and performance of the stepping motor. Therefore, power must be supplied to the stepping motor regardless of the change in the power supply voltage as described above. Conventionally, this has been implemented in the same manner as in FIG.

를 통해 스텝구동데이타(A, B,

)를 출력할시, 포트 P15로 제1전원(VH) 및 제2전원(V1)을 선택하기 위한 전원제어신호를 반생한다. 이때 상기 스텝구동데이타(A,B,

)출력시점에서 상기 CPU(1)은 상기 전원제어신호를 “하이”상태로 하여 P15포트로 출력하고, 소정시간 (TW)이 지난 뒤에 상기 전원제어신호를 “로우”상태로 천이시킨다. 이때 상기 CPU(1)로부터 발생되는 전원제어신호에 의해 전원선택부(2)의 트렌지스터(Q5,Q6)가 스위칭되며, 이로인해 상기 전원선택부(2)는 제3도에 도시된 바와 같이 상기 전원제어신호의 논리에 따라 연결되어 있는 제1전원(VH) 또는 제2전원(V1)을 선택하여 코일(11-14)로 인가한다. 또한 상기 CPU(1) 포트 PA, PB, P,

를 통해 출력되는 스텝구동데이타(A, B,

)의 상태에 따라 모터구동부(3)의 트랜지스터(Q1-Q4)가 스위칭되어 상기 코일(11-14)의 전류통로를 형성한다. 따라시 스테핑 모터는 상기 트렌지스터(Q1-Q4)의 스위칭 상태 및 코일(L1-L4)의 전류 흐름 상태에 따라 스텝 단위로 구동되는 것이다.First, referring to FIG. 1, a process of driving a stepping motor with the first power VH and the second power V1 is described. In the CPU 1, the ports PA, PB,

Step drive data (A, B,

) Outputs a power control signal for selecting the first power supply VH and the second power supply V1 to the port P15. At this time, the step driving data (A, B,

At the time of outputting, the CPU 1 outputs the power control signal to the P15 port in a "high" state, and transitions the power control signal to a "low" state after a predetermined time (TW). At this time, the transistors Q5 and Q6 of the power selector 2 are switched by the power control signal generated from the CPU 1, which causes the power selector 2 to operate as shown in FIG. The first power source VH or the second power source V1 connected to the coil 11-14 is selected according to the logic of the power control signal. In addition, the CPU (1) port PA, PB, P,

Step driving data (A, B,

The transistors Q1-Q4 of the motor driver 3 are switched to form the current path of the coils 11-14 according to the state of. Accordingly, the stepping motor is driven in step units according to the switching state of the transistors Q1-Q4 and the current flow state of the coils L1-L4.

At this time, the first power source VH is a power of 4-5 times that of the second power source V1 and is applied to the coil 11-14 at the time of step driving data generation, and is driven at a high speed by a stepping motor. If a change occurs according to the influence of the surrounding environment of (VH), when an error occurs in the power supplied to the stepping motor, the performance of the stepping motor is reduced. Therefore, as shown in FIG. 4, when the voltage rises to the VH1 voltage according to the change of the first power supply VH, the pulse width is reduced, and when the voltage falls to the VH2 voltage, the fill width is increased to equalize the power applied to the stepping motor. Should give

In order to solve the above problem, conventionally, the first power supply VH is input to the comparison terminal of the comparators CM11-CM4, and the reference terminal has a level shifted by the resistors R1--R5. Two reference voltages are input to sense a change state of the first power supply VH. That is, the CPU 1 reads the output of the comparator CMI-CM4 received through the ports P11-P14 in step A1, and then performs a priority encoder process in step A2. The reason why priority encoder processing is performed in step (A2) is that the output data of a parallel A / D converter composed of comparators (CM1-CM4) must be digitally converted in accordance with the priority encoder. to be.

After that, the CPU 1 calculates a difference between the data received through the comparators CM1-CM4 and the reference data TW in step (A3), and in step (A4) the first power source VH according to the difference. Calculate the enable time. That is, as shown in FIG. 4, in the case of the first power supply VH having a normal value, the first power supply VH may be supplied during the normal time TW. However, the first power supply rises to the level of the VH1 voltage. If it is determined that the case, the power control signal should be generated by subtracting ΔTW, which is the time corresponding to the rise in TW. When it is determined that the first voltage falls to the level of the VH2 voltage, a power control signal must be generated by adding ΔTW corresponding to the falling portion in TW. Therefore, in step (A4), the pulse width of the power supply control signal is determined by subtracting or adding the D TW time from TW in the state of the first power source VH.

)를 처리하여, (6)단계에서 상기(A4)단계에서 구한 전원제어신호와(A5)단계에서 구한 스텝 구동 데이타를 출력한다. 따라서 상기 제1전원(VH)이 설정된 전압 레벨보다 크면 상기 전압제어신호의 TW펄스폭을 감소시커 진압레벨을 일정하게 하고, 상기 설정된 전압 래벨보다 작으면 상기 전압제어신호의 TW펄스폭을 증가시켜 역시 상기 제1전원(VH)의 레벨을 설정한 레벨로 유지될 수 있도록 한다.In the subsequent step (A5), the CPU 1 performs step driving data (A, B,

), And outputs the power control signal obtained in step (A4) and the step driving data obtained in step (A5) in step (6). Therefore, when the first power supply voltage VH is greater than the set voltage level, the TW pulse width of the voltage control signal is decreased, and the suppressor suppression level is constant, and when it is smaller than the set voltage level, the TW pulse width of the voltage control signal is increased. Also, it is possible to maintain the level of the first power source VH at a set level.

However, when driving the stepping Morty using a double power source as described above, since the first power source (VH) is 4-5 times the second power source (V1) is not a constant voltage state, the change in power supply level is very severe. . Therefore, when there is a fluctuation of the input power voltage due to regional differences and the surrounding power environment, the change of the first power supply VH also occurs. At this time, if the rated allowable range of the input AC voltage is + 15%, -15%, since the fluctuation range of the first power source (VH) is 30%, the performance of the stepping motor is degraded by the variation of the power source. Therefore, in the parallel A / D converter used in the conventional method, the quantization error of the digitally converted data during the A / D conversion becomes quite large. In other words, assuming that the fluctuation range of the first power supply VH is 12V in FIG. 1, since four comparators are used, the resolution of the first power supply VH becomes 4V, regardless of the change of the first power supply V1I. The power specified by the stepping motor could not be supplied. In addition, since the detection voltage of the first power source VH varies according to the values of the resistors R1-R5 that repeat the reference voltages of the comparators CM1-CM4, only a voltage within a predetermined range can be detected. Also, it is difficult to improve the resolution because the number of comparators must be increased to reduce the quantization error. For example, if you want to improve the resolution twice, you need to double the number of comparators. As can be seen from the above, in the conventional stepping motor driving circuit, since the quantization error during the A / D conversion was large, it was not possible to supply stable uniform power to the stepping motor regardless of the state of the A / D power supply. In order to increase the number of comparators, a number of comparators had to be added.

Accordingly, an object of the present invention is to oscillate a frequency in accordance with a change state of the first power source in a driving circuit of a stepping motor using a dual power source consisting of a first power source having a high voltage and a second power source of another level, and this signal The method of the present invention provides a method of supplying a uniform level of power to the stamping motor by adaptively coping with a change in the first power by counting a period of a cycle to determine a pulse of a second signal for power selection.

Hereinafter, the present invention will be described in detail with reference to the drawings.

)의 논리에 따라 트랜지스터(Q1-Q4) 스위칭되어 상기 전원선택부(50 )지 출력으로 스테핑 모터를 구동하는 모터 구동부(60)로 구성된다.5 is a block diagram for carrying out the present invention, which comprises a CPU 10 that generates an interrupt request signal periodically and generates a power control signal by counting the period when an interrupt signal is generated, and resistors R12 and R13. And a voltage detector 20 which receives the first power VH and divides the received first power VH into resistors R12 and R13 to generate a voltage level signal of the first power VH. And a resistor R13, a capacitor C11, and a comparator CM1, which are connected to an output terminal of the voltage detector 20 to compare the level of the received first voltage VH1 with a predetermined reference voltage Vref. A voltage controlled oscillator 30 generating a frequency proportional to the detected value of the first voltage VH, an output and an interrupt request signal of the voltage J oscillator 30 are received, and the received two signals are logically multiplied to receive the interrupt. Outputs the voltage controlled oscillator 30 when a request signal is generated And an AND gate 40 for applying an interrupt signal to the CPU 10 in synchronization with the oscillation frequency, a resistor R6, R7, transistors Q5, Q6, and a diode D5. It is connected to the first power source (VH) and the second power source (VL), according to the logic state of the power control signal received from the CPU 10 transistors (Q5, 06) of the switching element is switched to the first power source ( VH) or the power supply selector 50 for selectively outputting the second power supply VL, the coils L1-L4, diodes D1-D4, ZDI, transistors Q1-Q4, and resistors R8-R11. And receiving the output of the power selector 50 as a power source and receiving the data output terminal of the CPU 10 as a control signal, and outputting the step driving data A, B, which are output from the CPU 10.

The transistor Q1-Q4 is switched in accordance with the logic of FIG. 2 to constitute a motor driver 60 for driving a stepping motor to the output of the power selector 50.

In the above configuration, the power selector 50 and the motor driver 60 perform the same functions as the power selector 2 and the motor driver 3 of FIG. 1, and the same reference numerals are used.

6 is an operational waveform diagram of each part of FIG. 5, where 6A is an interrupt request signal output from the CPU 10, 6B is a waveform diagram of the borrowed frequency output from the voltage controlled oscillator 30, and FIG. 6C is an output of the AND gate 40 which receives and interrupts the interrupt request signal and the oscillation frequency, and 6D is an output of the timer 11 that is embedded in the CPU 10 and used as a counter clock. .

7 is a flow chart of the present invention, the process of enabling the interrupt, the process of reading the contents of the stored timer buffer by performing the interrupt, and the position of the contents of the timer buffer (#TW) and the reference data (#TW) Calculating the pulse width TW of the voltage control signal, and outputting the voltage control signal to select the first power source VH and outputting step driving data.

8 is a flowchart for counting interrupt cycles occurring during the interrupt enable interval, wherein the interrupt cycle is one cycle interval of the voltage controlled oscillator 30.

Based on the above configuration, the present invention will be described in detail with reference to the third, fourth, fifth, sixth, seventh and eighth degrees.

First, in step (b1), the CPU 10 outputs an interrupt request signal having the same "high" logic as the port P1 (6A) to enable the interrupt so that an externally generated interrupt signal can be processed and at the same time the flag FO Reset to prepare for interrupt signal generation. When the CPU 10 outputs a "high" signal to the port P1, an interrupt signal is generated whenever the oscillation frequency of the voltage controlled oscillator 30 transitions from "high" logic to "low" logic. In this case, when the interrupt signal is generated, the CPU 10 interrupts the current command, executes the interrupt service routine, and then returns to the main routine to continue the interrupted command.

At this time, the output frequency of the voltage controlled oscillator 30 is proportional to the magnitude of the first power source VH. That is, the first power source VH received by the voltage detector 20 is divided by the resistors R12 and R13 and applied to the voltage controlled oscillator 30, which is an input voltage of the suppressor controlled oscillator 30. It acts as a voltage level shifter (vo1tage 1eve1 shifter) to match the level. In this case, when the voltage applied to the voltage controlled oscillator 30 is Vvco, the voltage value is determined by the voltage detector 20 as follows.

Vvco = VH * R13 / (R12 + K13)

That is, the voltage detector 20 performs a function of dividing the received first power VH. The first power VH is a 30 Vdc unstabilized power supply when the stepping motor is driven. ) Input voltage shifts the voltage level in case it is less than 10Vdc.

Then, the voltage controlled oscillator 30 receiving the output of the voltage detector 20 performs a function of changing the frequency of the output signal according to the plurality of the received voltage. The voltage controlled oscillator 30 includes a resistor R14 and a capacitor C11 that perform an integration function, and a comparator CM11. In this case, the output voltage of the voltage controlled oscillator 30 is Vo Harman, and when charging, Vo may be expressed as follows.

Vo: Vth (1-e ^{-t / s} .)

Vth = [(R13) f (R12 + H13)] * VH

S = C11 * [R14 + (R12 * R13) / (R12 + R13)]

Therefore, as described above, the time when the voltage applied to the inverting terminal of the comparator CM11 increases during charging of the integrator in the suppression-controlled oscillator 30 is proportional to the received first power source VH, and thus an output frequency signal It can be seen that the Vo is proportional to the first power VH. For example, if the voltage outputting the voltage detector 20 is 5Vdc, when the voltage controlled oscillator 30 oscillates at 50KHz, the voltage oscillates at 60KHz when the voltage is 4Vdc, and at 30KHz when the voltage is 6Vdc. Since the output frequency (period) of the voltage controlled oscillator 30 is proportional (inversely proportional to) the input voltage, when the frequency of this signal is read by the CPU 10, the digital data corresponding to the voltage level of the first power source VH is read. Since the information can be grasped, this data can be processed to provide a constant power when driving the stepping motor.

Therefore, when the output voltage of the first power source VH increases, the output of the voltage controlled oscillator 30 increases, and when the output of the first power source VH decreases, the output of the voltage controlled oscillator 30 decreases. Therefore, the change of the first power source VH changes the output frequency duty (period) of the voltage controlled field oscillator 30, which indicates that the period of the intercept signal is determined by the change of the first power source VH. That is, if the output of the voltage-controlled oscillator 30 is generated as 6B in FIG. 6, the AND gate 40 is controlled by the interrupt enable signal such as 6A by 6C. Whenever the output of the oscillator 30 transitions from "high" to "low" state, an interrupt signal is generated to the CPU 10. Therefore, the generation period of the interrupt signal is determined by the output frequency of the voltage controlled oscillator 30, and the output frequency of the voltage controlled oscillator 30 is determined according to the magnitude of the first power source VH.

When the interrupt signal is generated as described above, the CPV 10 executes the interrupt routine as shown in FIG. 8. First, the accumulator (ACC) and the program status word (Program Status) in order to stop the command being executed in step (C1). Save the Word PSW). In the next step (C2), the state of the flag FO is checked. If the fraud flag PO is in the reset state (F), the timer register is flipped in step (C3), and then in step (C4), the internal timer 11 is turned on. To start counting the cycles of the pre-cancer controlled oscillator 30. Thereafter, in step (C5), the flag FO is set, and in step (C6), the instruction exits the interrupt routine and resumes the interrupted instruction. At this time, since the timer 11 continues to be driven as shown in 6D, it can be seen that the period for the output frequency of the voltage controlled oscillator 30 is being counted.

At this time, if the output of the voltage-controlled oscillator 30 transitions from the "high" state to the "low" state again (6C), the AND gate 40 generates an interrupt signal to the CPU 10, and thus The CPU 10 stops the program being executed in step (C1) and checks the state of the flag FO in step (C2). At this time, since the flag FO is already set in the previous step (C5), the CPU 10 stops driving the timer 11 in the step (C7), and outputs through the port P1 such as (6A) Transmits the interrupt enable signal that was in use to a "low" state to stop subsequent interrupts. After performing step (C7), the flag FO is reset in step (C8). In step (C9), the count data counted so far is stored in a timer buffer and the interrupt routine is terminated.

In the interrupt routine of FIG. 8, the clock of the timer 11 is counted by a value proportional to the level of the received first power supply VH. Therefore, since the count value eventually changes according to the first power source VH, when the first voltage value VH supplied to the voltage controlled oscillator 30 is adjusted through the suppression detector 20, an out-of-oscillation frequency period is generated. It can be seen that the count value can be adjusted at an appropriate line. In other words, if the timer 11 clock is adjusted to 0 o'clock 255 for one cycle other than the voltage controlled oscillator 30, the quantization error becomes ΔVH / 256, and the resolution becomes considerably high. Therefore, the resolution can be made larger by adjusting the output period of the voltage generator.

As described above, a process of generating a power control signal using the contents of a timer register which counts an output frequency period of another voltage controlled oscillator 30 in response to a change in the first power source VH will be described.

First, the CPU 10 closes the count data #C stored in the timer register in step (b2), and stores the fetched count data U in the accumulator (ACC) in step (b3). Thereafter, the CPU 10 converts the frequency, which is the count data #C stored in the accumulator, to data in step (b4) (Frepuecy to Data Conversion). This indicates a frequency component in which the count data #C stored in the timer register counts one cycle signal of the voltage controlled oscillator 30 proportional to the first power source VH, so that the CPU 10 is suitable for internal processing. This is the process of converting data to #N. After the data #N is obtained in step (b4), the difference between the data #N and the period #TW of the power control signal corresponding to the first power source VH in the normal state is calculated in the step (b5). Therefore, when the step (b5) is performed, the TW of the voltage control signal according to the first power source VH is determined. As described above, the period of the TW of the power control signal for supplying uniform power to the stepping motor is set according to the level of the first power source VH.

)의 위상을 결정한 후, (b8)단계에서 P2포트를 전원제어신호 TW른 출력하고, 포트 PA,PB,

를 통해 스텝구동데이타(A, B,

)를 출력한다. 이때 상기 전원제이신호 TW가 “하이”상태일시에는 트랜지스티(Q5-Q6)가 턴온되어 제1전원(VH)이 코일(11-14)에 인가되므로, 스텝구동데이타(A,B,

)의 상태에 따라 트랜지스터(Q1-Q4)가 제어되어 스테핑 모터가 구동된다. 또한 상기 전원제어신호 TW가 “로우”상태 일시에는 상기 트랜지스터(Q5,Q6)이 턴오프 상태이므로 다이오드(D5)를 통해 제2전원(V1)이 코일(11-14)로 인가된다.Afterwards, in step (b7), the CPU 10 performs step driving data A, B, and D for driving the stepping motor.

After determining the phase of), in step (b8), the P2 port is outputted with the power control signal TW, and the ports PA, PB,

Step drive data (A, B,

) At this time, when the power supply J signal TW is in the "high" state, the transistors Q5-Q6 are turned on and the first power source VH is applied to the coils 11-14, so that the step driving data A, B,

The transistors Q1-Q4 are controlled according to the state of) to drive the stepping motor. In addition, since the transistors Q5 and Q6 are turned off when the power control signal TW is in the "low" state, the second power source V1 is applied to the coils 11-14 through the diode D5.

As described above, the stepping motor driving circuit using the double power source can adaptively drive the motor with uniform power even when the first power source having high voltage is changed, thereby making it possible to stabilize the driving of the stepping motor. Corresponding count period according to the change of one power source can be operated variably, quantization error can be reduced, resolution can be improved, and uniform power can be supplied to the stepping motor regardless of the change of external power source. There is an advantage to improve the life and performance of the stepping motor.

Claims (1)

A voltage control transmitter for oscillating a frequency proportional to the first power source, a power supply unit for selecting the first power source or the second power source according to the state of the power control signal, and the output power of the power source selection unit according to the received step driving data. In a stepping motor driving method comprising a motor driving unit for outputting the stepping motor to drive a motor, the step of counting the period of the oscillation frequency when detecting the generation of a sigma oscillation frequency, and detecting the end of the oscillation frequency Stops the count operation, analyzes the count data, calculates a difference between the count data and the reference data in the analysis process, recognizes a change in the first power supply, and detects the change in the first power supply. Setting an output period of the power control signal to supply uniform power to the stepping motor according to the And outputting a signal to the power selection unit and determining the phase of the step driving data and outputting the signal to the motor driving unit to drive the stepping motor with a uniform power regardless of the change of the first power source. Uniform power supply method.

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