JP2947667B2 - Pulse signal output control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse signal output control device, and more particularly to a pulse signal output device which outputs a pulse signal having a constant cycle and a variable duty value, for example, an opening of an engine idle speed control valve or a continuously variable transmission. The present invention relates to a pulse signal output control device for continuously controlling a gear ratio and the like.

[0002]

2. Description of the Related Art Conventionally, in order to output a pulse signal of a constant cycle of this kind, for example, as shown in a timing chart of FIG. The pulse signal rises at the interruption time of the interrupt signal (the ON signal is output from the CPU), and the next fall of the pulse signal thus risen occurs at the time of the above-mentioned rise. The fall time (the output signal off time of the CPU) is set in the timer (compare register) according to the required output value (ie, the required duty value) at that time (for example, when the required output value is 20%). In this case, a time delayed from the rising time by a time corresponding to 20% of the cycle is set). Even if the required output value is 0% at the time of the interruption of the time interrupt signal, it is determined whether or not it is 0% at each interruption (therefore, at the constant period). In this case, the output signal is not output (that is, the pulse signal does not rise) and the output signal is kept off.

Therefore, for example, as shown in FIG. 5, immediately after the interruption time, the requested output value changes from 0% to a value other than 0% (20% in the case shown). However, there is a problem that the ON output is actually started (that is, the pulse signal rises) until the next cycle (that is, the next time interrupt), and a response delay occurs. Was.

According to the above-mentioned prior art, as shown in FIG. 6, while the required output value is a value other than 0% (50% in the illustrated case) (ie, a duty other than 0%). Value control),
As shown in FIG. 6, at the timing of a certain pulse rising (that is, at the time when a time interrupt occurs), when an interrupt process having a higher level than that of itself is being executed, the rising of the pulse (that is, The output of the ON signal from the CPU is possible after the interrupt processing is completed, and the start time of the output of the ON signal is delayed accordingly.

However, if the start time of the output of the ON signal is delayed in this manner, the end time of the output of the ON signal (falling time of the next pulse) is set at the rising time of the delayed pulse as described above. The time set in the compare timer in the CPU (that is, the time delayed from the delayed pulse rising time by the time A corresponding to the product of the cycle and the required output value (for example, 50%)), and therefore, the ON time A has a length corresponding to the requested output value at that time, but if the next rise is executed at a regular time (that is, the next time interrupt is generated without delay due to the above-described interrupt processing). And the off-time (BA) at that time is shortened (that is, shorter than the value obtained by subtracting the time A from the above-mentioned period). Its duty value A / B, there is a problem that occurs an error between a duty value which is required at that time.

As described above, in the prior art, when outputting a pulse signal having a constant cycle and a variable duty value as described above, the rise of the pulse signal
The next fall of the pulse signal is made at the time of the interruption of the time interruption signal generated at predetermined intervals by the timer in the CPU, while the compare timer (compare register) in the CPU described above at the time of the rise. In this case, the response delay is set when the required duty value changes from 0% to any other value as shown in FIG. As shown in FIG. 6, there is a problem that the output duty value shifts due to the delay of the interrupt processing during the period in which the required duty value is a value other than 0%.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problem. In outputting a pulse signal whose duty value is variable at a constant period,
Responsiveness when the required duty value changes from 0% to any other value is improved, and further, the output duty value of the pulse signal during a period when the required duty value is a value other than 0% Irrespective of the presence / absence of interrupt processing or the like from other sources, it is possible to almost fulfill the required value.

[0008]

According to an embodiment of the present invention, there is provided a pulse signal for outputting a pulse signal having a variable duty value based on a time set in a compare register. In the output control device, while the required duty value is a value other than 0%, the pulse signal corresponding to the duty value is determined from the time when the previous rising and falling edges of the pulse signal were detected. A pulse which is characterized by setting a time delayed by an on-time and an off-time of a pulse signal in the compare register, and means for performing the next falling and rising of the pulse signal at the set time. A signal output control device is provided.

According to another aspect of the present invention, there is provided a pulse signal output control device for outputting a pulse signal having a variable duty value based on a time set in a compare register. When the value changes from 0% to another value, an on-time is set in the compare register, means for starting the pulse signal at the set on-time, and a required duty value other than 0% While the value is a value, a time delayed by the ON time and the OFF time of the pulse signal corresponding to the duty value from the time when the previous rising and falling of the pulse signal was detected is stored in the compare register. Setting means for setting the pulse signal to fall and rise at the set time. Pulse signal output control device is provided.

That is, the present invention is characterized in that the rise and fall of the pulse signal are both performed at the time set in a compare timer (compare register) in the CPU. When the required duty value changes from 0% to any other value, the time immediately after the change is detected (necessary to set the ON time in the compare register after the change is detected) (For example, a time several microseconds after the change is detected) is set in the compare register, and at the set time (the elapsed time of the timer in the CPU is compared to the compare register). At the time when the pulse signal coincides with the set time), the pulse signal is turned on (that is, the pulse signal rises).

While the required duty value is a value other than 0%, the next falling time (the falling time is stored in the compare register) when the rising of the pulse signal is detected. A time delayed from the stored rising time by a so-called on-time corresponding to the product of the cycle of the pulse signal and the duty value required at that time) is set in the compare register,
At the set time, the pulse signal is turned off (that is, the next falling is performed). When the falling of the pulse signal is detected, the next rising time (the rising time is calculated from the falling time stored in the compare register and the cycle and the on-time (that is, the cycle and the duty value). Is equivalent to the product of
Is set to the compare register, and the pulse signal is turned on at the set time (that is, the next start-up is performed).

[0012]

According to the above arrangement, when the required duty value changes from 0% to any other value, the on-output of the pulse signal starts based on the time at which the required duty value changes. Therefore, the response at the time of starting (or at the time of restarting) the output can be improved. Further, while the required duty value is a value other than 0%, the pulse signal is referenced with respect to the previous rising or falling time (stored in the compare register in the CPU as described above). Then, the next falling or rising time of the pulse signal is set, and the falling or rising is performed at the set time (that is, the next falling or rising with reference to the previous edge of the pulse signal). Since the start-up is executed), it is possible to output a pulse signal having an accurate duty value without causing a delay in processing due to another interrupt processing as described above.

[0013]

1 and 2 are flowcharts showing one embodiment of a control procedure in a CPU (microcomputer) in a pulse signal output control device according to the present invention.
FIG. 1 shows the main control procedure, and FIG. 2 shows the control procedure when a compare interrupt (interruption that occurs when the elapsed time of the timer coincides with the time set in the compare register) is performed. ing.

First, in FIG. 1, an output demand value is calculated in step 1 (for example, in the case where the opening of an engine idle speed control valve is controlled by the pulse signal, the engine speed, air conditioner signal, neutral The output request value, that is, the required duty value is determined by a signal from the switch, the engine water temperature, and the like. Next, at step 2, it is determined whether the calculated output request value is 0%. If the answer is yes (in the case of 0%), the process proceeds to step 7 where the output port register in the CPU is set to off and at step 8
Immediate mode (mode in which the contents of the output port register are output to the output port simultaneously with the setting, regardless of the compare register) is set inside the PU,
As a result, the output is immediately turned off (the pulse falls).

On the other hand, if the determination in step 2 is no (if the output request value is other than 0%), step 3
It is determined whether the current mode is the timer mode (that is, the mode in which the ON / OFF (pulse rise or fall) is performed at the time set in the compare register). If it is already in the timer mode), the process returns. On the other hand, in the case of know, the process proceeds to step 4 where the CPU
The timer mode is set internally. Next, at step 5, a time several microseconds after the time at that time is set as an on-time in the compare register (that is, the current time is read by a timer in the CPU, and then the on-time is set in the compare register). Is set in the compare register, taking into account the above-mentioned several microseconds as the time required for the operation. In step 6, output on is set in the output port register. Thus, when the elapsed time of the timer matches the ON time set in the compare register, an ON signal is output from the CPU (pulse rises). In this way, with reference to the time at which the change in the output request value from 0% is detected, almost simultaneously with the reference time (actually, several microseconds are expected as the time required for the set as described above). ), The pulse signal rises.

Next, the compare interrupt shown in FIG. 2 is interrupted when the elapsed time of the timer coincides with the time set in the compare register, as described above. It is determined in the CPU whether or not the timer mode is set. If the answer is yes, the process proceeds to step 12 to determine whether the pulse signal has risen or fall this time by turning on / off the output port register. It is determined depending on which is set.

If the answer is yes (if the pulse signal has risen this time), the process proceeds to step 13 where the timer mode setting is confirmed again. The time (falling time) is set. Here, the off-time is based on the current on-time stored in the compare register as a reference, and a time corresponding to the product of the pulse cycle and the duty value requested at that time after the reference time. It is time. In step 15, the output is set to OFF in the output port register. Thus, when the elapsed time of the timer matches the off time set in the compare register, the output signal from the CPU is turned off (pulse falls).

On the other hand, if the determination in step 12 is NO (if the pulse signal has fallen this time), the process proceeds to step 16 and the timer mode is set again again. Sets the next ON time (rise time) in the compare register. Here, the on-time is based on the current off-time stored in the compare register as a reference, and from the reference time, the product of the pulse period and the duty value required at that time from the pulse period. A time corresponding to a value obtained by subtracting the corresponding value is set as a later time. Step 18
Sets the output ON in the output port register. Thus, when the elapsed time of the timer matches the on-time set in the compare register, the CPU
Outputs an ON signal (pulse rises).

FIG. 3 shows an example of the system configuration of the pulse signal output control device according to the present invention. In this case, the opening of the idle speed control valve of the engine is controlled in accordance with the duty value of the pulse signal. It is shown. That is, the CP
The input port side of the input / output (I / O) device 1 inside the U (microcomputer) receives an engine speed, an air conditioner signal, a signal from a neutral switch, an engine water temperature, etc. A required output value (duty value) corresponding to the required opening degree at that time is calculated in the calculating unit (MPU) 2 and an output pulse signal is calculated based on the calculated required output value. The next on or off (rising or falling) time is also calculated, and the calculated next on or off time TM is set in the compare register 4. When the elapsed time of the timer 3 coincides with the time set in the compare register 4, a coincidence signal CD is input to the output port register 5 at which time the output port register is turned on or off. Is set to ON or OFF from the output side of the output port register 5 to the output port side of the I / O device 1, whereby the pulse signal of a predetermined duty value is It is output as an opening signal of a rotation speed control valve (ISC valve).

FIG. 4 is a timing chart showing a control situation in the pulse signal output control device according to the present invention. The time interrupt shown in the figure is for reference, and the relationship with the control according to the present invention is not shown. Absent. When the required output value changes from 0% to a value other than 0% (for example, 20%) as shown in FIG. 1, the timing corresponding to the time set in step 5 in FIG. Therefore, at approximately the same time as described above, the output pulse rises. As described above, the rise of the output pulse is performed when a change in the required output value from 0% is detected, regardless of the time interruption.

Further, while the required output value is a value other than 0% (for example, 20%), the next fall time is determined based on the previous rise time (for example), and the output is made at that time. When the pulse falls, the next rise time is determined based on the fall time, the output pulse rises at that time, and the same control is repeated thereafter.

[0022]

According to the present invention, when the required duty value changes from 0% to any other value, the time from the change point to the actual pulse output can be made very short, and the response time can be reduced. Performance can be improved. Further, the output duty value of the pulse signal while the required duty value is a value other than 0% can be accurately adjusted to almost the required value without being affected by interrupt processing from other sources. Value, and controllability can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing one embodiment of a control procedure in a pulse signal output control device of the present invention.

FIG. 2 is a flowchart showing one embodiment of a control procedure in the pulse signal output control device of the present invention.

FIG. 3 is a diagram illustrating an example of a system configuration of a pulse signal output control device according to the present invention.

FIG. 4 is a timing chart for explaining a control situation in the pulse signal output control device of the present invention.

FIG. 5 is a timing chart for explaining a control situation in a conventional pulse signal output control device.

FIG. 6 is a timing chart for explaining a control situation in a conventional pulse signal output control device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Input / output (I / O) device 2 ... Operation part (MPU) 3 ... Timer 4 ... Compare timer (compare register) 5 ... Output port register

Claims (2)

(57) [Claims] 1. A pulse signal output control device for outputting a pulse signal having a variable duty value based on a time set in a compare register, wherein a required duty value is a value other than 0%. While the pulse signal is set in the compare register at a time delayed from the time at which the previous rise and fall of the pulse signal were detected by the on time and the off time of the pulse signal corresponding to the duty value, respectively. A pulse signal output control device comprising means for causing the pulse signal to fall and rise next at the set time. 2. A pulse signal output control device for outputting a pulse signal whose duty value is variable based on a time set in a compare register, wherein a required duty value is from 0% to any other value. When changed to
Means for setting an on-time in the compare register, and raising the pulse signal at the set on-time;
While the required duty value is a value other than 0%, the on-time of the pulse signal corresponding to the duty value and the on-time of the pulse signal according to the duty value are respectively determined from the time when the previous rise and fall of the pulse signal were detected. A pulse signal output control device, characterized in that the pulse signal output control device is provided with means for setting a time delayed by an off-time in the compare register, and performing the next fall and rise of the pulse signal at the set time.