JPH10224201A - Semiconductor integration circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the reflection of a transmission signal, to accelerate, to dispense with terminating resistance and to miniaturize a printed circuit by providing an input protection circuit that uses an n-channel insulated gate field effect transistor whose drain is connected to an external terminal, whose source is connected to a ground line and whose gate is connected to the positive of power supply voltage. SOLUTION: When power supply is not fed, each of 1 to n of p and n MOS transistors 4 to 6 and 8 to 10 functions as an input protection circuit, which discharges static electricity from an external terminal 1 to a VDD power supply line 7 and a ground line. When power supply is fed, each of 1 to n of the transistors 4 to 6 and 8 to 9 becomes a non-conductive state, and the transistors 10 to n become conductive state and function as a terminating circuit between the terminal 1 and the ground line. With this, the input protection circuit 3 is used as a terminating resistance, prevents the reflection of a transmission signal at the time of an input mode, accelerates signal transmission, and also miniaturizes a printed circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device using an insulated gate field effect transistor constituting an input protection circuit or an insulated gate field effect transistor constituting an output circuit as a terminating resistor.

[0002]

2. Description of the Related Art Conventionally, in a printed circuit board on which a semiconductor integrated circuit device is mounted, it is necessary to match impedance between the semiconductor integrated circuit devices in order to suppress reflection noise for signal wiring requiring high-speed transmission. In general, a method of arranging a terminating resistor on a printed circuit board has been used as a means for realizing the same.

[0003]

However, when a terminating resistor is mounted on a printed circuit board, the mounting area becomes large, the size of the printed circuit board cannot be reduced, the signal wiring becomes long, and the signal delay increases. However, there was a problem that the size became large.

When the terminating resistor is formed in the semiconductor integrated circuit device, these problems can be solved. However, when the terminating resistor is formed independently in the semiconductor integrated circuit device, There is a problem that the size of the semiconductor integrated circuit device is increased.

In view of the above, the present invention can prevent reflection of a transmission signal in the input mode, increase the speed of signal transmission, and increase the size of the printed circuit board without increasing the chip size. It is an object of the present invention to provide a semiconductor integrated circuit device which does not require a terminating resistor and can reduce the size of a printed circuit board.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device having a drain connected to an external terminal, a source connected to a ground line, and a gate connected to a positive terminal. An input protection circuit having an n-channel insulated gate field effect transistor connected to a power supply line for supplying a power supply voltage is provided.

In the first aspect of the present invention, the n
The channel insulated gate field effect transistor functions as an input protection element that discharges static electricity input through an external terminal to a ground line when the power is not turned on, and when the power is turned on. , Becomes conductive,
It functions as a terminating resistor whose resistance value is the on-resistance value.

In a second aspect of the present invention (a semiconductor integrated circuit device according to claim 2), the drain is connected to an external terminal,
An input protection circuit having a p-channel insulated gate field effect transistor having a source connected to a power supply line supplying a positive power supply voltage and a gate connected to a ground line is provided.

In the second aspect of the present invention, the p
The channel insulated gate field effect transistor functions as an input protection element that discharges static electricity input through an external terminal to a power supply line when power is not turned on, and when the power is turned on. , Becomes conductive,
It functions as a terminating resistor whose resistance value is the on-resistance value.

[0010] In a third aspect of the present invention (a semiconductor integrated circuit device according to claim 3), the drain is connected to an external terminal,
An n-channel insulated gate field effect transistor having a source connected to a ground line, a gate connected to a power supply line supplying a positive power supply voltage, a drain connected to the external terminal, and a source connected to the power supply line. , An input protection circuit having a p-channel insulated gate field effect transistor having a gate connected to a ground line.

In a third aspect of the present invention, the above n
The channel insulated gate field effect transistor functions as an input protection element that discharges static electricity input through an external terminal to a ground line when the power is not turned on, and when the power is turned on. , Becomes conductive,
It functions as a terminating resistor whose resistance value is the on-resistance value.

Further, the p-channel insulated gate field effect transistor, when the power is not turned on,
It functions as an input protection element that discharges static electricity input through an external terminal to a power supply line. When power is turned on, it becomes conductive and functions as a terminating resistor whose resistance value is an on-resistance value.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device according to the third aspect, wherein the current path formed by the n-channel insulated gate field effect transistor and the p-channel insulated gate are formed. A current path disconnection circuit is provided which can selectively disconnect a current path formed by the field effect transistor.

In the fourth aspect of the present invention, as in the third aspect, the n-channel insulated gate field effect transistor and the p-channel insulated gate field effect transistor can be used as termination resistors. In addition, a test can be performed in a state where the n-channel insulated gate field-effect transistor and the p-channel insulated gate field-effect transistor do not function as a terminating resistor.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit device according to the fifth aspect, the current path formed by the n-channel insulated gate type field effect transistor or the p-channel insulated gate is provided. And a current path disconnecting circuit that can selectively disconnect any one of the current paths formed by the field effect transistor.

In the fifth aspect of the present invention, as in the third aspect, the n-channel insulated gate field effect transistor and the p-channel insulated gate field effect transistor can be used as termination resistors. In addition, only one of the n-channel insulated-gate field-effect transistor and the p-channel insulated-gate field-effect transistor can be made to function as a termination resistor by selection.

In a sixth aspect of the present invention (a semiconductor integrated circuit device according to a sixth aspect), one or more of the semiconductor integrated circuit devices have a drain connected to an external terminal for signal input / output and a source connected to a ground line. an open-drain output circuit comprising an n-channel insulated gate field effect transistor;
An output control circuit capable of fixing one or more of the one or more n-channel insulated gate field effect transistors in a conductive state.

According to a sixth aspect of the present invention, in the input mode, when one or more of the one or more n-channel insulated gate field effect transistors is fixed in a conductive state, One or more of the n-channel insulated gate field effect transistors can function as a terminating resistor.

According to a seventh aspect of the present invention, in the semiconductor integrated circuit device, the drain is connected to an external terminal for signal input / output, and the source is connected to a power supply line for supplying a positive power supply voltage. An open-drain output circuit having one or more p-channel insulated gate field effect transistors, and one or more of the one or more p-channel insulated gate field effect transistors in a conductive state in an input mode. And an output control circuit that can be fixed.

According to a seventh aspect of the present invention, in the input mode, when one or more of the one or more p-channel insulated gate field effect transistors is fixed to a conductive state, One or more of the p-channel insulated gate field effect transistors can function as a terminating resistor.

According to an eighth aspect of the present invention, in the semiconductor integrated circuit device according to the eighth aspect of the present invention, one or more of the semiconductor integrated circuit devices have a drain connected to a signal input / output external terminal and a source connected to a ground line. an n-channel insulated gate field effect transistor;
A push-pull output circuit including one or more p-channel insulated gate field effect transistors having a drain connected to the external terminal and a source connected to a power supply line for supplying a positive power supply voltage; and an input mode. An output control circuit that can fix one or more of the one or more n-channel insulated gate field effect transistors and one or more of the one or more p-channel insulated gate field effect transistors in a conductive state; It is to have.

According to an eighth aspect of the present invention, in the input mode, one or more of the one or more n-channel insulated gate field effect transistors and one or more of the one or more
When one or more of the channel insulated gate field effect transistors are fixed in a conductive state, the one or more n
One or more of the channel insulated gate field effect transistors and one or more of the one or more p-channel insulated gate field effect transistors can function as a termination resistor.

According to a ninth aspect of the present invention, in the semiconductor integrated circuit device according to the ninth aspect, in the eighth aspect, the output control circuit may be configured such that the one or more n-channel insulating devices are optionally selected in an input mode. One or more of the gate field effect transistors or one or more of the one or more p-channel insulated gate field effect transistors can be fixed in a conductive state.

According to a ninth aspect of the present invention, in the ninth aspect, as in the eighth aspect, the one or more n-channel insulated gate field effect transistors and the one or more p-channel insulated gate field effect transistors are provided. Any one or more of the one or more n-channel insulated gate field effect transistors or one or more of the one or more p-channel insulated gate field effect transistors can be used as a terminating resistor and optionally selected. Alone can function as a terminating resistor.

According to a tenth aspect of the present invention, in the semiconductor integrated circuit device according to the tenth aspect, the plurality of n-channel insulated gate field effect transistors and the plurality of p-channel insulated gate type are provided. In the output mode, the field effect transistor functions as an output transistor whose output impedance is 1 / 1.6 to 1 / 2.0 times the characteristic impedance of the external signal line connected to the external terminal. In some cases, it is sized to function as a terminating resistor whose resistance value is 1.6 to 2.0 times the characteristic impedance of the external signal line.

In the tenth aspect of the present invention, the eighth aspect comprises the eighth aspect.
In the same manner as the invention, the one or more n-channel insulated gate field effect transistors and the one or more p-channel insulated gate field effect transistors can be used as a termination resistor, and the voltage gain and the S / N ratio can be reduced. Good signal transmission can be performed.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
The first to eighth embodiments of the present invention will be described.

First Embodiment FIG. 1 FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention. In FIG. 1, 1 is an external terminal for an input signal connected to an external signal line, 2 is an input signal line for transmitting an input signal input via the external terminal 1 to an internal circuit, and 3 is an external signal line when power is not turned on. This is an input protection circuit for protecting the internal circuit from static electricity input via the terminal 1.

In the input protection circuit 3, 4-1 and 4-
2,4-n, 5-1,5-2,5-n, 6-1,6-
2, 6-n are pMOS transistors, and pMOS transistors 4-3, 4-4,..., 4- (n-1), 5
-3, 5-4, ..., 5- (n-1), 6-3, 6
4,..., 6- (n−1) are not shown.

These pMOS transistors 4-1 to 4-
n, 5-1 to 5-n, 6-1 to 6-n have drains connected to the input signal line 2 and supply a positive power supply voltage VDD (for example, 3.3 [V]) to the gate and source. Connected to the VDD power supply line 7.

8-1, 8-2,..., 8-n, 9
-1, 9-2, ..., 9-n, 10-1, 10-2, ...
..10-n is an nMOS transistor and nMOS
Transistors 8-3, 8-4, ..., 8- (n-1),
9-3, 9-4, ..., 9- (n-1), 10-3, 1
The illustrations of 0-4,..., 10- (n-1) are omitted.

Here, nMOS transistors 8-1 to 8-8
-N, 9-1 to 9-n have their drains connected to the input signal line 2 and their gates and sources connected to a ground line set to a ground voltage of 0 [V].

On the other hand, the nMOS transistor 10
In -1 to 10-n, the drain is connected to the input signal line 2, the gate is connected to the VDD power supply line 7, and the source is connected to the ground line.

In the first embodiment configured as described above, when the power is not turned on, the pMOS transistors 4-1 to 4-n, 5-1 to 5-n, 6-1 to 6
−n is the voltage applied to the static electricity input through the external terminal 1 to VDD.
It functions as an input protection element for discharging to the power supply line 7 and has nM
OS transistors 8-1 to 8-n, 9-1 to 9-n, 1
0-1 to 10-n function as input protection elements for discharging static electricity input through the external terminal 1 to the ground line.

On the other hand, when the power is turned on, the pMOS transistors 4-1 to 4-n, 5-1 to
5-n, 6-1 to 6-n and nMOS transistor 8-
1 to 8-n, 9-1 to 9-n are in an OFF (non-conducting) state,
The nMOS transistors 10-1 to 10-n are turned on (conductive).

Therefore, when the power is turned on, the nMOS transistors 10-1 to 10-n are connected between the external terminal 1 and the ground line and have a terminating resistance having an on-resistance as a resistance. Function as

As described above, according to the first embodiment of the present invention, the nMOS transistor 1 forming the input protection circuit 3
Since 0-1 to 10-n can be used as a terminating resistor, reflection of transmission signals can be prevented in the input mode, signal transmission can be speeded up, and chip size increases. In addition, the need for a terminating resistor on the printed circuit board is eliminated, and the size of the printed circuit board can be reduced.

In the first embodiment of the present invention,
Although the case where the nMOS transistors 10-1 to 10-n are used as the terminating resistors has been described, the nMOS transistors 9-1 to 9-n or the nMOS transistors
The transistors 8-1 to 8-n and 9-1 to 9-n may be used as a terminating resistor.

In the first embodiment of the present invention,
PMOS transistors 4-1 to 4-4 as input protection elements
-N, 5-1 to 5-n, and 6-1 to 6-n are described. However, these pMOS transistors 4-1 to 4-n, 5-1 to 5-n, and 6-n are provided. 1-6-n
May not be provided.

Second Embodiment FIG. 2 is a circuit diagram showing a main part of a second embodiment of the present invention. In FIG. 2, reference numeral 11 denotes an external terminal for an input signal connected to an external signal line, 12 denotes an input signal line for transmitting an input signal input via the external terminal 11 to an internal circuit, and 13 denotes an external signal when power is not turned on. This is an input protection circuit for protecting the internal circuit from static electricity input via the terminal 11.

In the input protection circuit 13, 14-
1, 14-2, 14-n, 15-1, 15-2, 15-
n, 16-1, 16-2, 16-n are pMOS transistors, and pMOS transistors 14-3, 14-n
4,..., 14- (n−1), 15-3, 15-4,.
..15- (n-1), 16-3, 16-4,... 1
6- (n-1) is not shown.

Here, the pMOS transistors 14-1 to 14-1
14-n and 15-1 to 15-n each have a drain connected to the input signal line 12, and a gate and a source connected to the positive power supply voltage V.
It is connected to a VDD power supply line 17 that supplies DD (for example, 3.3 [V]).

On the other hand, the pMOS transistor 16
In -1 to 16-n, the drain is connected to the input signal line 12, the gate is connected to the ground line, and the source is connected to the VDD power supply line 17.

Also, 18-1, 18-2,..., 18-
n, 19-1, 19-2, ..., 19-n, 20-1,
20-n are nMOS transistors, and nMOS transistors 18-3, 18-4,.
18- (n-1), 19-3, 19-4, ... 19-
(N-1), 20-3, 20-4, ... 20- (n-
1) is not shown.

These nMOS transistors 18-1 to 18-1
8-n, 19-1 to 19-n, 20-1 to 20-n are
The drain is connected to the input signal line 12, and the gate and source are connected to the ground line.

In the second embodiment thus configured, when the power is not turned on, the pMOS transistors 14-1 to 14-n, 15-1 to 15-n, 1
6-1 to 16-n function as input protection elements for discharging static electricity input through the external terminal 11 to the VDD power supply line 17, and the nMOS transistors 18-1 to 18-n.
n, 19-1 to 19-n and 20-1 to 20-n function as input protection elements for discharging static electricity input via the external terminal 11 to the ground line.

On the other hand, when the power is on, the pMOS transistors 14-1 to 14-n, 15
-1 to 15-n and nMOS transistors 18-1 to 18-1
8-n, 19-1 to 19-n and 20-1 to 20-n are O
In the FF state, the pMOS transistors 16-1 to 16-n are in the ON state.

Therefore, when the power is turned on, the pMOS transistors 16-1 to 16 -n have the on-resistance which is connected between the external terminal 11 and the VDD power supply line 17. Functions as a terminating resistor.

As described above, according to the second embodiment of the present invention, the pMOS transistors 16-1 to 16-n constituting the input protection circuit 13 can be used as the terminating resistors. Signal reflection can be prevented, signal transmission can be speeded up, and a terminal resistor on the printed board is not required without increasing the chip size, and the printed board can be downsized.

Note that in the second embodiment of the present invention,
Although the case where the pMOS transistors 16-1 to 16-n are used as the terminating resistors has been described, the pMOS transistors 15-1 to 15-n or pM
OS transistors 14-1 to 14-n, 15-1 to 15
-N may be used as a terminating resistor.

In the second embodiment of the present invention,
As input protection elements, nMOS transistors 18-1 to 18-1
18-n, 19-1 to 19-n, and 20-1 to 20-n are described.
OS transistors 18-1 to 18-n, 19-1 to 19
-N and 20-1 to 20-n may not be provided.

Third Embodiment FIG. 3 FIG. 3 is a circuit diagram showing a main part of a third embodiment of the present invention. In FIG. 3, reference numeral 21 denotes an external terminal for an input signal connected to an external signal line, 22 denotes an input signal line for transmitting an input signal input via the external terminal 21 to an internal circuit, and 23 denotes an external signal when the power is not turned on. This is an input protection circuit for protecting the internal circuit from static electricity input via the terminal 21.

In the input protection circuit 23, 24
1, 24-2, 24-n, 25-1, 25-2, 25-
n, 26-1, 26-2, 26-n are pMOS transistors, and pMOS transistors 24-3, 24-
4,..., 24- (n-1), 25-3, 25-4,.
..25- (n-1), 26-3, 26-4,... 2
6- (n-1) is not shown.

Here, the pMOS transistors 24-1 to 24-1
In 24-n and 25-1 to 25-n, the drain is connected to the input signal line 22, and the gate and source are connected to the positive power supply voltage V.
It is connected to a VDD power supply line 27 that supplies DD (for example, 3.3 [V]).

On the other hand, the pMOS transistor 26
-1 to 26-n have a drain connected to the input signal line 22, a gate connected to the ground line, and a source connected to the VDD power supply line 27.

Also, 28-1, 28-2,..., 28-
n, 29-1, 29-2, ..., 29-n, 30-1,
30-n are nMOS transistors, and nMOS transistors 28-3, 28-4,.
28- (n-1), 29-3, 29-4, ... 29-
(N-1), 30-3, 30-4, ..., 30- (n-
1) is not shown.

Here, the nMOS transistors 28-1 to 28-1
28-n and 29-1 to 29-n have their drains connected to the input signal line 22, and their gates and sources connected to the ground line.

On the other hand, the nMOS transistor 30
In -1 to 30-n, the drain is connected to the input signal line 22, the gate is connected to the VDD power supply line 27, and the source is connected to the ground line.

In the third embodiment thus configured, when the power is not turned on, the pMOS transistors 24-1 to 24-n, 25-1 to 25-n,
6-1 to 26-n function as input protection elements for discharging the static electricity input via the external terminal 21 to the VDD power supply line 27, and the nMOS transistors 28-1 to 28-n
n, 29-1 to 29-n and 30-1 to 30-n function as input protection elements for discharging static electricity input via the external terminal 21 to the ground line.

On the other hand, when the power is turned on, the pMOS transistors 24-1 to 24-n, 25
-1 to 25-n and nMOS transistors 28-1 to 28-2
8-n, 29-1 to 29-n are OFF, and pMOS transistors 26-1 to 26-n and nMOS transistors 30-1 to 30-n are ON.

Therefore, when the power is turned on, the pMOS transistors 26-1 to 26 -n have the on-resistance which is connected between the external terminal 21 and the VDD power supply line 27. Function as a terminating resistor, nMOS
Each of the transistors 30-1 to 30-n functions as a terminating resistor connected between the external terminal 21 and the ground line and having a resistance value of an on-resistance value.

As described above, according to the third embodiment of the present invention, the pMOS transistors 26-1 to 26-n and the nMOS transistor 30-1 constituting the input protection circuit 23 are provided.
30-n can be used as a terminating resistor, so that reflection of transmission signals can be prevented in the input mode, signal transmission can be speeded up, and printing can be performed without increasing the chip size. This eliminates the need for a terminating resistor on the substrate, and makes it possible to reduce the size of the printed circuit board.

In the third embodiment of the present invention,
pMOS transistors 26-1 to 26-n and nMOS
The case where the transistors 30-1 to 30-n are used as the terminating resistors has been described.
S transistors 25-1 to 25-n and nMOS transistors 29-1 to 29-n, or pMOS transistors 24-1 to 24-n, 25-1 to 25-n and n
MOS transistors 28-1 to 28-n, 29-1 to 2
9-n may be used as a terminating resistor.

Also, in the input mode, the current path formed by the pMOS transistors 26-1 to 26-n and nMO
In the case where a current path disconnection circuit capable of selectively disconnecting the current path formed by the S transistors 30-1 to 30-n is provided, the pMOS transistor 26-
It is possible to perform a test in a state where the current paths formed by 1 to 26-n and the nMOS transistors 30-1 to 30-n do not function as a terminating resistor.

In the input mode, the current path or nMO formed by pMOS transistors 26-1 to 26-n is
When a current path disconnection circuit capable of selectively disconnecting any of the current paths formed by S transistors 30-1 to 30-n is provided, pM
Only one of the OS transistors 26-1 to 26-n or the nMOS transistors 30-1 to 30-n can function as a terminating resistor.

Fourth Embodiment FIG. 4 FIG. 4 is a circuit diagram showing a main part of a fourth embodiment of the present invention. 4, reference numeral 33 denotes an external terminal for signal input / output connected to the external signal line, and reference numeral 34 denotes an open drain type output circuit for outputting an output signal to the external terminal 33.

In the output circuit 34, 35 is an nMOS transistor having an on-resistance value of 67 [Ω], and 36 is an nMOS transistor having an on-resistance value of 200 [Ω]. These nMOS transistors 35 and 36 have drains. The source is connected to the external terminal 33, and the source is connected to the ground line.

Reference numeral 37 denotes an output control circuit for controlling ON / OFF of the nMOS transistors 35 and 36 based on output control signals SA, SB and SC output from the internal circuits. Reference numeral 38 denotes output control signals SA and SB. , SC NOR
This is a NOR circuit that processes and controls ON / OFF of the nMOS transistor 35.

An inverter 39 inverts the output control signal SB, an OR circuit 40 performs an OR operation on the output of the inverter 39 and the output control signal SA, and a reference numeral 41 denotes an OR circuit 40.
Of the output and output control signal SC by NAND processing
NAND for controlling ON and OFF of the S transistor 36
Circuit.

Table 1 shows the logical values of the output control signals SA, SB, and SC, and the ON and OFF states of the nMOS transistors 35 and 36.
It shows a part of the relationship with the F state.

[0071]

[Table 1]

That is, when the output control signal SA = "0" (low potential), SB = "0" and SC = "0", NOR
Output of circuit 38 = “1” (high potential), nMOS transistor 35 = ON, output of NAND circuit 41 = “1”, n
The MOS transistor 36 is turned on.

Further, output control signal SA = "0", SB =
When "1" and SC = "0", the output of the NOR circuit 38 is "0", the nMOS transistor 35 is OFF, and the NA
Output of ND circuit 41 = "1", nMOS transistor 3
6 = ON.

The output control signal SA = "0", SB =
When “0” and SC = “1”, the output of the NOR circuit 38 = “0”, the nMOS transistor 35 = OFF, the output of the inverter 39 = “1”, the output of the OR circuit 40 =
"1", the output of the NAND circuit 41 = "0", and the nMOS transistor 36 is turned off.

Therefore, in the output mode, when the output control signals SA = "0", SB = "0" and SC = "0", the nMOS transistor 35 = ON and the nMOS transistor 36 = ON, and the output signal Can be output as "0".

In this case, the output impedance of the output circuit 34 is 1 / (1 / ON resistance of nMOS transistor 35 + 1 / ON resistance of nMOS transistor 36) =
1 / (1/67 + 1/200) = 50 [Ω].

In the output mode, for example, when the output control signals SA = "0", SB = "1", and SC = "0", the nMOS transistor 35 = OFF and the nMOS
The transistor 36 is turned on, and in this case also, "0" can be output as an output signal.

In this case, the output impedance of the output circuit 34 is the ON resistance value of the nMOS transistor 36 = 20.
0 [Ω].

In the output mode, for example, when the output control signals SA = "0", SB = "0" and SC = "1", the nMOS transistor 35 = OFF and the nMOS
Transistor 36 = OFF, output signal "1"
Can be output.

On the other hand, in the input mode, when the output control signals SA are fixed at "0", SB = "0", and SC = "0", the nMOS transistor 35 is turned on and the nMO
By fixing the S transistor 36 to ON, the nMOS transistors 35 and 36 can function as a terminating resistor connected between the external terminal 33 and the ground line.

In this case, the terminating resistance value is 1 / (1 / nM
ON resistance value of OS transistor 35 + 1 / ON resistance value of nMOS transistor 36) = 1 / (1/67 + 1/2)
00) = 50 [Ω].

In the input mode, for example, when the output control signals SA are fixed at “0”, SB is set at “1”, and SC is set at “0”, the nMOS transistor 35 is turned off and nM
When the OS transistor 36 is fixed to ON, the nMOS transistor 36 can function as a terminating resistor connected between the external terminal 33 and the ground line. In this case, the terminating resistance is the on-resistance value of the nMOS transistor 36. = 2
00 [Ω].

In the input mode, for example, when the output control signal SA is fixed at "0", SB = "0", and SC = "1", the nMOS transistor 35 = OFF, nM
The OS transistor 36 can be fixed at OFF and the nMOS transistors 35 and 36 can be prevented from functioning as a terminating resistor.

As described above, according to the fourth embodiment of the present invention, the nMOS transistor 3
Since 5 and 36 can be used as termination resistors,
In the input mode, reflection of transmission signals can be prevented, signal transmission can be speeded up, and terminal resistors on the printed circuit board are not required without increasing the chip size. Can be planned.

Fifth Embodiment FIG. 5 FIG. 5 is a circuit diagram showing a main part of a fifth embodiment of the present invention. In FIG. 5, reference numeral 44 denotes an external terminal for signal input / output connected to an external signal line, and reference numeral 45 denotes an open drain type output circuit for outputting an output signal to the external terminal 44.

In the output circuit 45, reference numeral 46 denotes an nMOS transistor having an on-resistance of 67 [Ω]; 47, an nMOS transistor having an on-resistance of 267 [Ω];
Reference numeral 8 denotes an nMOS transistor having an on-resistance of 800 [Ω].
Reference numeral 48 has a drain connected to the external terminal 44 and a source connected to the ground line.

Reference numeral 49 denotes nM based on output control signals SA, SB, SC, SD, SE output from the internal circuit.
An output control circuit for controlling ON and OFF of the OS transistors 46, 47, and 48, and 50 is an output control signal SA,
SB and SC are NOR-processed and the nMOS transistor 46
Is a NOR circuit for controlling ON and OFF of the control signal.

Reference numeral 51 denotes an inverter for inverting the output control signal SB, and reference numeral 52 denotes an OR circuit for ORing the output of the inverter 51 and the output control signal SA.

Reference numeral 53 denotes output control signals SC, SD and O
A NAND circuit for performing NAND processing on the output of the R circuit 52 to control ON / OFF of the nMOS transistor 47;
4 performs NAND processing on the output control signals SC and SE and the output of the OR circuit 52 to turn on and off the nMOS transistor 48.
This is a NAND circuit that controls the FF.

Table 2 shows output control signals SA, SB, SC,
Logic values of SD and SE and nMOS transistors 46 and 4
7 shows a part of the relationship between ON and OFF states of 7 and 48.

[0091]

[Table 2]

That is, the output control signal SA = "0", SB =
When "0", SC = "0", SD = "0", SE = "0", output of NOR circuit 50 = "1", nMOS transistor 46 = ON, output of NAND circuit 53 =
“1”, nMOS transistor 47 = ON, output of NAND circuit 54 = “1”, nMOS transistor 48 = O
N.

Further, output control signal SA = "0", SB =
When "1", SC = "0", SD = "0", SE = "0", the output of the NOR circuit 50 = "0", the nMOS transistor 46 = OFF, and the output of the NAND circuit 53 =
“1”, nMOS transistor 47 = ON, output of NAND circuit 54 = “1”, nMOS transistor 48 = O
N.

Further, output control signal SA = "0", SB =
When “0”, SC = “1”, SD = “0”, SE = “1”, the output of the NOR circuit 50 = “0”, the nMOS transistor 46 = OFF, and the output of the NAND circuit 53 =
“1”, nMOS transistor 47 = ON, output of inverter 51 = “1”, output of OR circuit 52 = “1”, N
The output of the AND circuit 54 = "0", and the nMOS transistor 48 is turned off.

Further, output control signal SA = "0", SB =
When "0", SC = "1", SD = "1", SE = "0", the output of the NOR circuit 50 = "0", the nMOS transistor 46 = OFF, and the output of the inverter 51 =
“1”, output of OR circuit 52 = “1”, NAND circuit 5
3 output = “0”, nMOS transistor 47 = OF
F, the output of the NAND circuit 54 is "1", and the nMOS transistor 48 is turned on.

Further, the output control signal SA = "0", SB =
When "0", SC = "1", SD = "1", SE = "1", the output of the NOR circuit 50 = "0", the nMOS transistor 46 = OFF, and the output of the inverter 51 =
“1”, output of OR circuit 52 = “1”, NAND circuit 5
3 output = “0”, nMOS transistor 47 = OF
F, the output of the NAND circuit 54 is "0", and the nMOS transistor 48 is turned off.

Therefore, in the output mode, the output control signals SA = "0", SB = "0", SC = "0", SD = "
When "0" and SE = "0", the nMOS transistor 46 = ON, the nMOS transistor 47 = ON,
When the nMOS transistor 48 is turned on, “0” can be output as an output signal.

In this case, the output impedance of the output circuit 45 is 1 / (1 / the ON resistance of the nMOS transistor 46 + 1 / the ON resistance of the nMOS transistor 47 + 1
/ On resistance value of nMOS transistor 48) = 1 / (1
/ 67 + 1/267 + 1/800) = 50 [Ω].

In the output mode, the output control signal SA =
"0", SB = "1", SC = "0", SD = "0",
When SE = "0", the nMOS transistor 4
6 = OFF, nMOS transistor 47 = ON, nMO
The S transistor 48 is turned on, and in this case also, "0" can be output as an output signal.

In this case, the output impedance of the output circuit 45 is 1 / (1 / ON resistance of nMOS transistor 47 + 1 / ON resistance of nMOS transistor 48) =
1 / (1/267 + 1/800) = 200 [Ω].

In the output mode, the output control signal SA =
"0", SB = "0", SC = "1", SD = "0",
When SE = "1", the nMOS transistor 4
6 = OFF, nMOS transistor 47 = ON, nMO
The S transistor 48 is turned off, and in this case also, “0” can be output as an output signal.

In this case, the output impedance of the output circuit 45 is the ON resistance value of the nMOS transistor 47 = 26.
7 [Ω].

In the output mode, the output control signal SA =
“0”, SB = “0”, SC = “1”, SD = “1”,
When SE = "0", the nMOS transistor 4
6 = OFF, nMOS transistor 47 = OFF, nM
The OS transistor 48 is turned on, and in this case also, “0” can be output as an output signal.

In this case, the output impedance of the output circuit 45 is the ON resistance value of the nMOS transistor 48 = 80.
0 [Ω].

In the output mode, the output control signal SA =
“0”, SB = “0”, SC = “1”, SD = “1”,
When SE = "1", the nMOS transistor 4
6 = OFF, nMOS transistor 47 = OFF, nM
The OS transistor 48 is turned off, and "1" can be output as an output signal.

On the other hand, in the input mode, the output control signals SA = "0", SB = "0", SC = "0", SD = "
To fix "0" and SE = "0", the nMOS transistor 46 = ON and the nMOS transistor 47 = O
N, nMOS transistor 48 is fixed at ON, and nMO
The S transistors 46, 47, and 48 can function as termination resistors connected between the external terminal 44 and the ground line.

In this case, the terminating resistance value is 1 / (1 / nM
ON resistance value of OS transistor 46 + ON resistance value of nMOS transistor 47 + ON resistance value of nMOS transistor 48) = 1 / (1/67 + 1/267 + 1)
/ 800) = 50 [Ω].

In the input mode, the output control signal SA =
"0", SB = "1", SC = "0", SD = "0",
When SE is fixed at “0”, the nMOS transistor 46 is OFF, the nMOS transistor 47 is ON, and n
When the MOS transistor 48 is fixed to ON, the nMOS transistors 47 and 48 can function as a terminating resistor connected between the external terminal 44 and the ground line.

In this case, the terminating resistance value is 1 / (1 / nM
ON resistance value of OS transistor 47 + 1 / ON resistance value of nMOS transistor 48) = 1 / (1/267 + 1 /
800) = 200 [Ω].

In the input mode, the output control signal SA =
"0", SB = "0", SC = "1", SD = "0",
When SE is fixed to “1”, the nMOS transistor 46 is OFF, the nMOS transistor 47 is ON, and n
When the MOS transistor 48 is fixed at OFF, the nMOS transistor 47 can function as a terminating resistor connected between the external terminal 44 and the ground line. In this case,
The termination resistance value is the ON resistance value of the nMOS transistor 47 = 267 [Ω].

In the input mode, the output control signal SA =
“0”, SB = “0”, SC = “1”, SD = “1”,
When SE is fixed to “0”, the nMOS transistor 46 is turned off, the nMOS transistor 47 is turned off,
By fixing the nMOS transistor 48 to ON, the nMOS transistor 48 can function as a terminating resistor connected between the external terminal 44 and the ground line. In this case,
The terminating resistance value is the ON resistance value of the nMOS transistor 48 = 800 [Ω].

In the input mode, the output control signal SA =
“0”, SB = “0”, SC = “1”, SD = “1”,
When SE is fixed at “1”, the nMOS transistor 46 is turned off, the nMOS transistor 47 is turned off,
nMOS transistor 48 is fixed at OFF, and nMOS
The transistors 46, 47, and 48 can be prevented from functioning as termination resistors.

As described above, according to the fifth embodiment of the present invention, the nMOS transistor 4 forming the output circuit 45
Since 6, 47 and 48 can be used as terminating resistors, reflection of transmission signals can be prevented in the input mode, signal transmission can be speeded up, and the chip size does not increase. This eliminates the need for a terminating resistor on the printed board, and allows the printed board to be downsized.

Sixth Embodiment FIG. 6 FIG. 6 is a circuit diagram showing a main part of a sixth embodiment of the present invention. 6, reference numeral 57 denotes an external terminal for signal input / output connected to the external signal line, and 58 denotes an open drain type output circuit for outputting an output signal to the external terminal 57.

In the output circuit 58, 59 is a pMOS transistor having an on-resistance of 67 [Ω], and 60 is a pMOS transistor having an on-resistance of 200 [Ω]. These pMOS transistors 59 and 60 have drains. Connected to the external terminal 57, the source is the VDD power line 6
1 connected.

An output control circuit 62 controls ON / OFF of the pMOS transistors 59 and 60 based on output control signals SA, SB and SC output from internal circuits.

In the output control circuit 62, 63 is an inverter for inverting the output control signal SA, 64 is an inverter for inverting the output control signal SB, and 65 is inverters 63 and 6
4 and the output control signal SC are NAND-processed to obtain pM
NAN that controls ON and OFF of the OS transistor 59
This is a D circuit.

An AND circuit 66 performs an AND operation on the output of the inverter 63 and the output control signal SB.
This is a NOR circuit that controls the ON / OFF of the pMOS transistor 60 by performing NOR processing on the output of the ND circuit 66 and the output control signal SC.

Table 3 shows the logical values of the output control signals SA, SB, and SC, and the ON and OFF states of the pMOS transistors 59 and 60.
It shows a part of the relationship with the F state.

[0120]

[Table 3]

That is, the output control signal SA = "0", SB =
When “0” and SC = “1”, the output of the inverter 63 = “1”, the output of the inverter 64 = “1”, and the NAND
Output of circuit 65 = "0", pMOS transistor 59 =
ON, output of NOR circuit 67 = "0", pMOS transistor 60 = ON.

Further, output control signal SA = "0", SB =
When “1” and SC = “0”, the output of the NAND circuit 65 = “1”, the pMOS transistor 59 = OFF, the output of the inverter 63 = “1”, the output of the AND circuit 66 =
"1", the output of the NOR circuit 67 = "0", and the pMOS transistor 60 is turned on.

The output control signal SA = "0" and SB =
When “0” and SC = “0”, the output of the NAND circuit 65 = “1”, the pMOS transistor 59 = OFF, A
Output of ND circuit 66 = “0”, output of NOR circuit 67 =
“1”, pMOS transistor 60 = OFF.

Therefore, in the output mode, when the output control signals SA = "0", SB = "0", and SC = "1", the pMOS transistor 59 = ON, the pMOS transistor 60 = ON, and the output signal As "1".

In this case, the output impedance of output circuit 58 is 1 / (1 / ON resistance of pMOS transistor 59 + 1 / ON resistance of pMOS transistor 60) =
1 / (1/67 + 1/200) = 50 [Ω].

In the output mode, the output control signal SA =
When “0”, SB = “1”, and SC = “0”,
The pMOS transistor 59 is turned off and the pMOS transistor 60 is turned on. In this case, “1” can be output as an output signal.

In this case, the output impedance of the output circuit 58 is the ON resistance value of the pMOS transistor 60 = 20.
0 [Ω].

In the output mode, the output control signal SA =
When “0”, SB = “0”, and SC = “0”,
With the pMOS transistor 59 = OFF and the pMOS transistor 60 = OFF, “0” can be output as an output signal.

On the other hand, in the input mode, when the output control signal SA is fixed at "0", SB = "0", and SC = "1", the pMOS transistor 59 is turned on and the pMO
By fixing the S transistor 60 = ON, the pMOS transistors 59 and 60 can function as a terminating resistor connected between the external terminal 57 and the VDD power supply line 61.

In this case, the terminating resistance value is 1 / (1 / pM
ON resistance value of OS transistor 59 + 1 / ON resistance value of pMOS transistor 60) = 1 / (1/67 + 1/2)
00) = 50 [Ω].

In the input mode, the output control signal SA =
When fixing to “0”, SB = “1” and SC = “0”, the pMOS transistor 59 is fixed to OFF and the pMOS transistor 60 is fixed to ON, and the pMOS transistor 6 is fixed.
0 can function as a terminating resistor connected between the external terminal 57 and the VDD power supply line 61. In this case, the terminating resistance is the on-resistance value of the pMOS transistor 59 =
200 [Ω].

In the input mode, the output control signal SA =
When fixing to "0", SB = "0" and SC = "0", fix the pMOS transistor 59 = OFF and the pMOS transistor 60 = OFF so that the pMOS transistors 59 and 60 do not function as the terminating resistors. can do.

As described above, according to the sixth embodiment of the present invention, the pMOS transistor 5 forming the output circuit 58
Since 9, 60 can be used as a terminating resistor,
In the input mode, reflection of transmission signals can be prevented, signal transmission can be speeded up, and terminal resistors on the printed circuit board are not required without increasing the chip size. Can be planned.

Seventh Embodiment FIG. 7 FIG. 7 is a circuit diagram showing a main part of a seventh embodiment of the present invention. 7, reference numeral 70 denotes an external terminal for signal input / output connected to the external signal line, and 71 denotes an open drain type output circuit for outputting an output signal to the external terminal 70.

In the output circuit 71, reference numeral 72 denotes a pMOS transistor having an on-resistance of 67 [Ω]; 73, a pMOS transistor having an on-resistance of 267 [Ω];
Reference numeral 4 denotes a pMOS transistor having an on-resistance of 800 [Ω].
74 has a drain connected to the external terminal 70 and a source connected to the VDD power supply line 75.

Reference numeral 76 denotes pM based on output control signals SA, SB, SC, SD, SE output from the internal circuit.
This is an output control circuit that controls ON and OFF of the OS transistors 72, 73, and 74.

In the output control circuit 76, 77 is an inverter for inverting the output control signal SA, 78 is an inverter for inverting the output control signal SB, and 79 is inverters 77 and 7
8 and the output control signal SC are NAND-processed to obtain pM
NAN that controls ON and OFF of the OS transistor 72
This is a D circuit.

An AND circuit 80 performs an AND operation on the output of the inverter 77 and the output control signal SB, and an output circuit 81 sets the output control signals SC and SD and the output of the AND circuit 80 to NO.
A NOR circuit 82 performs an R process to control the ON / OFF of the pMOS transistor 73, and a NOR circuit 82 performs a NOR process on the output control signals SC and SE and the output of the AND circuit 80 to control the ON / OFF of the pMOS transistor 74. is there.

Table 4 shows the output control signals SA, SB, SC,
Logic values of SD and SE and pMOS transistors 72 and 7
3 shows a part of the relationship between ON and OFF states of 3 and 74.

[0140]

[Table 4]

That is, output control signal SA = "0", SB =
When "0", SC = "1", SD = "0", SE = "0", the output of the inverter 77 = "1", the output of the inverter 78 = "1", and the output of the NAND circuit 79 =
“0”, pMOS transistor 72 = ON, output of NOR circuit 81 = “0”, pMOS transistor 73 = O
N, the output of the NOR circuit 82 = "0", and the pMOS transistor 74 is turned on.

Further, output control signal SA = "0", SB =
When "1", SC = "0", SD = "0", SE = "0", the output of the NAND circuit 79 = "1" and the pMOS
Transistor 72 = OFF, output of inverter 77 =
“1”, output of AND circuit 80 = “1”, NOR circuit 8
1 output = “0”, pMOS transistor 73 = ON,
The output of the NOR circuit 82 = "0", and the pMOS transistor 74 is turned on.

Output control signal SA = "0", SB =
When "0", SC = "0", SD = "1" and SE = "0", the output of the NAND circuit 79 = "1" and the pMOS
Transistor 72 = OFF, output of NOR circuit 81 =
“0”, pMOS transistor 73 = ON, output of AND circuit 80 = “0”, output of NOR circuit 82 = “1”,
The pMOS transistor 74 is turned off.

Further, output control signal SA = "0", SB =
When "0", SC = "0", SD = "0" and SE = "1", the output of the NAND circuit 79 = "1" and the pMOS
Transistor 72 = OFF, output of AND circuit 80 =
“0”, output of NOR circuit 81 = “1”, pMOS transistor 73 = OFF, output of NOR circuit 82 =
“0”, the pMOS transistor 74 = ON.

The output control signal SA = "0", SB =
When "0", SC = "0", SD = "0", SE = "0", the output of the NAND circuit 79 = "1" and the pMOS
Transistor 72 = OFF, output of AND circuit 80 =
“0”, output of NOR circuit 81 = “1”, pMOS transistor 73 = OFF, output of NOR circuit 82 =
“1”, pMOS transistor 74 = OFF.

Therefore, in the output mode, the output control signals SA = "0", SB = "0", SC = "1", SD = "
When "0" and SE = "0", the pMOS transistor 72 = ON, the pMOS transistor 73 = ON,
By setting the pMOS transistor 74 = ON, “1” can be output as an output signal.

In this case, the output impedance of the output circuit 71 is 1 / (1 / the ON resistance value of the pMOS transistor 72 + 1 / the ON resistance value of the pMOS transistor 73 + 1
/ ON resistance value of pMOS transistor 74) = 1 / (1
/ 67 + 1/267 + 1/800) = 50 [Ω].

In the output mode, the output control signal SA =
"0", SB = "1", SC = "0", SD = "0",
When SE = "0", the pMOS transistor 7
2 = OFF, pMOS transistor 73 = ON, pMO
The S transistor 74 is turned on, and in this case also, "1" can be output as an output signal.

In this case, the output impedance of output circuit 71 is 1 / (1 / ON resistance of pMOS transistor 73 + 1 / ON resistance of pMOS transistor 74) =
1 / (1/267 + 1/800) = 200 [Ω].

In the output mode, the output control signal SA =
"0", SB = "0", SC = "0", SD = "1",
When SE = "0", the pMOS transistor 7
2 = OFF, pMOS transistor 73 = ON, pMO
The S transistor 74 is turned off, and in this case also, "1" can be output as an output signal.

In this case, the output impedance of the output circuit 71 is the ON resistance value of the pMOS transistor 73 = 26.
7 [Ω].

In the output mode, the output control signal SA =
"0", SB = "0", SC = "0", SD = "0",
When SE = "1", the pMOS transistor 7
2 = OFF, pMOS transistor 73 = OFF, pM
The OS transistor 74 is turned on, and in this case also, "1" can be output as an output signal.

In this case, the output impedance of output circuit 71 is the ON resistance value of pMOS transistor 74 = 80
0 [Ω].

In the output mode, the output control signal SA =
"0", SB = "0", SC = "0", SD = "0",
When SE = "0", the pMOS transistor 7
2 = OFF, pMOS transistor 73 = OFF, pM
When the OS transistor 74 is turned off, “0” can be output as an output signal.

On the other hand, in the input mode, the output control signals SA = "0", SB = "0", SC = "1", SD = "
When “0” and SE = “0” are fixed, the pMOS transistor 72 = ON and the pMOS transistor 73 = O
N, pMOS transistor 74 is fixed at ON and pMO
S transistors 72, 73 and 74 are connected to external terminal 70 and VD
It can function as a terminating resistor connected to the D power supply line 75.

In this case, the terminating resistance value is 1 / (1 / pM
ON-resistance value of OS transistor 72 + ON-resistance value of pMOS transistor 73 + 1 / ON-resistance value of pMOS transistor 74) = 1 / (1/67 + 1/267 + 1)
/ 800) = 50 [Ω].

In the input mode, the output control signal SA =
"0", SB = "1", SC = "0", SD = "0",
When SE is fixed to “0”, the pMOS transistor 72 is turned off, the pMOS transistor 73 is turned on, and p
MOS transistor 74 is fixed at ON, and pMOS transistors 73 and 74 are connected to external terminal 70 and VDD power supply line 75.
And can function as a terminating resistor connected between them.

In this case, the terminating resistance value is 1 / (1 / pM
ON resistance value of OS transistor 73 + 1 / ON resistance value of pMOS transistor 74) = 1 / (1/267 + 1 /
800) = 200 [Ω].

In the input mode, the output control signal SA =
"0", SB = "0", SC = "0", SD = "1",
When SE is fixed to “0”, the pMOS transistor 72 is turned off, the pMOS transistor 73 is turned on, and p
By fixing the MOS transistor 74 to OFF, the pMOS transistor 73 can function as a terminating resistor connected between the external terminal 70 and the VDD power supply line 75,
In this case, the termination resistance value is the ON resistance value of the pMOS transistor 73 = 267 [Ω].

In the input mode, the output control signal SA =
"0", SB = "0", SC = "0", SD = "0",
When SE is fixed to “1”, the pMOS transistor 72 = OFF, the pMOS transistor 73 = OFF,
The pMOS transistor 74 can be fixed to ON, and the pMOS transistor 74 can function as a terminating resistor connected between the external terminal 70 and the VDD power supply line 75,
In this case, the termination resistance value is the ON resistance value of the pMOS transistor 74 = 800 [Ω].

In the input mode, the output control signal SA =
"0", SB = "0", SC = "0", SD = "0",
When SE is fixed to “0”, the pMOS transistor 72 = OFF, the pMOS transistor 73 = OFF,
pMOS transistor 74 is fixed at OFF, and pMOS
The transistors 72, 73, and 74 can be prevented from functioning as termination resistors.

As described above, according to the seventh embodiment of the present invention, the pMOS transistor 7 forming the output circuit 71
Since 2, 73 and 74 can be used as terminating resistors, reflection of transmission signals can be prevented in the input mode, signal transmission can be speeded up, and chip size does not increase. This eliminates the need for a terminating resistor on the printed board, and allows the printed board to be downsized.

Eighth Embodiment FIG. 8 FIG. 8 is a circuit diagram showing a main part of an eighth embodiment of the present invention. 8, reference numeral 85 denotes an external terminal for signal input / output connected to an external signal line, and reference numeral 86 denotes a push-pull type output circuit for outputting an output signal to the external terminal 85.

In the output circuit 86, 87 is a pMOS transistor having an on-resistance of 67 [Ω], 88 is an nMOS transistor having an on-resistance of 67 [Ω], 89
Is a pMOS transistor having an ON resistance of 200 [Ω], and 90 is an nMOS transistor having an ON resistance of 200 [Ω].

Here, pMOS transistors 87 and 89
Has a drain connected to the external terminal 85 and a source connected to VD
The nMOS transistors 88 and 90 have their drains connected to the external terminal 85 and their sources connected to the ground line.

An output control circuit 92 controls ON and OFF of the pMOS transistors 87 and 89 and the nMOS transistors 88 and 90 based on output control signals SA, SB and SC output from internal circuits.

In the output control circuit 92, 93 is an inverter for inverting the output control signal SA, 94 is an inverter for inverting the output control signal SB, and 95 is inverters 93 and 9
4 and the output control signal SC are NAND-processed to obtain pM
NAN that controls ON and OFF of the OS transistor 87
This is a D circuit.

Reference numeral 96 denotes output control signals SA, SB, S
C is NOR-processed to turn on the nMOS transistor 88,
This is a NOR circuit that controls OFF.

Reference numeral 97 denotes an AND circuit for performing an AND process on the output of the inverter 93 and the output control signal SB.
This is a NOR circuit that performs a NOR process on the output of the ND circuit 97 and the output control signal SC to control ON / OFF of the pMOS transistor 89.

An OR circuit 99 performs an OR operation on the output of the inverter 94 and the output control signal SA.
This is a NAND circuit that controls ON and OFF of the nMOS transistor 90 by performing NAND processing on the output of the circuit 99 and the output control signal SC.

Table 5 shows the logical values of the output control signals SA, SB, SC, the pMOS transistors 87, 89, and the nMOS.
A part of the relationship between the ON and OFF states of the transistors 88 and 90 is shown.

[0172]

[Table 5]

That is, output control signal SA = “0”, SB =
When "0" and SC = "0", the output of the NAND circuit 95 = "1", the pMOS transistor 87 = OFF, N
Output of OR circuit 96 = "1", nMOS transistor 8
8 = ON.

Output of AND circuit 97 = “0”, N
Output of OR circuit 98 = "1", pMOS transistor 8
9 = OFF, output of NAND circuit 100 = “1”, nM
The OS transistor 90 is turned on.

Output control signal SA = "0", SB =
When “0” and SC = “1”, the output of the inverter 93 = “1”, the output of the inverter 94 = “1”, and the NAND
Output of circuit 95 = “0”, pMOS transistor 87 =
ON, output of NOR circuit 96 = "0", nMOS transistor 88 = OFF.

The output of AND circuit 97 = "0", N
Output of OR circuit 98 = "0", pMOS transistor 8
9 = ON, output of OR circuit 99 = “1”, output of NAND circuit 100 = “0”, nMOS transistor 90 = O
It becomes FF.

Output control signal SA = "0", SB =
When "1" and SC = "0", the output of the NAND circuit 95 = "1", the pMOS transistor 87 = OFF, N
Output of OR circuit 96 = "0", nMOS transistor 8
8 = OFF.

The output of inverter 93 = "1", A
Output of ND circuit 97 = “1”, Output of NOR circuit 98 =
"0", pMOS transistor 89 = ON, output of inverter 94 = "0", output of OR circuit 99 = "0", N
The output of the AND circuit 100 = "1", and the nMOS transistor 90 is turned on.

Further, output control signal SA = “1”, SB =
When "0" and SC = "0", the output of the NAND circuit 95 = "1", the pMOS transistor 87 = OFF, N
Output of OR circuit 96 = "0", nMOS transistor 8
8 = OFF.

The output of AND circuit 97 = “0”, N
Output of OR circuit 98 = "1", pMOS transistor 8
9 = OFF, output of NAND circuit 100 = “1”, nM
The OS transistor 90 is turned on.

Further, output control signal SA = “1”, SB =
When “0” and SC = “1”, the output of the inverter 93 = “0”, the output of the NAND circuit 95 = “1”, and pMO
S transistor 87 = OFF, output of NOR circuit 96 =
“0”, the nMOS transistor 88 = OFF.

The output of NOR circuit 98 = “0”, p
MOS transistor 89 = ON, output of OR circuit 99 =
“1”, output of NAND circuit 100 = “0”, nMOS
The transistor 90 is turned off.

Therefore, in the output mode, the output control signal SA is fixed at "0" and SB is fixed at "0",
To make C transition, the output circuit 86 is connected to the pMOS transistors 87 and 89 and the nMOS transistors 88 and 9.
It can function as a push-pull type output circuit composed of zero.

In this case, output control signal SC =
In the case of “0”, the pMOS transistor 87 = O
FF, pMOS transistor 89 = OFF, nMOS transistor 88 = ON, nMOS transistor 90 = O
N, and “0” can be output as an output signal.

On the other hand, output control signal SC = "1"
In this case, pMOS transistor 87 = ON, p
By setting the MOS transistor 89 to ON, the nMOS transistor 88 to OFF, and the nMOS transistor 90 to OFF, "1" can be output as an output signal.

In this case, the output impedance of the output circuit 86 is 1 / (1 / ON resistance of pMOS transistor 87 + 1 / ON resistance of pMOS transistor 89) =
1 / (1 / ON resistance value of nMOS transistor 88 + 1
/ On resistance value of nMOS transistor 90) = 1 / (1
/ 67 + 1/200) = 50 [Ω].

In the output mode, the output control signal SA =
When the output control signal SC is transited by fixing “1” and SB = “0”, the output circuit 86 can function as a push-pull output circuit including the pMOS transistor 89 and the nMOS transistor 90.

In this case, output control signal SC =
In the case of “0”, the pMOS transistor 89 = O
The FF and the nMOS transistor 90 can be turned on, and "1" can be output as an output signal.

On the other hand, output control signal SC = "1"
In this case, the pMOS transistor 89 = ON, n
By setting the MOS transistor 90 to OFF, "1" can be output as an output signal.

In this case, the output impedance of output circuit 86 is the ON resistance value of pMOS transistor 89 = nM
The ON resistance value of the OS transistor 90 = 200 [Ω].

In the input mode, the output control signal SA =
When fixing "0", SB = "1", and SC = "0", the pMOS transistor 87 = OFF, the nMOS transistor 88 = OFF, and the pMOS transistor 89 = O
N, nMOS transistor 90 can be fixed at ON.

Therefore, the pMOS transistor 89 functions as a termination resistor connected between the external terminal 85 and the VDD power supply line 91, and the nMOS transistor 90 functions as a termination resistor connected between the external terminal 85 and the ground line. Can be.

In this case, the terminating resistance value is 1 / (1 / pM
ON resistance value of OS transistor 89 + 1 / ON resistance value of nMOS transistor 90) = 1 / (1/200 + 1 /
200) = 100 [Ω].

In the input mode, the output control signal SA =
When fixing “1”, SB = “0”, and SC = “0”, the pMOS transistor 87 = OFF, the nMOS transistor 88 = OFF, and the pMOS transistor 89 = O
FF and nMOS transistor 90 can be fixed at ON.

Therefore, nMOS transistor 90 can function as a terminating resistor connected between external terminal 85 and the ground line. In this case, the terminating resistance value is n
The ON resistance value of the MOS transistor 90 becomes 200 [Ω].

In the input mode, the output control signal SA =
When fixing "1", SB = "0", and SC = "1", the pMOS transistor 87 = OFF, the nMOS transistor 88 = OFF, and the pMOS transistor 89 = O
N, nMOS transistor 90 can be fixed at OFF.

Therefore, the pMOS transistor 89 can function as a terminating resistor connected between the external terminal 85 and the ground line. In this case, the terminating resistance value is p
The ON resistance value of the MOS transistor 89 becomes 200 [Ω].

As described above, according to the eighth embodiment of the present invention, the pMOS transistor 89 forming the output circuit 86
In addition, since the nMOS transistor 90 can be used as a terminating resistor, reflection of a transmission signal can be prevented in the input mode, and signal transmission can be speeded up.
The terminating resistor on the printed circuit board is not required without increasing the chip size, and the printed circuit board can be reduced in size.

FIG. 9 is a circuit diagram showing a simulation model of the signal transmission circuit. In FIG. 9, reference numeral 103 denotes a signal source; 104, an output impedance of Z0 / k [Ω];
05 is the transmitting end, 106 is the characteristic impedance Z0
Reference numeral 107 denotes a receiving end, and reference numeral 108 denotes a terminating resistor having a resistance value of Z0 × k [Ω].

That is, k is the resistance ratio, and the external signal line 1
06 characteristic impedance value / output impedance 1
04 value = resistance value of terminating resistor 108 / external signal line 106
Is the value of the characteristic impedance.

FIG. 10 is a diagram showing the relationship between the resistance ratio k, the voltage gain and the SN ratio in the simulation model shown in FIG.
0 indicates the SN ratio.

As is clear from FIG. 10, when the resistance ratio k is 1.6 to 2.0, that is, when the output impedance is 1
04 is 1/1 of the characteristic impedance of the external signal line 106.
When the resistance is set to 1.6 to 1 / 2.0 and the resistance value of the terminating resistor 108 is set to 1.6 to 2.0 times the characteristic impedance of the external signal line 106, the voltage gain is set to -3 dB or more and the SN Good transmission conditions with a ratio of 20 dB or more can be obtained.

Therefore, also in the eighth embodiment of the present invention, in the output mode, for example, the output circuit 86 is set to pM
It operates as a push-pull type output circuit composed of OS transistors 87 and 89 and nMOS transistors 88 and 90. In the input mode, for example, when the pMOS transistor 89 or the nMOS transistor 90 functions as a terminating resistor, the output impedance of the output circuit 86 Of the characteristic impedance of the external signal line is 1 / 1.6-
PMOS so that the termination resistance value is 1.6 to 2.0 times the characteristic impedance of the external signal line.
Transistors 87 and 89 and nMOS transistor 8
When determining the sizes of 8, 90, the voltage gain is set to -3.
It is possible to obtain good transmission conditions of not less than dB and an SN ratio of not less than 20 dB.

[0204]

As described above, according to the first invention (semiconductor integrated circuit device of the first aspect) of the present invention, the n-channel insulated gate field effect transistor constituting the input protection circuit is provided with a terminating resistor. In the input mode, reflection of transmission signals can be prevented, signal transmission can be speeded up, and a termination resistor on the printed circuit board is not required without increasing the chip size. Thus, the size of the printed circuit board can be reduced.

According to the second aspect of the present invention, the p-channel insulated gate field effect transistor constituting the input protection circuit can be used as a terminating resistor. In the input mode, reflection of transmission signals can be prevented, signal transmission can be speeded up, and an increase in chip size does not occur.
This eliminates the need for a terminating resistor on the printed board, and allows the printed board to be downsized.

According to the third aspect of the present invention, the n-channel insulated gate field effect transistor and the p-channel insulated gate field effect transistor constituting the input protection circuit are provided. Since it can be used as a terminating resistor, reflection of transmission signals can be prevented in the input mode, signal transmission can be speeded up, and the terminating resistor on the printed circuit board can be used without increasing the chip size. And the size of the printed circuit board can be reduced.

According to the fourth aspect of the present invention, the same effect as that of the third aspect can be obtained, and the n-channel insulated gate constituting the input circuit can be obtained. The test can be performed without using the field-effect transistor and the p-channel insulated-gate field-effect transistor as termination resistors.

According to the fifth aspect of the present invention (semiconductor integrated circuit device according to the fifth aspect), the same effects as those of the third aspect can be obtained, and the input circuit can be configured by selecting n It is also possible to use only one of the terminating resistor composed of the channel insulated gate field effect transistor and the p-channel insulated gate field effect transistor constituting the input circuit as the terminating resistor.

According to the sixth invention (semiconductor integrated circuit device) of the present invention, an n-channel insulated gate field effect transistor constituting an open drain type output circuit is used as a termination resistor. So you can
In the input mode, reflection of transmission signals can be prevented, signal transmission can be speeded up, and terminal resistors on the printed circuit board are not required without increasing the chip size. Can be planned.

According to the seventh aspect of the present invention, a p-channel insulated gate type field effect transistor constituting an open drain type output circuit is used as a termination resistor. So you can
In the input mode, reflection of transmission signals can be prevented, signal transmission can be speeded up, and terminal resistors on the printed circuit board are not required without increasing the chip size. Can be planned.

According to the eighth aspect of the present invention, the n-channel insulated-gate field-effect transistor and the p-channel insulated-gate electric field constituting the push-pull type output circuit are provided. Since the effect transistor can be used as a terminating resistor, reflection of a transmission signal can be prevented in the input mode, signal transmission can be speeded up, and an increase in chip size does not occur on a printed circuit board. This eliminates the need for a terminating resistor, and makes it possible to reduce the size of the printed circuit board.

According to the ninth aspect (semiconductor integrated circuit device of the ninth aspect) of the present invention, the same effects as those of the eighth aspect can be obtained, and the output circuit can be selectively configured. Alternatively, one or more of one or a plurality of n-channel insulated gate field effect transistors or one or more of one or a plurality of p-channel insulated gate field effect transistors forming an output circuit can function as a termination resistor. .

According to the tenth aspect (semiconductor integrated circuit device of the tenth aspect) of the present invention, the same effects as those of the eighth aspect can be obtained, and a signal having good voltage gain and SN ratio can be obtained. Transmission can take place.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a main part of a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a main part of a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a main part of a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a main part of a seventh embodiment of the present invention.

FIG. 8 is a circuit diagram showing a main part of an eighth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a simulation model of a signal transmission circuit.

10 is a diagram showing a relationship between a resistance ratio k, a voltage gain and an SN ratio in the simulation model shown in FIG.

[Explanation of symbols]

 SA, SB, SC, SD, SE output control signal

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 29/78 H03K 19/003 (72) Inventor Yoshinori Maeda 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa FUJITSU LIMITED (72) Inventor Junnoyuki Takushima 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (10)

[Claims] An input protection circuit having an n-channel insulated gate field effect transistor having a drain connected to an external terminal, a source connected to a ground line, and a gate connected to a power supply line for supplying a positive power supply voltage. A semiconductor integrated circuit device comprising: 2. An input protection circuit having a p-channel insulated gate field effect transistor having a drain connected to an external terminal, a source connected to a power supply line supplying a positive power supply voltage, and a gate connected to a ground line. A semiconductor integrated circuit device comprising: 3. An n-channel insulated gate field effect transistor having a drain connected to an external terminal, a source connected to a ground line, a gate connected to a power supply line for supplying a positive power supply voltage, and a drain connected to the power supply line. A semiconductor integrated circuit comprising: an input protection circuit having a p-channel insulated gate field-effect transistor connected to an external terminal, a source connected to the power supply line, and a gate connected to the ground line. Circuit device. 4. A current path disconnecting circuit capable of selectively disconnecting a current path formed by said n-channel insulated gate field effect transistor and a current path formed by said p-channel insulated gate field effect transistor. 4. The semiconductor integrated circuit device according to claim 3, comprising: 5. A current path capable of selectively cutting either a current path formed by the n-channel insulated gate field effect transistor or a current path formed by the p-channel insulated gate field effect transistor. 4. The semiconductor integrated circuit device according to claim 3, further comprising a cutting circuit. 6. An open drain type output circuit comprising one or a plurality of n-channel insulated gate field effect transistors having a drain connected to an external terminal for signal input / output and a source connected to a ground line; A semiconductor integrated circuit device comprising: an output control circuit capable of fixing one or more of the one or more n-channel insulated gate field effect transistors in a conductive state in a mode. 7. An open drain comprising one or more p-channel insulated gate field effect transistors having a drain connected to an external terminal for signal input / output and a source connected to a power supply line for supplying a positive power supply voltage. A semiconductor device comprising: an output circuit having a shape; and an output control circuit capable of fixing one or more of the one or more p-channel insulated gate field effect transistors in a conductive state in an input mode. Integrated circuit device. 8. An n-channel insulated gate field effect transistor having a drain connected to an external terminal for signal input / output, a source connected to a ground line, and a drain connected to the external terminal, A push-pull output circuit having one or more p-channel insulated gate field effect transistors having a source connected to a power supply line supplying a positive power supply voltage; and the one or more n-channels in an input mode. An output control circuit capable of fixing one or more of the insulated gate field effect transistor and one or more of the one or more p-channel insulated gate field effect transistors in a conductive state is provided. Semiconductor integrated circuit device. 9. The output control circuit according to claim 1, wherein one or more of said one or more n-channel insulated gate field-effect transistors or one or more of said one or more p-channel insulated gate field-effect transistors is selected in an input mode. 9. The semiconductor integrated circuit device according to claim 8, wherein one or more of the semiconductor integrated circuit devices can be fixed in a conductive state. 10. The output impedance of the plurality of n-channel insulated gate field effect transistors and the plurality of p-channel insulated gate field effect transistors in an output mode is the characteristic impedance of an external signal line connected to the external terminal. Functions as an output transistor that is 1 / 1.6 to 1 / 2.0 times as large as the resistance of the external signal line in the input mode. 9. The semiconductor integrated circuit device according to claim 8, wherein said semiconductor integrated circuit device has a size capable of functioning as a terminating resistor.