JPH05167426A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent occurrence of malfunction by providing a reflectance decrease means based on a characteristic impedance of a transmission wire to a position in which the impedance in the transmission wire is changed discontinuously. CONSTITUTION:A reflection reduction circuit including CMOS circuits 1,4 formed on a semiconductor board 52 and resistors 5, 7 used to decrease the reflection or to prevent the reflection is provided before a resistive component 14. That is, the resistor 5 is connected in the vicinity of the resistive component 14 and between a wire 12 and a power supply voltage Vcc and the resistor 7 is connected in the vicinity of the resistive component 14 and between the wire 12 and a power supply voltage Vss. The resistors 5, 7 act like termination resistors in a sense. Then the energy of the transmission signal is reflected partially at least one position on the wire 12, and the reflection is reduced at least at one position based on a characteristic impedance of the wire 12. Then occurrence of malfunction due to reflection is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device capable of preventing reflection of a transmission signal generated in wiring.

[0002]

2. Description of the Related Art In recent years, as the degree of integration of semiconductor integrated circuit devices has increased, the demand for high-speed operation has also increased. For example, the currently commonly known microprocessor operates under a basic operating clock signal of 40 MHz, and it is expected that the processing speed will be ever higher.

As the operating speed of a semiconductor integrated circuit device increases, the presence of reflected signals in wiring cannot be ignored. For example, when the semiconductor integrated circuit device is operated under a basic operation clock signal exceeding 100 MHz, reflection of the transmission signal occurs at various parts of the wiring. The reflection of the transmission signal occurs at a portion where the impedance of the wiring is discontinuously changed, for example, a location where the wiring is connected using a contact hole or a location where the width of the wiring is reduced.

The reflection of the transmission signal generated in the wiring not only reduces the energy of the transmission signal, but also transmits the reflection signal to the electronic circuit at the destination, which causes malfunction. The present invention is generally applied to a semiconductor integrated circuit device that operates at a high frequency exceeding 100 MHz, but in the following description, a microprocessor will be described as an example.

FIG. 7 is a general block diagram of a microprocessor. This block diagram schematically shows the layout of the circuit configuration formed on the semiconductor substrate 50. Referring to FIG. 7, this microprocessor includes a bus control circuit 61 for controlling an internal data bus and an internal address bus, an instruction decoder 62 for decoding an instruction code IC given from the bus control circuit 61, and a decoded decoder. The control circuit 63 generates various control signals Sc in response to the instruction code, and the operation execution circuit 64 executes operations in response to the control signals Sc. Data and address signals used in the calculation are given to the calculation execution circuit 64 via the bus control circuit 61. The data and address signals are transmitted via the wiring 65 formed on the semiconductor substrate 50. On the other hand, the control signal Sc is transmitted via the wiring 66 formed on the substrate 50. It is pointed out that these wires 65 and 66 generally have long wire lengths.

FIG. 8 is a circuit block diagram for explaining signal transmission in a conventional semiconductor integrated circuit device.
Referring to FIG. 8, the semiconductor integrated circuit device includes two CMOS circuits 1 and 4 formed on a semiconductor substrate 51. Each of the CMOS circuits 1 and 4 is composed of a CMOS transistor (not shown). An inverter 2 for transmission is provided at the output of the CMOS circuit 1.
An inverter 3 for receiving is provided at the input of the CMOS circuit 4. The wiring 12 is provided between the inverters 2 and 3. In the following description, the transmission signal Sp output from the CMOS circuit 1 is transmitted to the CMOS circuit 4 via the wiring 12.
Is assumed to be transmitted to. Wiring 12 shown in FIG.
Corresponds to one of the wires 65 or 66 in the microprocessor shown in FIG. 7, for example.

As described above, the wiring formed on the semiconductor substrate 51 passes through the long wiring path on the substrate 51 to form the C wiring.
The MOS circuits 1 and 4 are connected. The long wiring path includes a connection portion using a contact hole and / or a portion where the width of the wiring is reduced. In such a place, the impedance of the wiring 12 is generally partially changed. In other words, the impedance of the wiring 12 is discontinuously changed. The resistance 14 shown in FIG. 8 equivalently shows the resistance component generated at the connection point of the wiring using the contact hole, for example. The impedance of the wiring 12 is discontinuously changed due to the change in the shape of the wiring as described above, and therefore discontinuities in such impedance can occur at a plurality of points in a long wiring path. However, in FIG. 8, only one place is shown for simplification of description.

As shown in FIG. 8, the transmission signal Sp is transmitted to the CMSO circuit 4 via the wiring 12, but due to the presence of the resistance component 14, a part of the energy of the transmission signal Sp is reflected. To be done. Therefore, the resistance component 14
The reflection signal Sr reflected by is superimposed on the wiring 12. The other component (main component) St of the transmission signal Sp is
It is transmitted to the CMOS circuit 4 via the resistance component 14.

The cause of the reflection of the transmission signal Sp is explained as follows. Since the transmission signal Sp is a high-frequency digital clock signal exceeding 100 MHz, it contains various high-frequency signal components. Therefore, it is understood that the wiring 12 has a characteristic impedance in signal transmission at high frequency. Therefore, the presence of the resistance component 14 acts as a discontinuity point of the characteristic impedance in the wiring 12. In other words, the presence of the resistance component 14 causes a mismatch in the wiring. The reflection of the transmission signal Sp is
It occurs at such mismatches in impedance.

[0010]

The reflected signal Sr causes the following problems. First, the reflected signal Sr having a high frequency is also transmitted to the destination CMOS circuit 4, and CM
This causes a malfunction in the OS circuit 4. That is, C
The reflected signal Sr transmitted to the MOS circuit is the original signal S
It is superimposed on t and acts as noise on the CMOS circuit 4. As a result, malfunction occurs in the CMOS circuit 4.

In addition to this, since the transmission signal Sp is a clock signal having a high frequency, that is, a pulse signal,
It contains various high frequency signal components. In other words, the signal Sp includes wideband signal components. As mentioned above, the high frequency signal components are partially lost from the transmitted signal Sp by reflection, which changes the waveform of the transmitted signal St. That is, the steep rise or fall of the transmitted signal St is lost. It is pointed out that this also causes the malfunction in the CMOS circuit 4.

Generally speaking, a clock signal or a pulse signal handled in a digital circuit is a wide band signal, and therefore impedance discontinuities (or mismatch points) are present everywhere in the circuit. This means that reflections can occur everywhere in the circuit. As a result, malfunctions are likely to occur in reflection in high-speed digital circuits.

The present invention has been made to solve the above problems, and it is possible to prevent malfunction of a semiconductor integrated circuit device operated at a high frequency due to reflection of a transmission signal. To aim.

[0014]

A semiconductor integrated circuit device according to the present invention includes a semiconductor substrate, first and second electronic circuits formed on the substrate, and a high frequency output from the first electronic circuit. Transmission wiring for transmitting a transmission signal to the second electronic circuit. The impedance of the transmission line is discontinuously changed due to a change in the shape of the transmission line at least at one position on the line. The semiconductor integrated circuit device further includes reflection reducing means for reducing the reflection occurring at the at least one position of the transmission wiring based on the characteristic impedance of the transmission wiring.

[0015]

In the semiconductor integrated circuit device according to the present invention, the energy of the transmission signal is partially reflected at the at least one position on the wiring, and the reflection reduction means is provided at the at least one position based on the characteristic impedance of the wiring. Reduce reflections at. As a result, the reflection is prevented from causing a malfunction.

[0016]

1 is a simplified circuit diagram of a semiconductor integrated circuit device showing an embodiment of the present invention. The circuit shown in FIG. 1 can be applied to the signal transmission wiring in the microcomputer shown in FIG. 7, for example. Referring to FIG.
This semiconductor integrated circuit device includes CMOS circuits 1 and 4 formed on a semiconductor substrate 52. In comparison with the conventional circuit shown in FIG. 8, it is pointed out that a reflection reducing circuit including resistors 5 and 7 for reducing or preventing reflection is provided prior to the resistance component 14. That is, the resistor 5 is connected between the wiring 12 and the power supply potential Vcc near the resistance component 14. On the other hand, the resistor 7 is connected between the wiring 12 and the ground potential Vss near the resistance component 14. It is pointed out that resistors 5 and 7 are, in a sense, termination resistors.

The characteristic impedance of the transmission line 12 is Zo.
Then, the impedance or resistance value of each of the resistors 5 and 7 at high frequency is set to 2Zo. For example, assuming that the characteristic impedance Zo of the transmission line 12 at a certain high frequency is 100Ω, the resistors 5 and 7 having the impedance (or resistance value) of 200Ω at the same frequency are provided. Generally, the characteristic impedance Zo of the wiring can be known by calculation or simulation based on the width, thickness, dielectric constant, sheet resistance, etc. of the wiring on the semiconductor substrate.

Resistors 5 and 7 serve to eliminate the mismatch in impedance caused by the presence of resistive component 14. That is, impedance matching is obtained at the position on the wiring 12 prior to the resistance component 14 by the action of the resistors 5 and 7, so that the reflection of the transmission signal Sp is reduced or prevented at this position. As a result, the transmission signal Sp is transmitted to the CMOS circuit 4 without being reflected by the presence of the resistance component 14.

Therefore, since the signal transmitted to the CMOS circuit 4 does not include a reflected signal component having a high frequency, malfunction of the CMOS circuit 4 can be prevented. In addition to this, a desired waveform of the transmitted signal, ie the transmitted clock signal or pulse signal, is obtained in the CMOS circuit 4, which also prevents malfunctions.

In the above description, the resistance value of the resistors 5 and 7 is twice the characteristic impedance Zo (= 2Zo).
Although the example in which is selected is described, it is pointed out that even if the resistance values of the resistors 5 and 7 exceed 10 times the characteristic impedance Zo, the effect of preventing reflection is actually obtained. In other words, it is pointed out that the resistance values of the resistors 5 and 7 are preferably selected also taking into account the power consumption and / or the reduction of the amplitude of the transmitted signal.

FIG. 2 is a structural diagram on the semiconductor substrate of the reflection reducing circuit shown in FIG. Referring to FIG. 2A, CM
The OS inverter 2 is a PM formed in the n-well 21.
It includes an OS transistor Q1 and an NMOS transistor Q2 formed in the p well 22. On the other hand, the CMOS inverter 3 includes a PMOS transistor Q3 formed in the n-well 23 and an NMO formed in the p-well 24.
S transistor Q4. An aluminum wiring 13 is connected between the output of the inverter 2 and the input of the inverter 3. Aluminum wiring 12 is connected to polysilicon layer 28 forming the gates of transistors Q3 and Q4 through contact hole 27. Therefore, the resistance component 14 exists at the position of the contact hole 27.

Therefore, the resistors 5 and 7 for reducing the reflection are formed by the polysilicon layers 29 and 30 in the positions preceding the contact holes 27. That is, the resistor 5 is formed by the polysilicon layer 29 between the aluminum wiring 9 and the polysilicon wiring 12 for the power supply Vcc. On the other hand, the resistor 7 is formed by the polysilicon layer 30 between the aluminum wiring 10 for grounding and the polysilicon wiring 12.

FIG. 2B shows a sectional structure taken along line 2B-2B in FIG. 2A. As shown in FIG. 2B, the polysilicon layers 29 and 30 are formed between the semiconductor substrate 52 and the insulating films 25 and 26.

In the example shown in FIG. 2, the case where the resistance component 14 is caused by the presence of the contact hole 27 is shown, but as described above, the resistance component 14 is caused not only by the contact hole or the through hole but also by the wiring. It is pointed out that changes in shape (eg, reduction of wiring width) can occur. In addition to this, in the example shown in FIG. 2, the resistors 5 and 7 are formed by the polysilicon layers 29 and 30, but the resistors 5 and 7 can also be realized by a MOS transistor. In the following description, other embodiments of the present invention will be described.

FIG. 3 is a simplified circuit diagram of a semiconductor integrated circuit device showing another embodiment of the present invention. Referring to FIG. 3, the semiconductor integrated circuit device is formed on a semiconductor substrate 53, and has CMOS circuits 1 and 4 and a switching circuit 31 which operates in response to externally applied control signals S1 and S2. 32 and a control voltage generation circuit 33. The transmission signal Sp output from the CMOS circuit 1 is transmitted to the CMOS circuit 4 via the wiring 12.

Control voltage generating circuit 33 receives power supply potential Vcc and ground potential Vss from the outside, and generates predetermined control voltages V1 to V4. Switching circuit 31
Receives control voltages V1 and V2 and selectively outputs control voltages V1 and / or V2 in response to a control signal S1 applied from the outside. Switching circuit 32 receives control voltages V3 and V4 and selectively outputs them in response to control signal S2.

Prior to resistance component 14, PMOS transistors 5a and 6a are connected in parallel between transmission line 12 and power supply potential Vcc. Transistors 5a and 6a
Respectively receives control voltages V5 and V6 output from the switching circuit 31. In addition to this,
NMOS transistors 7a and 8a are connected in parallel between transmission line 12 and ground potential Vss. The gates of transistors 7a and 8a receive control voltages V7 and V8 output from switching circuit 32, respectively.

In operation, the control voltage generation circuit 33
Control voltage V1 each having a predetermined voltage level
To V4. The switching circuit 31 responds to the control signal S1 applied via the bonding pad 34 to supply the control voltages V1 and V2 to the transistor 5a.
And selectively to the gates of 6a. That is, the gate voltages of the transistors 5a and 6a can be controlled externally. Generally, the ON resistance or conduction resistance of a MOS transistor is changed depending on the gate voltage. Since the gate voltages of the transistors 5a and 6a shown in FIG. 3 can be externally controlled, the impedance for matching the impedance of the wiring, that is, the on-resistance of the transistors 5a and 6a is controlled to a preferable value.

The gate voltages of the NMOS transistors 7a and 8a can also be externally controlled via the switching circuit 32. As a result, the impedance for matching, namely transistors 5a, 6a, 7a and 8
Since the on-resistance of a can be set to an optimum value based on the characteristic impedance of the wiring 12, the reflection caused by the presence of the resistance component 14 can be more flexibly reduced.

FIG. 4 is a simplified circuit diagram of a semiconductor integrated circuit device showing still another embodiment of the present invention. Compared to the example shown in FIG. 3 with reference to FIG. 4, the matching transistors 5a formed on the semiconductor substrate 54,
It is pointed out that the gate voltages of 6a, 7a and 8a are directly controlled externally via bond pads 36-39. Therefore, the switching circuit 31
And 32 and the control voltage generating circuit 33 are not required.

By controlling the control voltage provided through the bonding pads 36 to 39, the impedance for matching, that is, the transistors 5a and 6a.
The on-resistance of a, 7a and 8a is adjusted to the desired value. Therefore, also in this embodiment, the resistance component 14
The reflections caused by the presence of are more flexibly prevented.

FIG. 5 is a simplified circuit diagram of a semiconductor integrated circuit device showing still another embodiment of the present invention. Referring to FIG. 5, in this embodiment, a PMOS for matching is used.
The transistor 5b and the NMOS transistor 7b are formed on the semiconductor substrate 55. The gate of the transistor 5b is grounded. The gate of transistor 7b is connected to power supply potential Vcc. Therefore, the transistors 5b and 7b are always brought to the ON state. As a result, these transistors 5b and 7b act as resistors having a resistance value determined by a predetermined ON resistance. In other words, transistors 5b and 7b
Correspond to the resistors 5 and 7 shown in FIG. 1, respectively.

FIG. 6 is a simplified circuit diagram of a semiconductor integrated circuit device showing still another embodiment of the present invention. Referring to FIG. 6, as in the example shown in FIGS. 3 and 4, PMOS transistors 5c, 6c and N for matching are provided.
MOS transistors 7c and 8c are formed on semiconductor substrate 56. The connection between the gates of the transistors 5c and 6c and the ground potential is FIB (Focused Io).
n Beam) and conductor films 43 and 44, which may be formed by n beam. Similarly, the connection between the gate of the transistor 7c and the power supply potential Vcc is also made by the conductor film 45 formed by FIB. The gate of the transistor 8c is a conductor film 4 formed by FIB.
It is grounded via 6.

In the embodiment shown in FIG. 6, the gate of the transistor for matching is selectively supplied with the power supply potential Vcc or the ground potential Vs by using the conductor film formed by FIB.
connected to s. Therefore, the impedance for matching, that is, the on-resistance for matching can be physically controlled. As a result, also in this embodiment, the reflection caused by the presence of the resistance component 14 can be prevented more preferably.

As described above, the semiconductor integrated circuit device operated under a high frequency such as a microprocessor has impedances for matching the impedances in the wiring, that is, the resistors 5 and 7, the conductive MOS transistor 5a, and the like. 6a, 7a, 8a and the like are provided prior to the resistance component 14 that causes reflection. Therefore,
It is possible to prevent the reflection of the transmission signal at the portion of the wiring 12 where the impedance is discontinuous. In addition to this, FIGS.
In the embodiments shown in FIGS. 5 and 6, the impedance for matching, that is, the on-resistance of the MOS transistor can be controlled electrically or physically, so that the reflection can be prevented more flexibly.

In the above description, the countermeasure for one discontinuity of impedance in one wiring 12 has been described.
It is pointed out that similar measures are taken at other places where the impedance of the wiring changes discontinuously. In addition to this, the resistance component 14 is caused not only by a contact hole or a through hole but also by a change in the shape of the wiring such as a reduction in the width of the wiring, and similar measures are taken also in such a portion. It is pointed out.

By effectively preventing the reflection in the transmission wiring as described above, the electronic circuit of the destination, that is, the CM.
A malfunction in the OS circuit 4 can be prevented.

[0038]

As described above, according to the present invention, since the reflection reducing means is provided based on the characteristic impedance of the transmission wiring at the position where the impedance of the transmission wiring is discontinuously changed, the reflection signal is reduced. As a result, malfunction is prevented.

[Brief description of drawings]

FIG. 1 is a simplified circuit diagram of a semiconductor integrated circuit device showing an embodiment of the present invention.

FIG. 2 is a structural diagram of the reflection reducing circuit shown in FIG. 1 on a semiconductor substrate.

FIG. 3 is a simplified circuit diagram of a semiconductor integrated circuit device showing another embodiment of the present invention.

FIG. 4 is a simplified circuit diagram of a semiconductor integrated circuit device showing still another embodiment of the present invention.

FIG. 5 is a simplified circuit diagram of a semiconductor integrated circuit device showing still another embodiment of the present invention.

FIG. 6 is a simplified circuit diagram of a semiconductor integrated circuit device showing still another embodiment of the present invention.

FIG. 7 is a general block diagram of a microprocessor.

FIG. 8 is a simplified circuit diagram showing signal transmission in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 1 CMOS circuit (transmission side) 4 CMOS circuit (reception side) 5 Matching resistance 12 Transmission wiring 14 Discontinuous resistance component in wiring 52 Semiconductor substrate Zo Wiring characteristic impedance

Claims (3)

[Claims] 1. A semiconductor integrated circuit device operated at a frequency exceeding a predetermined high frequency, comprising: a semiconductor substrate; first and second electronic circuits formed on the substrate; and on the substrate. And a transmission line for transmitting a high-frequency transmission signal output from the first electronic circuit to the second electronic circuit, the impedance of the transmission line being at least one of the lines. At a position, the energy of the transmission signal is discontinuously changed due to a change in a shape of the transmission wiring, the energy of the transmission signal is partially reflected at the at least one position on the wiring, The transmission line is connected between the vicinity of the position and the power supply potential,
A semiconductor integrated circuit device comprising reflection reducing means for reducing reflection occurring at one position based on the characteristic impedance of the transmission wiring. 2. An electric control means for electrically controlling the reflection reducing means so that the reflection reducing amount by the reflection reducing means is maximized in response to an externally applied control signal. Item 2. The semiconductor integrated circuit device according to item 1. 3. The semiconductor integrated circuit according to claim 1, further comprising a circuit connection physical changing means for physically changing a circuit connection in said reflection reducing means and maximizing a reflection reduction amount by said reflection reducing means. Circuit device.