JPH10223683A - Semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a semiconductor module adaptable to a three-dimensional laminate mounting structure and small-size/thin type configuration, by placing a wiring and inner leads between an insulation film and a surface having input/ output pads of a semiconductor chip, and making one side of a device hole smaller than that of the semiconductor chip. SOLUTION: On input/output pads of a semiconductor chip 101 tape automated bonding(TAB) bumps are mounted. A film carrier 102 is fed in the form of a TAB tape, having a previously formed wiring 106, inner leads 103 and vias 105. A device hole 110 is set to be smaller than the semiconductor chip 101 to avoid dropping the chip through the hole 110. The chip 101 and the film carrier 102 are TAB-connected so that the surface of the chip 101 having the input/output pads faces the wiring 106 and the inner leads 103 formed on the carrier film 102.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor module, and more particularly to a three-dimensional semiconductor multi-chip module in which semiconductor chips are three-dimensionally stacked.

[0002]

2. Description of the Related Art In recent years, three-dimensional semiconductor modules in which semiconductor chips are three-dimensionally stacked have been developed in order to improve the mounting density of semiconductor chips. As a known example of such a semiconductor module, there is JP-A-6-13541. The cross-sectional structure of the semiconductor module described in the known example,
For example, FIG. A semiconductor chip 602 is mounted on a wiring board 601 and both are interconnected by wires 603. The wiring board 601 and the wiring board 606 are connected by solder joint 6
Connect at 05. The lid 604 is provided for sealing the semiconductor chip 602 and determining the distance between the wiring substrates 601 and 606.

[0003]

FIG. 7 shows a structure in which the above-described semiconductor module is further reduced in size and thickness. FIG. 7A is a top view and FIG. 7B is a cross-sectional view. A film carrier 704 is composed of the insulating film 701, the wiring 702, and the inner leads 703, the semiconductor chip 705 is thinned by polishing, and the input / output pads on the inner leads 703 and the semiconductor chip 705 are TAB (Tape Automated Bolt).
It is considered that the thickness per layer can be reduced by connecting using the nding) technique. If the thickness can be further reduced, the radius of the solder ball 706 connecting the layers can be reduced, and the area required for signal input / output from the module can be reduced, so that the size of the entire module can be reduced. The insulating film 701 has a device hole 707 necessary for the TAB connection, and a via hole 709 for connecting the wiring 702 and the solder ball 706.

However, the structure shown in FIG. 6 has the following problem as described with reference to FIG.

[0005] First, when the layer interval is reduced, the back surface of the semiconductor chip 705 comes into contact with the lower inner lead 708, so that the inner lead 708 may be electrically short-circuited. Even if the vertical relationship between the wiring 702, the inner leads 703, and the insulating film 701 is reversed, since the opening size of the device hole 707 is usually larger than the semiconductor chip 705, the inner leads 708
Is inevitable. In order to prevent this short circuit, a spacer like the lid 604 in FIG. 6 is required between the semiconductor chip 705 and the inner lead 708.
The introduction of spacers prevents thinning of the module.

Second, since the thermal expansion coefficient of the insulating film 701 is large, the stress applied to the solder ball 706 increases, and the life of interlayer connection is shortened.

[0007] Third, there is no standard for aligning the film carrier with the mold used for packaging the module. Since the film is a flexible material, it is necessary to secure rigidity by packaging to improve the handling of the module. At the time of packaging, the film carrier laminate is set in a mold, but since there is no standard for aligning the two, there is no accuracy in the package outer dimensions.

Fourth, the increase in the number of pins of the module and the increase in the capacity of the power supply are not compatible. When a large number of signals are input and output from the module, it is desirable that the radius of the signal connection solder balls be small. On the other hand, when the power consumption of the semiconductor chip is large, it is desirable that the radius of the solder ball for power supply connection be large. If a small-radius solder ball and a large-radius solder ball coexist on the film carrier at the same time, the small-radius solder ball cannot be connected between the film carriers due to insufficient solder volume.

A first object of the present invention is to provide a semiconductor module suitable for a three-dimensional stacked mounting structure and a reduction in size and thickness.

A second object of the present invention is to provide a semiconductor module having improved reliability of an interlayer connection.

A third object of the present invention is to provide a semiconductor module in which the accuracy of the package outer dimensions is improved.

A fourth object of the present invention is to provide a three-dimensional semiconductor multi-chip module in which the number of signal pins is increased and the capacity of a power supply is increased.

[0013]

In order to achieve the first object, a wiring 702 and an inner lead 703 are arranged between an insulating film 701 and a surface of a semiconductor chip 705 where input / output pads are provided, and , Device hole 70
7 is shorter than at least one side of the semiconductor chip 705.

In order to achieve the second object, the space between the film carriers, that is, the periphery of the semiconductor chip and the solder balls is filled with a silicon-based resin or an epoxy-based resin having a low elastic modulus.

In order to achieve the third object, at least two guide holes penetrating the insulating film portion are provided in the laminated film carrier.

To achieve the fourth object, a radius R1 of a via hole for signal connection, a radius R2 of a via hole for power supply, a volume V1 of a solder ball for signal connection, and a volume V2 of a solder ball for power supply are provided. In general, V1 / R1 ＾
2 = V2 / R2 ＾ 2.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same reference numerals indicate the same components.

FIG. 1 is a sectional view of a semiconductor module according to a first embodiment of the present invention. 2A and 2B are structural views of the layers and one layer constituting the semiconductor module of FIG. 1, wherein FIG. 2A is a top view and FIG. 2B is a sectional view. In FIG.
Film carrier 102 on which semiconductor chip 101 is mounted
Are stacked, and the semiconductor chip of each layer and the package base 108 of the lowermost layer are connected by the solder balls 107, thereby forming the semiconductor module 100. Wiring (not shown) for connecting the solder ball 107 and the package pin 109 is built in the package base 108. Also, in FIG.
Comprises an inner lead 103, an insulating film 104, and a wiring 106. The portion shown by a dotted line in FIG. 2A is below the insulating film 104. The device hole 110 includes the inner lead 103 and the semiconductor chip 101.
For TAB connection. Via holes 105 are formed in the insulating film 104 and connect the wirings 106 to the solder balls 107 connecting the layers. With the above connection, the package pin 109 is connected to the semiconductor chip 101 via the package base 108, the solder ball 107, the via hole 105, the wiring 106 and the inner lead 103, and supplies power to the semiconductor chip. , Input and output signals.

Hereinafter, a method for manufacturing the semiconductor module 100 will be described.

First, in order to reduce the thickness of the module, the semiconductor chip 101 is polished from the back surface of the chip to a thickness of about 100 μm. Further, TAB connection bumps are mounted on the input / output pads of the semiconductor chip 101. Note that a passivation insulating film is usually formed on the surface of the semiconductor chip 101 except for the vicinity of the TAB connection bumps.

The film carrier 102 is supplied in the form of a TAB tape.
6, inner leads 103 and via holes 105 are formed. As a material of the film carrier, for example, polyimide can be used for an insulating film portion, and copper can be used for a wiring portion and an inner lead portion. The thickness is, for example, about 50 μm for the insulating film part and 20 for the wiring and inner lead part.
３０30 μm. Here, although the size of the device hole 110 is sufficient for the TAB connection, the semiconductor chip 10
It is set smaller than 1 so that the semiconductor chip 101 does not pass through the device hole 110.

Then, the semiconductor chip 101 and the film carrier 102 are connected by TAB. Here, the surface of the semiconductor chip 101 where the input / output pads are located and the film carrier 1
02 and the mounting surface of the inner lead 103 are arranged to face each other. After connecting the semiconductor chip 101 and the film carrier 102, solder balls 107 for interlayer connection are arranged on the via holes 105 and heated to connect the solder balls 107 and the wiring 106. In addition, a solder resist is applied to a portion of the wiring surface of the film carrier 102 that is not connected by soldering. Thus, a basic unit to be laminated on the module is created.

Next, the package base 108 is arranged at the lowermost layer, and the film carrier 102 on which the semiconductor chip 101 is mounted is laminated thereon. It is easy to align the film carriers by using sprocket holes attached to the TAB tape. Then, the entire laminate is reflowed to melt the solder balls and connect the layers. The space between the film carriers, that is, the solder ball 1
07 and the periphery of the semiconductor chip 101 are filled with the resin 111 without gaps and molded, and the laminate is packaged. The material of the resin 111 needs to have a low elastic modulus (for example, 1300 kg / mm ^ 2 or less) and a lower coefficient of thermal expansion than polyimide, which is a material of the insulating film. For example, an epoxy resin, a silicon resin, or a silicon-modified epoxy in which the silicone resin is blended with the epoxy resin as a flexible agent can be used. Finally, the semiconductor module 100 is completed by attaching the package pins 109.

Hereinafter, features of the semiconductor module 100 according to the present embodiment will be described. In the film carrier of each layer, the inner lead is sandwiched between the insulating film and the semiconductor chip, and the device hole is smaller than the semiconductor chip. Therefore, even if the layer interval is reduced, the semiconductor chip only contacts the lower insulating film. It is. Accordingly, since the semiconductor chip and the inner lead do not short-circuit, the layer interval can be reduced until the semiconductor chip and the insulating film come into contact. For example, in the present embodiment, the layer interval can be reduced to about 200 μm, and even if ten semiconductor chips are stacked, the module thickness is only about 2 mm. In addition, in the present embodiment, the number of components is smaller and the cost is lower than in the case where a separate component such as a spacer is used for insulating the inner leads and the semiconductor chip, and the module can be made thinner. . Since the film carrier laminate is molded with a resin having a low coefficient of thermal expansion and a low modulus of elasticity, the stress applied to the solder balls can be reduced, and the life of the interlayer connection can be extended. Furthermore, since all the layers are collectively filled with the resin, the number of processes is smaller and the cost is lower than in the case where the semiconductor chip is sealed for each layer.

FIGS. 3 and 4 show a second embodiment of the present invention. The present embodiment is characterized in that a guide hole is provided in an insulating film portion of a film carrier in order to align a film carrier laminate and a mold. FIG. 3 shows the film carrier 301 supplied in the form of a TAB tape. In the process of laminating the film carriers, the film carriers can be aligned with each other by using the sprocket holes 302 attached to the TAB tape. However, since the sprocket holes are cut off in the resin molding process after the film carrier is laminated, the sprocket holes cannot be used for alignment between the film carrier laminate and the mold. Therefore, the guide hole 30 is provided in the film carrier 301.
3 is empty. The guide hole allows two or more insulating films to penetrate in a place where there is no wiring pattern on the film carrier or a place where it does not conflict with a signal or power supply of the semiconductor chip. FIG. 4 shows an upper mold 401 of a molding die 400.
And a lower mold 402, and a film carrier laminate 403 set in a mold. Film carrier laminate 40
3 has a guide hole 404 similar to that of the film carrier 301.
Is empty, and the lower mold 402 has a film carrier 403.
The guide pins 405 corresponding to the guide holes are provided. The film carrier laminate 403 is aligned with the lower mold 402 by inserting the guide pins 405 into the guide holes 404. Since the guide hole 404 is formed by photolithography or punching when the TAB tape is formed, the position accuracy of the guide hole with respect to the outer shape of the film carrier is high. According to the present embodiment, the guide hole and the mold are aligned and packaged.
The dimensional accuracy of the package outer shape with respect to the film carrier position can be increased.

FIG. 5 shows a third embodiment of the present invention. The present embodiment is characterized in that the via hole radius and the solder ball radius in interlayer connection are changed in size between signal connection and power supply connection. FIG.
(A) shows a state where a solder ball is placed on a via hole, and (B) shows a state after interlayer connection. Via hole 50
Numeral 3 is for signal connection, and its radius is R1. The solder ball 504 is for signal connection, and its volume is set to V1. On the other hand, the via hole 501 is for power connection, and its radius is R2. The solder ball 502 is for power supply connection, and its volume is set to V2. By reducing R1, a semiconductor module corresponding to a large number of signal pins can be provided. Further, by increasing R2, the power supply wiring can be strengthened, and a semiconductor module capable of mounting a large number of semiconductor chips with large power consumption can be provided. However, when the power supply line and the signal line are connected using the same size solder balls, the heights of the solder joints after the lamination of the film carrier are different due to different via hole radii. Therefore, R1, V1, R2, V
Between two,

[0027]

(Equation 1)

R 1, V 1,
Set R2 and V2. Then, as shown in FIG.
Even with connections having different via hole radii, the height of the solder joints can be substantially the same. For example, if the radius R1 of the via hole for signal connection is 150 μm and the radius R2 of the via hole for power supply connection is 300 μm, and a layer interval of 200 μm is connected, a radius of about 1 μm is required for the signal connection.
A solder ball having a radius of about 240 μm is used for connection to a power supply of 50 μm. According to the present embodiment, it is possible to provide a semiconductor module in which the number of signal lines is increased and the power supply lines are strengthened.

[0029]

According to the first aspect of the present invention, since the semiconductor chip comes into contact with the insulating film, the inner leads are not short-circuited. In addition, the number of parts is smaller and the cost can be reduced, and the module can be made thinner than in the case where a separate part such as a lid is used.

According to the second means of the present invention, since the stress applied to the solder ball can be reduced, the life of the interlayer connection can be extended. Further, since all the layers are collectively filled with the resin, the number of processes is smaller and the cost is lower than in the case where the semiconductor chip is sealed for each layer.

According to the third means of the present invention, since the alignment accuracy between the film carrier laminate and the mold is improved, the external dimensions of the package can be improved.

According to the fourth aspect of the present invention, since the thickness of the interlayer connection can be made the same regardless of the diameter of the via hole, it is possible to increase the number of signal pins and strengthen the power supply line.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a semiconductor module according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a part of the semiconductor module according to the first embodiment of the present invention;

FIG. 3 is a diagram illustrating a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a third embodiment of the present invention.

FIG. 6 is a diagram illustrating a conventional technique.

FIG. 7 is a structural diagram of a semiconductor module which is further reduced in thickness and size based on a conventional technique.

[Explanation of symbols]

 100 semiconductor module 101, 602, 705 semiconductor chip 102, 301, 704 film carrier 103, 703, 708 inner lead 104, 701 insulating film 106, 702 Wiring 105, 501, 503, 709: Via holes 110, 707: Device holes 107, 502, 504, 706: Solder balls 108: Package base 109: Package pins 111: Resin 302: Sprocket holes 303, 404: Guide holes 400: Mold die 401: Upper die 402: Lower die 403: Film carrier laminate 405: Guide pins 601 and 606 ... Wiring board 603 ... Wire 604 ... Lid 605 ...・ Soldering.

Claims (4)

[Claims] 1. A semiconductor module comprising at least one film carrier on which a semiconductor chip is mounted,
An input / output pad is provided on the surface of the semiconductor chip, and the film carrier includes an insulating film, wiring formed on the surface of the insulating film, and a device hole corresponding to the semiconductor chip which is a part of the wiring. An inner lead extending inward and connected to the input / output pad; a surface of the insulating film and a surface of the semiconductor chip facing each other; at least one side of the device hole being at least one side of the semiconductor chip; A semiconductor module characterized by being shortened. 2. The semiconductor module according to claim 1, wherein a silicon-based resin or an epoxy-based resin having a low elastic modulus is filled between the film carriers. 3. The semiconductor module according to claim 2, wherein said film carrier is provided with at least two guide holes passing through said insulating film portion. 4. A three-dimensional semiconductor multi-chip module in which film carriers each having a semiconductor chip mounted thereon are stacked and connected to each other, the via holes being formed in the film carrier and the solder balls connected to the via holes. Connecting between film carriers, via hole radius R1 for signal connection and via hole radius R2 for power supply connection
Between the solder ball volume V1 for signal connection and the solder ball volume V2 for power connection, approximately V1 / R1 ＾ 2 = V2 /
A three-dimensional semiconductor multi-chip module having a relationship of R2 ＾ 2.