JPH1022298A - Semiconductor device and production of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the parasitic capacitance between the drain electrodes and gate electrodes of adjacent FETs by integrating the low-resistance layer of gate electrode of one FET with the electrode connected to the source region or drain region of the other adjacent FET. SOLUTION: An epitaxial layer 2 is constituted by successively forming an undope buffer layer 2a, p-type buried layer 2b and n-type channel layer 2c on a semiconductor wafer 1. A heat-resistant layer 3a of a gate electrode 3 is formed on the channel layer 2c of the epitaxial layer 2 and on the heat- resistant layer, a low-resistance layer 3b is formed. Then, Si ions of Si are implanted while using the heat-resistant layer 3a of that gate electrode 3 as a mask, and (n) layers 4a to become sources and drains 4 of FET are formed so as to be adjacent. Thus, the parasitic capacitance between the drain electrodes and gate electrodes of adjacent FET can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a technique effective when applied to a high-speed semiconductor device using a compound semiconductor.

[0002]

2. Description of the Related Art In a semiconductor device which operates at a high speed, such as a Schottky gate type field effect transistor (MESFET) using a compound semiconductor, reduction of parasitic resistance is an important point of performance improvement. Therefore, in order to reduce the parasitic resistance, a technique of selectively forming a high-concentration n + layer by self-alignment in which ion implantation is performed using a heat-resistant gate electrode as a mask has been conventionally used.

In such a self-alignment process, since the gate electrode used as a mask needs to be heat-treated later, it is thermally stable even if the specific resistance is high.
W, inevitably using a material such as WSi _X, a low resistivity material such as Al can not be used for thermally unstable.

For this reason, as the gate length is reduced for the purpose of improving the performance of the FET, such as an increase in the high-frequency gain, the gate height is subject to process restrictions in accordance with the gate length. When the gate length becomes submicron, the gate electrode has a high resistance, which impairs the high speed operation of the device.

Therefore, a method is known in which after the heat treatment, a low-resistance metal is further laminated on the heat-resistant gate to reduce the gate resistance.

[0006]

However, the above method has the following problems.

In a field effect transistor having a conventional structure, for example, when the drain electrode and the gate electrode of two transistors adjacent to each other on an integrated circuit, such as an output transistor of a differential circuit, are connected, the end of the gate electrode An insulating film is formed on the provided pad, and both are electrically connected through a through hole.

With respect to such a semiconductor device, the inventors of the present invention have provided a drain electrode of an output transistor of a differential circuit,
The speed characteristics of the integrated circuit were analyzed with respect to the parasitic capacitance between the transistor and the gate electrode of the next transistor. As a result, the effect of the parasitic capacitance between the drain electrode and the gate electrode on the operation speed of the circuit was extremely large. It has been found that the parasitic capacitance in this portion needs to be minimized.

Another problem of the prior art is that the process of manufacturing a semiconductor device is complicated due to the complicated wiring structure. In particular, the process of stacking a metal on a gate to reduce the gate resistance is complicated, which causes a decrease in yield and an increase in cost.

An object of the present invention is to solve the above problems, to provide a technique capable of reducing the parasitic capacitance between the drain electrode and the gate electrode between adjacent FETs and simplifying the configuration of a semiconductor device. Is to do.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

Means for Solving the Problems Among the inventions disclosed in the present application, the outline of typical inventions will be briefly described.
It is as follows.

According to the present invention, the present invention relates to a gate electrode of an FET constituted by a heat-resistant layer and a low-resistance layer superposed on the heat-resistant layer. And an electrode connected to the source region or the drain region of the FET described above are integrally formed in the same layer.

According to the above-described means, the low-resistance layer of the gate electrode of the field-effect transistor constituting the circuit and the source-drain electrode of the adjacent field-effect transistor are formed of the same layer, thereby increasing the distance between the two transistors. Since the parasitic capacitance between the two transistors can be reduced by making the distances as close as possible, a high-speed circuit can be achieved.

Further, since the configuration of the semiconductor device can be simplified, the yield can be improved and the cost can be reduced.

Hereinafter, embodiments of the present invention will be described.

In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG. 1 is a plan view showing a main part of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a view taken along line AA in FIG. FIG. 3 is a vertical sectional view taken along line BB in FIG.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate using semi-insulating GaAs, and 2 denotes an epitaxial layer formed on the semiconductor substrate 1 and formed in a mesa shape for element isolation. An undoped buffer layer 2a is 300 nm on a semiconductor substrate 1, a P-type buried layer 2b doped with 3 × 10 ¹⁶ Be is 300 nm, and Si is 4 × 1.
An ^18- doped n-type channel layer 2c is laminated to a thickness of 15 nm.

Reference numeral 3 denotes a gate electrode formed on the channel layer 2c.
It is formed to a thickness of 700 nm to 00 nm, on which a low resistance layer 3b is laminated. Heat-resistant layer 3 of this gate electrode 3
Using a as a mask, ion implantation of Si is performed to form an n-layer 4a to be the source and drain 4.

Reference numeral 5 denotes a side wall insulating film formed by anisotropically processing the silicon oxide film. Using the side wall insulating film 5 and the heat-resistant layer 3a as a mask, a high concentration of about 5 × 10 ¹³ / cm ^2. After the implantation of the Si ions, annealing is performed to form an n + layer 4b serving as the source and drain 4.

Reference numeral 4c denotes an n + layer which is newly formed after partially removing the epitaxial layer 2 in order to reduce the resistance between the source and the drain. The source / drain formed on the n + layer 4c In the present invention, the ohmic electrode 6 and the low resistance layer 3b of the gate electrode 3 are, for example, Au /
It is integrally formed by a metal layer made of Ni / AuGe.

In the semiconductor device of the present invention, the ohmic electrode 6 of the source and the drain and the low resistance layer 3b of the gate electrode 3 are formed by the same layer as compared with the conventional semiconductor device similarly shown in FIGS. Therefore, there is no need to connect the low-resistance layer 3b and the ohmic electrode 6 via the through hole formed in the interlayer insulating film 7 as in the conventional case. For this reason, the configuration of the semiconductor device is simplified, a space for forming the through hole 10 is not required, and the interval between the transistors can be reduced.

Next, a method of manufacturing the semiconductor device will be described with reference to FIGS.

First, on a semi-insulating GaAs semiconductor substrate 1 by MBE (Molecular Beam Epitaxy).
The epitaxial layer 2 is grown. Epitaxial layer 2
As, for example, after the undoped buffer layer 2a is 300nm grown on the semiconductor substrate 1, 3 Be × 10 ¹⁶
The doped p-type buried layer 2b is 300 nm, and the Si is 4 ×
Each of the n-type channel layers 2c doped with 10 ^{18 is} grown to a thickness of 15 nm.

The epitaxial layer 2 is subjected to mesa etching for element isolation except for a part where an element is formed.

Next, a WSi film is deposited to a thickness of 700 nm and is patterned by dry etching to form a heat-resistant layer 3a of the gate electrode 3 on the channel layer, for example, with a gate length of 300 nm. Using this heat-resistant layer 3a as a mask, ion implantation of Si is performed to form an n-layer 4a. This state is shown in FIG.

Next, a silicon oxide film is deposited on the entire surface by a plasma CVD method, the silicon oxide film is anisotropically processed by dry etching, and a side wall insulating film 5 is formed on the side wall of the heat resistant layer 3a. Using the sidewall insulating film 5 and the heat-resistant layer 3a as a mask, high-concentration Si ions of about 5 × 10 ¹³ / cm ² are implanted, followed by annealing to form an n + layer 4b. This state is shown in FIG.

Next, in order to reduce the resistance between the source and the drain 4, the epitaxial layer is partially removed, and the removed portion is subjected to metal organic chemical vapor deposition (MOCVD).
Is used to selectively grow the n + layer 4c. This state is shown in FIG.

Next, an interlayer insulating film 7 made of silicon oxide is deposited to a thickness of 200 nm by a plasma CVD method, and the n + layer 4c of the source and drain 4 and the heat-resistant layer 3a of the gate electrode 3 are formed using a resist mask 8 formed by photolithography. Open the top. This state is shown in FIG.

Next, a metal film 9 made of Au / Ni / AuGe is deposited on the entire surface by vacuum evaporation. This state is shown in FIG.

After that, the resist mask 8 and the unnecessary metal film 9 deposited on the resist mask 8 are removed,
The metal film 9 is alloyed to form the low resistance layer 3b and the ohmic electrode 6 for 5 minutes. In this manner, as shown in FIGS. 1 to 3, the low-resistance layer 3b of the gate electrode 3 and the ohmic electrodes 6 of the source and drain 4 are integrally formed by the same process.

In the conventional manufacturing method, the steps up to the steps shown in FIGS. 7 to 9 are the same, but thereafter, as shown in FIG. 12, the metal film 9 to be the low resistance layer 3b of the gate electrode 3 is formed by patterning. Then, as shown in FIG. 13, the metal film 11 to be the ohmic electrode 6 must be formed by patterning. In the present invention, the low-resistance layer 3b and the ohmic electrodes 6 of the source and drain 4 are formed by the same process. It can be formed.

(Embodiment 2) Next, a method for manufacturing a semiconductor device according to another embodiment of the present invention will be described with reference to FIGS. 7 to 9 and FIGS.

In this embodiment, the steps up to the steps shown in FIGS. 7 to 9 are the same as those of the above-described embodiment, but thereafter, the interlayer insulating film 7 made of silicon oxide is formed by the plasma CVD method. Is deposited to a thickness of 700 nm thicker than in the embodiment described above, and a photoresist is further applied thereon to a thickness of about 1.6 μm for planarization, and the interlayer insulating film 7 is etched by dry etching (RIE) to expose the head of the heat-resistant layer 3a. Next, the source and drain 4 are opened, and Au / Ni /
A metal film 9 made of AuGe is deposited on the entire surface by vacuum evaporation. This state is shown in FIG.

Next, the metal film 9 is processed into a predetermined shape of the low resistance layer 3b and the ohmic electrode 6 by ion milling. Thereafter, a heat treatment is performed at 400 ° C. for 5 minutes to form a metal film 9.
Is alloyed to form the low resistance layer 3b and the ohmic electrode 6. This state is shown in FIG. Thus, the low-resistance layer 3b of the gate electrode 3 and the ohmic electrodes 6 of the source and drain 4 are simultaneously formed.

In the present embodiment, the low-resistance layer can be finely processed by ion milling, and the source and drain regions can be flattened.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

[0039]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, there is an effect that the low resistance layer of the gate electrode and the source / drain electrode of the field effect transistor constituting the circuit can be formed by the same layer.

(2) According to the present invention, the effect (1) is that the parasitic capacitance between the two transistors can be reduced by minimizing the distance between the two transistors.

(3) According to the present invention, the effect (2) has an effect that a high-speed circuit can be achieved.

(4) According to the present invention, the effect (1) has an effect that the configuration of the semiconductor device can be simplified.

(5) According to the present invention, there is an effect that the yield is improved by the effect (4).

(6) According to the present invention, there is an effect that the cost can be reduced by the effect (4).

[Brief description of the drawings]

FIG. 1 is a plan view showing a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a longitudinal sectional view taken along line AA in FIG.

FIG. 3 is a longitudinal sectional view taken along line BB in FIG.

FIG. 4 is a plan view showing a main part of a conventional semiconductor device.

FIG. 5 is a longitudinal sectional view taken along line AA in FIG.

FIG. 6 is a longitudinal sectional view taken along line BB in FIG.

FIG. 7 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 8 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 9 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 10 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 11 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 12 is a longitudinal sectional view showing a main part of a conventional semiconductor device for each process.

FIG. 13 is a longitudinal sectional view showing a main part of a conventional semiconductor device for each process.

FIG. 14 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention for each step.

FIG. 15 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention for each step.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Epitaxial layer, 2a ... Buffer layer, 2b ... Buried layer, 2c ... Channel layer, 3 ... Gate electrode, 3a ... Heat-resistant layer, 3b ... Low resistance layer, 4 ... Source, drain, 4a ... , N layers, 4b, 4c... N + layers, 5... Sidewall insulating films, 6... Ohmic electrodes, 7... Interlayer insulating films, 8.

Claims (6)

[Claims] 1. A semiconductor device having an FET in which a gate electrode is constituted by a heat-resistant layer formed on a main surface of a semiconductor substrate and a low-resistance layer superposed on the heat-resistant layer, wherein the gate electrode of one FET is A low-resistance layer and an electrode connected to a source region or a drain region of another adjacent FET are integrated with each other. 2. The semiconductor device according to claim 1, wherein said semiconductor substrate is a compound semiconductor crystal substrate. 3. The method according to claim 1, wherein the compound semiconductor is at least GaAs.
3. The semiconductor device according to claim 2, comprising at least one of s, InGaAs, and AlGaAs. 4. A method for manufacturing a semiconductor device having an FET in which a gate electrode is constituted by a heat-resistant layer formed on a main surface of a semiconductor substrate and a low-resistance layer overlaid on the heat-resistant layer, A method for manufacturing a semiconductor device, wherein a low resistance layer of the gate electrode and an electrode connected to a source region or a drain region of another adjacent FET are formed using the same material and in the same process. 5. The method according to claim 4, wherein the semiconductor substrate is a compound semiconductor crystal substrate. 6. The method according to claim 1, wherein the compound semiconductor is at least GaAs.
6. The method according to claim 5, wherein the method includes one or more of s, InGaAs, and AlGaAs.