JPH1022297A - Semiconductor device and production of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use a metal layer as a control gate electrode by sticking 1st and 2nd wafers, fusing welding them together so as to sandwich the metal layer between the 1st wafer and the 2nd wafer. SOLUTION: In the 1st and 2nd silicon wafers 1 and 3, their one sides are oxidized, that 1st silicon wafer 1 is formed of a silicon layer 5 having an SiO2 layer 7, and the 2nd silicon wafer 3 is formed of a silicon layer 9 having an SiO2 layer 11. Then, a metal layer 13 is formed on the SiO2 layer 11 of the 2nd wafer 3 and patterned into desired form, the SiO2 layers 7 and 11 of two 1st and 2nd silicone wafers 1 and 3 are heated and pressed, and the SiO2 layers 7 and 11 of the respective wafers 1 and 3 are melted so that the patterned metal layer 13 can be overlaid. Thus, the metal layer 13 can be used as the control gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor and a semiconductor device manufactured by the method.

[0002]

BACKGROUND OF THE INVENTION Many semiconductor devices can be made very small or operate more efficiently when a metal gate electrode is embedded in a stacked semiconductor layer structure. . It is known to utilize buried interconnect layers for devices in semiconductor arrays on a single wafer, for example, for more efficient connection of power lines, but to grow layers above the metal This technique is difficult, and in practice, this technique does not help in the manufacture of individual buried control gate electrodes.

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of forming a metal layer, for example, a method of manufacturing a semiconductor device using this metal layer as a control gate electrode, and a semiconductor device. To provide.

[0004]

According to the present invention, the following means have been taken in order to solve the above-mentioned problems. In the method for manufacturing a semiconductor according to the present invention, a metal layer is formed on a first wafer, and the first wafer and the second wafer are sandwiched between the first wafer and the second wafer. The second wafer is bonded and melt-bonded.

[0005] In the method of the present invention, preferred embodiments are as follows. (1) The metal layer is patterned before the first and second wafers are bonded and melt-bonded.

(2) The first and second wafers are melt-bonded by applying heat and pressure. (3) The first and second wafers each include silicon and at least one oxidized surface.

(4) The metal layer is formed on the oxidized surface of the first wafer, and the oxidized surface of the second wafer is melt-bonded to the surface on which the metal layer is formed. (5) The wafer comprises GaAs.

As mentioned above, in the method of the present invention, if the metal functions as one or more individual gate electrodes along with the signal wiring for the same, the metal layer is fused to the wafers. It must be patterned before. Usually, the bonding of two wafers by melting is performed by applying heat and pressure.

[0009] One or more shapes of semiconductor materials are susceptible to this technology. However, a particularly preferred material is silicon which has been oxidized on at least one side to form SiO ₂ . At least one surface of each of the two silicon wafers was oxidized, and a metal layer was deposited thereon and, if necessary, patterned, the oxidized surface of the other wafer had metal deposited thereon. It can be melt-bonded to the oxidized surface of the first silicon wafer.

A semiconductor device according to the present invention comprises at least one metal control gate electrode, wherein the metal control gate electrode is sandwiched between two semiconductor wafers that are melt-bonded to each other. Preferred embodiments of the semiconductor device of the present invention are as follows.

(1) The metal control gate electrode is a gate of a field effect transistor. (2) The metal control gate electrode is a back gate embedded in a patterned wafer having an etching side surface on which the regrown structure is formed.

(3) The regrown structure is covered with a front gate electrode. (4) A field effect transistor is provided, and at least one
Having two buried gate electrodes.

(5) The gate electrodes in adjacent layers of the transistor are not arranged on each other. The present invention is very useful for manufacturing a field effect transistor. Thus, the metal control gate electrode of the device according to the invention can be, for example, a field-effect transistor (FE)
The gate electrode of T) may be used. This makes it possible to easily manufacture a stacked layer of the FET. The gate electrodes of the device within each layer can be staggered with respect to any adjacent layers to minimize stray field effects.

The technique of the present invention is appropriate for a type of semiconductor device where the stack layer is patterned to form a mesa-type structure covered by one or more layers by a regrowth technique. The control gate electrode can be embedded in the stack layer of the mesa structure and provides better control of the carriers flowing through the regrown structure, which is usually dominated by a front gate overlying the regrown layer. Is controlled.

[0015]

Embodiments of the present invention will be described with reference to the drawings. The basic semiconductor manufacturing method of the present invention will be described in detail with reference to FIGS.

As shown in FIG. 1, the first and second silicon wafers 1 and 3 are oxidized on one side, and the first silicon wafer 1 is composed of a silicon layer 5 having an SiO ₂ layer 7, Is composed of a silicon layer 9 having an SiO ₂ layer 11.

The metal layer 13 is deposited on the SiO ₂ layer 7 of the first silicon wafer 1 and patterned into a desired shape. Next, as shown in FIG. 2, the SiO ₂ layers 7 and 11 of the _two wafers 1 and 3 are heated and pressurized, and the SiO ₂ layers of the respective wafers 1 and 3 are melted,
Cover the patterned metal layer 13.

FIG. 3 shows an example in which the above basic technique is applied to the stacked FET structure 15. First p ^- silicon wafer 17 is oxidized on its upper surface 19 and lower surface 21. The second p ^- silicon wafer 23 is oxidized on its upper surface 25 and lower surface 27, like the first p ^- silicon wafer 17. Therefore, the first wafer has a p ⁻ layer composed of the upper SiO ₂ layer 19 and the lower SiO ₂ layer 21.
The second wafer comprises a p ^- layer 23 sandwiched between an upper SiO ₂ layer 25 and a lower SiO ₂ layer 27.

Here, one or more gate electrodes 2
9 are formed by deposition and patterning of the metal on the upper SiO ₂ layer of the first wafer. Similarly, the gate electrodes 31, 33, etc. are formed on the upper SiO 2 of the second wafer.
Formed on _two layers. The two wafers are now fused and bonded by applying appropriate heat and pressure to bring the lower SiO ₂ layer 21 of the first wafer and the upper SiO ₂ layer 25 of the second wafer together. In this method, the metal gate electrodes 31, 33, etc. on the second wafer are embedded in the structure. It can also be seen that any desired number of gate electrodes and devices can be arranged in a single plane and in any desired number of planes stacked in this manner. For simplicity, the wiring to the gate electrode is not shown, and the formation of ohmic contacts acting as the source and drain is not shown, but the means for producing this is obvious to those skilled in the art, and so description and illustration are omitted. .

As described above, in the apparatus shown in FIG.
It can be seen that the upper SiO ₂ layer 19 of the wafer forms a gate insulating layer for the first transistor having a conduction channel formed by the p ⁻ layer 17 below the metal gate electrode 29. At the next level down, the upper Si
The O ₂ layer 25 behaves as a gate insulating layer for the metal gate electrodes 31 and 33, and the p ^- silicon layer behaves as a respective lower conductive channel, where the respective source and source (not shown) on either side of each gate electrode. Two lower transistors with drains are configured.

FIG. 4 is a diagram showing another embodiment of the present invention. The device 39 comprises a mesa-shaped structure 37 formed by a plurality of layers, and these layers selectively
9 and 41 are etched so as to be exposed.
Any suitable structure may be a mesa-type structure, eg, HEMT4
3 by regrowth. The HEMT 43 represents a “high electron mobility transistor” and is one of the structures well known to those skilled in the art, where high mobility carriers are trapped in a single plane close to the interface of two different semiconductor materials. It consists of layers of different band gaps as possible. This is always covered with the front gate 45. To control the carriers in the HEMT structure, upper and lower gate electrodes 47,
Forty-nine buried metals are added to the mesa structure. The metal gate electrode is confined within the layer in a manner similar to transistor fabrication, as described with reference to FIG. The lower wafer 49 is made of an oxidized silicon layer on one surface and has an upper SiO ₂ layer 53. The intermediate wafer 55 has a silicon layer which is oxidized on both sides and is sandwiched between a lower SiO ₂ layer 59 and an upper SiO ₂ layer 61. Similarly, the top wafer is oxidized on one side and has a silicon layer 65 and a SiO ₂ layer 67.

The lower back gate electrode 49 is manufactured by depositing and patterning a metal on the SiO ₂ layer 53 of the lower wafer 49. Above this is a lower SiO ₂ layer 5 which is in contact with the upper SiO ₂ layer 53 of the lower wafer.
9 is disposed. Prior to this, the upper metal of the back gate electrode 47 is
5 by deposition and patterning of metal on the upper SiO ₂ layer 61.

An upper wafer having an SiO ₂ layer 67 that contacts the upper SiO ₂ layer 63 of the intermediate wafer 55 is disposed above the intermediate wafer. Here, by applying pressure and heat, as described above, the metal gate electrode 47,
Lock in 49. Therefore, the multilayer structure is formed by etching the mesa and the HEMT structure 43 and,
The front gate 45 is formed by regrowth. This basic type of structure is suitable for a very wide variety of devices with so-called quantum effects. The present invention is not limited to the above embodiments of the present invention, and it is needless to say that various modifications can be made without departing from the spirit of the present invention.

[0024]

According to the present invention, the following effects can be obtained. As described above, the present invention is very useful for manufacturing a field effect transistor, and the metal control gate electrode of the device according to the present invention is, for example, a field effect transistor (FE).
The gate electrode of T) may be used, and the stack type layer of the FET can be easily manufactured. Also, the gate electrodes of the device in each layer can be staggered with respect to any adjacent layers to minimize stray field effects.

[Brief description of the drawings]

FIG. 1 is a diagram showing a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is another view showing the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a diagram showing an example in which the present invention is applied to a stacked FET structure.

FIG. 4 is a diagram showing another method for manufacturing the semiconductor device of the present invention.

[Explanation of symbols]

1 ... first silicon wafer 3 ... second silicon wafer 5 ... silicon layer 7 ... SiO ₂ layer 9 ... silicon layer 11 ... SiO ₂ layer 13 ... metal layer 15 ... stacked FET structure 17 ... first p ^- silicon Wafer 19: Upper surface (upper SiO ₂ layer) 21: Lower surface (lower SiO ₂ layer) 23: Second p ^- silicon wafer 25: Upper surface (upper SiO ₂ layer) 27: Lower surface (lower SiO ₂ layer) 29, 31, 33 ... gate electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication H01L 29/786

Claims (2)

[Claims] A first metal layer formed on the first wafer and the first wafer and the second wafer sandwiching the metal layer between the first wafer and the second wafer; And a method for manufacturing a semiconductor device, comprising: 2. A semiconductor device, comprising: at least one metal control gate electrode, wherein the metal control gate electrode is sandwiched between two semiconductor wafers that are melt-bonded to each other.