GB2301707A - Method of forming a semi-conductor device having conductors between fused wafers - Google Patents

Method of forming a semi-conductor device having conductors between fused wafers Download PDF

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Publication number
GB2301707A
GB2301707A GB9511156A GB9511156A GB2301707A GB 2301707 A GB2301707 A GB 2301707A GB 9511156 A GB9511156 A GB 9511156A GB 9511156 A GB9511156 A GB 9511156A GB 2301707 A GB2301707 A GB 2301707A
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wafer
metal
wafers
conductor
gate electrode
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GB2301707B (en
GB9511156D0 (en
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Jeremy Henley Burroughes
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Toshiba Europe Ltd
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Toshiba Cambridge Research Centre Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A method of fabricating a semiconductor device comprising forming a conductor 13 at the surface of a first wafer 3 and fusing the surface of the first wafer 3 with a second wafer 1. The metal layer is thus sandwiched between the wafers. The method is suited to manufacture of semiconductor devices having control gate electrodes buried by being trapped between two such fused wafers. The conductor may be formed of metal deposited on the wafer surface or a heavily doped region formed in the wafer surface (Figs 5-6, not shown). The metal conductor may also have a thicker layer of oxide formed around it (Figs. 7-8, not shown). The method is suitable for producing stacked FET structures.

Description

SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME The present invention relates to a method of fabricating a semiconductor device and to a device made by that method. Many forms of semiconductor device could be made with a greater degree of miniaturisation or be made to operate more efficiently if metal gate electrodes could be buried within a stacked semiconductor layer structure. Although it is known to utilise buried wiring layers for, e. g. more efficient connection of power supply lines to devices in a semiconductor array on a single wafer, the technique for growing layers on top of the metal is difficult and does not really lend itself to fabrication of discrete buried control gate electrodes.
A new method of fabricating a semiconductor device which enables metal layers, for example for use as control gate electrodes, to be readily produced. Thus, a first aspect of the present invention provides a method of fabricating a semiconductor device, the method comprising forming a conductor at a first surface of a first wafer and fusing a second wafer with the said surface of the first wafer. In this way, the conductor becomes burried between the two wafers.
The conductor material may simply be a metal. This can be deposited on the surface of the first wafer, which surface is to be fused with the second wafer.
However, if the metal is intended to function as one or more discrete gate electrodes together with signal wiring to same, the metal layer needs to be patterned before the wafers are fused together.
The use of metal as the conductor may, however, not be the most preferred conductor material because of its lack of compatibility with the wafer material. More specifically, it can be difficult to bond two wafers together by fusing if one has metal on its surface to be bonded, especially if the metal is proud of the wafer.
Therefore, two other variants are also described herein.
In the first variant, at least one region of a surface of the first wafer is very heavily doped, eg by ion implantation or diffusion Either p-type or n-type impurities may be used but one or other may be preferred depending on the particular structure being fabricated.
In order to obtain a sufficiently high conductivity, it is preferred that the impurity concentration should be from 10 cm to 1 21cm3, more especially from 1019cm to 10 3.
As described in one preferred embodiment of this first variant, after implantation into a silicon substrate, the wafer is annealed to activate the dopant. Then, an oxide layer is formed over the implanted surface prior to fusing with the second wafer.
A second variant entails use of a heavily doped semiconductor such as silicon (e.g. poly-n Si) or a metal compound as the conductor, more particularly, a metal compound which is compatible with the first wafer. The metal compound could be a metal silicide, such as tungsten silicide.
In a preferred embodiment of the second variant, the surface of the first wafer is oxidized prior to deposition of a metal silicide. Then, a silicon dioxide film is formed over the same surface. The silicide film may be patterned prior to formation of the oxide films.
The wafers may be formed of any semiconductor-type material but a particularly preferred material is silicon. For some devices of interest, at least one surface of the first wafer has an upper silicon dioxide surface. This surface can be fused with another oxide film on the surface of a second silicon layer. In this way, the conductor is embedded in an SiO2 insulating layer.
Thus, if two silicon wafers are oxidized on at least one surface and then the conductor is in the form of a metal layer deposited on one oxidized surface, patterned as necessary, the oxidized surface of the other wafer can then be fused to the oxidized surface of the first silicon wafer having the metal thereon.
In addition to silicon, other semiconductor materials are susceptible to this basic technique, for example InP or GaAs.
The method of the present invention leads to production of devices which themselves, constitute a second aspect of the present invention which provides a semiconductor device comprising at least one control gate electrode, the control gate electrode being formed of a conductor sandwiched between two semiconductor wafers which are fused together. The conductor material may, for example, be of any kind described in the context of the first aspect of the invention.
The method of the present invention is very useful for fabrication of field effect transistors. Thus, the metal control gate electrode of the device according to the present invention may be the gate electrode of such a field effect transistor (FET). Thus, it becomes possible to fabricate stacked layers of FETs. The gate electrodes of the devices in each layer can be arranged to be staggered with respect to those of any adjacent layer to minimise stray field effects.
The technique of the present invention is also very suited to the kind of device wherein a stacked layer structure is patterned to form a Mesa-type structure which is then covered with one or more further layers by a regrowth technique. Control gate electrodes can be buried in the stacked layers of the Mesa-type structure to give better control of carriers flowing within the regrowth structure, which usually are primarily controlled by a front gate overlying the regrowth layers.
The present invention will now be explained in more detail by reference to the following description of preferred embodiments and with reference to the accompanying drawings, in which: Figure 1 shows a pair of wafers in preparation for execution of a first embodiment of a method according to the present invention; Figure 2 shows completion of the first embodiment of the method according to the present invention, using the two wafers shown in Figure 1; Figure 3 shows the arrangement of gate electrodes of FETs in a stacked structure formed in accordance with the present invention; Figure 4 shows a patterned wafer/regrowth structure with buried control gate (back) electrodes and formed in accordance with the present invention; Figures 5 and 6 show a second embodiment of a method according to the present invention; and Figures 7 and 8 show a third embodiment of a method according to the present invention.
The basic method of the present invention will now be explained by a description of a first embodiment thereof, and specifically with reference to Figures 1 and 2. First, as shown in Figure 1, a pair of silicon wafers 1 and 3 are oxidized on one surface thereof, so that each respectively consists of a base silicon layer 5 with a surface SiO2 layer 7 for the first wafer 1 and likewise, another base silicon layer 9 with surface SiO2 layer 11.
A metal layer 13 is then deposited on the SiO2 layer 11 of the first wafer 3 and patterned to a desired configuration. Next, as shown in Figure 2, the two SiO2 layers 7, 11 of the wafers 1, 3 are pressed together under application of heat to fuse the SiO2 layers of each wafer together, thus burying the patterned metal 13.
Application of this basic technique to a stacked FET structure 15 is shown in Figure 3. A first p silicon wafer 17 is oxidized on its upper surface 19 and lower surface 21. A second p silicon wafer 23 is likewise oxidized on its upper surface 25 and lower surface 27.
Thus, a first wafer comprises a p layer with upper SiO2 layer 19 and lower SiO2 layer 21 and the second wafer consists of a p layer 23 sandwiched between an upper SiO2 layer 25 and lower SiO2 layer 27.
Then, one or more gate electrodes 29, etc. are formed by deposition and patterning of metal on the upper SiO2 layer 29 of the first wafer. Similarly, gate electrodes 31, 33, etc. are formed on the upper SiO2 layer 25 of the second wafer. The two wafers are then fused together by bringing together the lower SiO2 layer 21 of the first wafer with the upper SiO2 layer 25 of the second wafer, with application of appropriate heat and pressure. In this way, the metal gate electrodes 31, 33, etc. on the second wafer are buried within the structure. It will be appreciated that any desired number of gate electrodes/devices can be arranged in a single plane and with any desired number of planes stacked in this way.For simplicity, the wiring to the gate electrodes is not shown, nor is formation of the ohmic contacts acting as source and drain, although the means of effecting this will be readily apparent to persons skilled in the art.
Thus, it can be noted that with the device in Figure 3, the upper SiO2 layer 19 of the first wafer forms the gate insulation layer for a first transistor which has a conduction channel formed by the p layer 17, below the metal gate electrode 29. In the next level down, the upper SiO2 layer 25 acts as the gate insulation layer for the metal gate electrodes 31 and 33 and the p silicon layer acts as conduction channel below each, thus constituting two lower transistors with respective sources and drains (not shown) on either side of each gate electrode.
Figure 4 shows an alternative possible application of the technique of the present invention. This device 35 consists of a Mesa-like structure 37 formed by a plurality of layers which are selectively etched to expose oblique facets 39, 41, etc. Any suitable structure can be formed by regrowth over this Mesa-like structure, for example a HEMT 43 (HEMT stands for "high electron mobility transistor" and is a kind of structure well known in the art which consists of layers of different band gaps in which high mobility carriers can be trapped in a single plane, close to an interface between two different semiconductor materials). This is typically overlaid by a front gate 45. To control carriers within the HEMT structure, buried metal upper and lower gate electrodes 47, 49 are incorporated in the Mesa-like structure.
The metal gate electrodes can be encapsulated in the layers by a method analogous to the production of the transistor as described with reference to Figure 3. A lower wafer 49 consists of a silicon layer 51 oxidized on one surface to have an upper SiO2 layer 53. A middle wafer 55 is oxidized on both surfaces to have a silicon layer 57 sandwiched between a lower SiO2 layer 59 and an upper SiO2 layer 61. Similarly, an upper wafer is oxidized on one surface to comprise a silicon layer 65 and an SiO2 layer 67.
The lower back gate electrode 49 is produced by deposition and patterning of metal on the SiO2 surface 53 of the lower wafer 49. Over this is laid the middle wafer 55 with its lower SiO2 layer 59 in contact with the upper SiO2 layer 53 of the lower wafer.
Previously, the upper metal back gate electrode 47 has been fabricated by deposition and patterning of metal on the upper SiO2 surface 61 of the middle wafer 55.
Over the middle wafer is placed the upper wafer with its SiO2 layer 67 contacting the upper SiO2 layer 63 of the middle wafer 55. Then, application of pressure and heat traps the metal gate electrodes 47, 49 as previously described. This multi-layer structure is then etched to form a Mesa and the HEMT structure 43 and front gate 45 are then formed by regrowth. This basic kind of structure lends itself to a very wide variety of so-called quantum effect devices.
Figures 5 and 6 show a method according to a second embodiment of the present invention. As shown in Figure 5, a mask 71 is formed on one surface 73 of a silicon wafer 75. The mask 71 is formed with an opening 77 therein, corresponding to a predetermined wiring pattern. Impurities (eg n-type) are implanted through the opening 77 to form a heavily doped region 79 with an 20 concentration of about 2 x 1020 -3 impurity concentration of about 2 x 1020 cm- cm Next, as shown in Figure 6, the wafer is annealed and the mask is removed by etching and a portion of the wafer 77 above the heavily doped region 79 is oxidized to form an SiO2 layer 81. The SiO2 can then be fused with an oxide layer such as the layer 7 of the wafer 1 shown in Figure 1. In this way, a conductive region 79 is buried within a stacked layer structure.
In this embodiment, it is not necessary to fuse one wafer with a surface of another wafer on which there is a metallic region.
A third embodiment of a method according to the present invention is shown in Figures 7 and 8. First, as shown in Figure 7, a thin oxide layer 83 (ca 100A) is formed on one surface 85 of a silicon wafer 87.
Next, a tungsten silicide layer capped with silicon nitride is deposited over the thin oxide layer 83 and selectively etched to leave a predetermined tungsten silicide conductor region 89. The silicon nitride is now etched from above the metal layers.
Next, as shown in Figure 8, a silicon dioxide layer 91 is formed over the structure of Figure 7. As shown in Figure 8, the layer 91 does not grow over the tungsten silicide. The silicon nitride protects the metal layer from the oxidization process. Last, the silicon dioxide layer 91 can be fused with an oxide layer such as the layer 7 of the wafer 1 shown in Figure 1. As with the method of the second embodiment, there is no problem of trying to fuse two wafers, one of which has a metallic region protruding above the surface to be fused with the other wafer.
In the light of this description, modifications of the described embodiments, as well as other embodiments, all within the scope of the present invention as defined by the appended claims, will become apparent to persons skilled in this art.

Claims (26)

CLAIMS:
1. A method of fabricating a semiconductor device, the method comprising forming a conductor at a surface of a first wafer and fusing a second wafer with the said surface of the first wafer.
2. A method according to claim 1, wherein the conductor is a heavily doped region at the said surface of the first wafer.
3. A method according to claim 2, wherein the heavily doped region is formed by implantation or diffusion using a mask to create a predetermined pattern.
4. A method according to claim 3, further comprising the step of annealing after implantation.
5. A method according to any of claims 2 - 4, wherein the wafers comprise silicon and after formation of the heavily doped region a silicon dioxide film is grown on the said surface of the first wafer.
6. A method according to claim 1, wherein the conductor is a metal compound compatible with the first wafer.
7. A method according to claim 6, wherein the first wafer comprises silicon and the metal compound is a metal silicide.
8. A method according to claim 7, wherein the metal silicide is a tungsten silicide.
9. A method according to claim 7 or claim 8, wherein the said surface of the first wafer is first oxidised and then the metal silicide is deposited on the oxidised surface.
10. A method according to any of claim 7-9, wherein after deposition of the metal silicide, a silicon dioxide film is grown on the said surface of the first wafer.
11. A method according to any of claims 6-9, wherein the deposited metal compound is patterned before the wafers are fused.
12. A method according to claim 1, wherein the conductor is a metal.
13. A method according to claim 12, wherein the metal is patterned before the wafers are fused.
14. A method according to claim 12 or claim 13, wherein the wafers comprise silicon, at least one surface of the first wafer having been oxidised.
15. A method according to claim 4, wherein the metal layer is formed on an oxidized surface of the first wafer.
16. A method according to any of claims 5, 10, 14 or 15, wherein at least one surface of the second wafer is oxidised and the wafers are fused at their oxidised surfaces.
17. A method according to claim 1, wherein the wafers comprise GaAs.
18. A method according to any preceding claim, wherein the wafers are fused by application of heat and pressure.
19. A semiconductor device comprising at least one control gate electrode, the control gate electrode being formed of a conductor and sandwiched between two semiconductor wafers which are fused together.
20. A device according to claim 19, wherein the metal control gate electrode is the gate electrode of a field effect transistor.
21. A device according to claim 19, wherein the control gate electrode is a back gate buried in a patterned wafer having an etched side surface on which is formed a regrowth structure.
22. A device according to claim 21, wherein the regrowth structure is overlaid with a front gate electrode.
23. A device comprising a stack of field effect transistors and having at least one buried gate electrode as defined in claim 20.
24. A device according to claim 23, wherein the gate electrodes in adjacent layers of transistors are not located above one another.
25. A method of fabricating a semiconductor device, the method being substantially as hereinbefore described with reference to any of the accompanying drawings.
26. A semiconductor device, substantially as hereinbefore described with reference to any of the accompanying drawings.
GB9511156A 1995-06-02 1995-06-02 Semiconductor device and method of making same Expired - Fee Related GB2301707B (en)

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GB2301707A true GB2301707A (en) 1996-12-11
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2775831A1 (en) * 1998-03-05 1999-09-03 Ind Tech Res Inst Back-etched or smart cut SOI wafer production with a buried layer especially for manufacturing bipolar junction transistor and BiCMOS ICs

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0238066A2 (en) * 1986-03-18 1987-09-23 Fujitsu Limited A method for effecting adhesion of silicon or silicon dioxide plates
US5281834A (en) * 1990-08-31 1994-01-25 Motorola, Inc. Non-silicon and silicon bonded structure and method of manufacture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0238066A2 (en) * 1986-03-18 1987-09-23 Fujitsu Limited A method for effecting adhesion of silicon or silicon dioxide plates
US5281834A (en) * 1990-08-31 1994-01-25 Motorola, Inc. Non-silicon and silicon bonded structure and method of manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2775831A1 (en) * 1998-03-05 1999-09-03 Ind Tech Res Inst Back-etched or smart cut SOI wafer production with a buried layer especially for manufacturing bipolar junction transistor and BiCMOS ICs

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GB2301707B (en) 1999-12-22
GB9511156D0 (en) 1995-07-26

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