JPH10222422A - Cache memory control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To continuously hold the instruction code of a program which is necessary to periodically be operated and to shorten the processing time of second and subsequent period programs by collectively changing a single entry or plural entries in an unused state. SOLUTION: A processor 11 reads program instruction code data 121-i stored in a memory 12 and data 121-d necessary for an operation through a bus 14, operates them by using an arithmetic circuit 111 and stores the operated result in a register 112 and the memory 12 in the processor 11. It is program-controlled by repetitively executing a series of operation actions. When the invalidity instruction of the entry is given from the processor 11, a data field 132 is rewritten into the memory 12 and a state display field 133 is changed to the unused state. Consequently, the occupied time of the processor 11 is reduced after the period program is once stored in the cache memory 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a cache memory control system.

[0002]

2. Description of the Related Art Conventionally, there are many information processing apparatuses using a cache memory. Once the data including the instruction code is once stored in the high-speed cache memory, the second and subsequent reading and writing of the data do not require access to the low-speed memory, so that the program can be executed at high speed.

There is also an entry invalidation function (a function of making it unused) provided in the present invention, which covers the entire area of the cache memory.

[0004] However, none has a function of partially invalidating.

When an entry corresponding to the program instruction address in the cache memory is already in use at the time of executing a program which needs to be operated periodically, the currently used data is firstly swept out and the current data is used. There are also means for invalidating an entry (unused state), then copying new instruction code data to the entry, and validating (in use). In the case of this method, other multiple data using the same entry
If the contents stored in the cache memory are lost, it is necessary to read from the slow memory again, resulting in halving the effect of the high speed.

[0006]

SUMMARY OF THE INVENTION The present invention provides a means for reliably holding periodically used data (including an instruction code) in a high-speed cache memory. The effect is not to decrease.

[0007]

Means for solving the problems A cache memory control function having a plurality of entries is provided with means for invalidating (unused) a single or a plurality of entries. If the entry invalidation flag for control and the periodic program control entry invalidation flag are "invalidation not completed", the corresponding entry in which each instruction of the program that needs to be operated periodically should be stored. An instruction is provided for instructing an entry to be invalidated (unused state) to be invalidated, and then an instruction is provided for changing the periodic program control entry invalidation flag to “invalidation completed state”.

When the processor tries to read the instruction code of the program or the data necessary for the operation from the memory, the cache memory control circuit calculates the entry to be stored, examines the status display field of the entry, and finds that the status display field is not set. In the case of the use state, the state display field is changed to the use state, and the data is stored (copied) in the data field. When the status display field is in use, data is not stored (copied) in the data field.

When the processor updates the value of the data stored in the data field of the operation result and writes it back again as the same data, the status display field is kept in use and the new data is stored in the data field. Store in field.

[0010] The new data is written back to the memory in response to a "write back instruction to the memory" from the processor.

On the other hand, when an instruction to invalidate the entry is issued from the processor, the data field is written back to the memory, and then the status display field is changed to an unused state.

When the processor attempts to execute the cache memory storage control unit for the first time, the entry invalidation flag for this cycle program control is "invalidation not yet completed". In response, an instruction to instruct the entry to be invalidated is executed.
By executing this instruction, the value of the current data field of each entry is written back to the memory, and then the status display field is set to an unused state. Thus, the preparation for storing (hitting) the periodic operation unit in the cache memory is completed.

Next, the periodic program control entry invalidation flag is updated to the "invalidation completed state", and the preprocessing of the cache memory storage control unit ends.

Subsequently, the instructions of the cyclic operation unit are sequentially executed while being stored in the respective entries.

When the execution of the instructions of all the cyclic operation units is completed, the processing of the first cyclically operated program ends.

In order to operate a periodic program,
When the information processing device detects the interruption by the periodic interruption means,
Execute this cycle program again.

Since the second and subsequent times, the entry invalidation flag for periodic program control is in the "invalidation completed state", the cache memory storage controller processing is performed in the first determination processing of the cache memory storage controller processing. Exit without doing anything.

Next, the execution of the instructions of the periodic operation unit is started. Since the instructions of these periodic operation units are already stored in the respective entries in the cache memory, the read processing is completed at a high speed and read from the memory. Is performed in the same way as

[0019]

FIG. 1 shows an information processing apparatus.

The information processing apparatus 1 includes a processor 11, a memory 12, a cache memory 13, and a bus 1 connecting these.
4

The processor 11 reads the program instruction code data 121-i stored in the memory 12 and the data 121-d required for the operation via the bus 14, and performs the operation using the operation circuit 111. Program control is performed by repeatedly performing a series of arithmetic operations for storing the result in the register 112 or the memory 12 in the processor 11.

The cache memory 13 is a memory that can be read and written at a higher speed than the memory 12, and uses a plurality of entries 131 for holding a copy of the memory 12 and the value of the address 122 of the data 121 in the memory 12 as the copy source. And a cache memory control circuit 134 that calculates an entry 1311 for storing the data 121.

Each entry has a data field 132,
The field 132 includes a status display field 133 indicating that the field is in use.

When the processor 11 attempts to read the instruction code 121-i of the program or the data 121-d required for the operation from the memory 12, the cache memory control circuit 134 calculates an entry 1311 to be stored, and displays the status of the entry 1311. The field 1331 is examined, and if the status display field 1331 is in the unused state, the status display field 1331 is changed to the in-use state, and the data 121 is stored (copied) in the data field 1321. When the status display field 1331 is in use, the data 121 is stored in the data field 13.
21 is not stored (copied).

Since the cache memory is generally expensive, it has a smaller capacity than the memory 12, and there are a plurality of objects using the same entry. For example, if the memory 12 is 0x
When there are from 80000000 to 0x8000FFFF, that is, in the case of 64 Kbytes, the cache memory 13 is mounted in a small amount such as 8 Kbytes, and
4K bytes / 8K bytes = 64 will use the same entry. The cache memory control circuit 134
For example, the data entry 1311 is calculated using a plurality of intermediate bits of the address (32-bit data) of the data to be stored as an entry index. When the capacity of one entry is 8 bytes, the number of entries is 8K bytes / 8 bytes = 1K, and the corresponding address is 0x0000.
The corresponding entry is determined by masking with 1FF8 and dividing the value by 8 (bytes) as an entry index.

The above is a general cache memory entry determination method.

When the processor 11 updates the value of the data stored in the data field 1321 with the result of the operation and writes it back as a new value of the same data, the status display field 1331 is kept in the in-use state. ,
The new data 121 is stored in the data field 1321.

The new data 121 is written back to the memory 12 in response to a write-back instruction 41 from the processor 11 to the memory.

On the other hand, when the processor 11 instructs the invalidation instruction 42 of the entry, the data field 13
21 is written back to the memory 12, and then the status display field 1331 is changed to an unused status.

The above is an embodiment of each means constituting the information processing apparatus 1.

An embodiment of software for controlling the information processing apparatus 1 is shown in FIGS.

FIG. 2 shows the overall configuration of software for controlling the information processing apparatus 1.

Software 3 for controlling information processing apparatus 1
Is software that includes a program 31 that operates periodically and performs some output using the information processing apparatus 1. The program 31 that operates periodically includes the information processing apparatus 1.
Is necessary for normal operation of the device, and does not necessarily directly affect the output.

The program 31 that operates periodically includes a cache memory storage control unit 311 and a periodic operation unit 312.

Each of the cache memory storage control unit 311 and the cyclic operation unit 312 is composed of a single or a plurality of instruction codes.
Is composed of a plurality of bytes of instruction code and operand data that can be interpreted and executed by.

The periodic operation unit 312 is stored from an address in the memory 12, for example, address 0x800001200, and the cache memory storage control unit 311 continuously stores the address at the young address (at the address where the processor 11 can continuously read the instruction). Is stored.

The cache memory storage control unit 311 has the configuration shown in FIG.
As shown in (1), this program first issues an invalidation instruction 22 to the entries 3121 to 312n so that the instruction codes of the cyclic operation unit 312 can be stored in the corresponding entries 3121 to 312n.

When the processor 11 attempts to execute the cache memory storage control unit 311 for the first time, the entry invalidation flag 313 for this period program control is “invalidation not yet completed”. Of the invalidation instruction 42 is executed. By executing this instruction, the entries 3121 to 312n
The value of the current data field 1321 of the entry is written back to the memory 12, and then the status display field 133
Set 1 to unused state. Thus, the preparation for storing (hitting) the periodic operation unit 312 in the cache memory 13 is completed.

Next, the periodic program control entry invalidation flag 313 is updated to "invalidation completed state", and the preprocessing of the cache memory storage control unit 311 is terminated.

Subsequently, the instructions of the cyclic operation unit 312 are sequentially executed while being stored in the corresponding entries 3121 to 312n. At this time, the status display field of each entry is changed to "in use".

When the execution of the instructions of all the cyclic operation units 312 is completed, the processing of the first cyclically operated program 31 ends.

In order to operate a periodic program,
When the information processing device 1 detects the interruption by the period interruption means 15, the information processing device 1 executes the present period program again.

After the second time, as shown in FIG. 4, since the entry invalidation flag 313 for periodic program control is in the "invalidation completed state", the first determination processing of the cache memory storage control unit 311 processing is performed. In 3111, the cache memory storage control unit 311 ends the processing without doing anything.

Next, the execution of the instruction of the periodic operation unit 312 is started. Since each instruction of the periodic operation unit 312 has already been stored in the entries 3121 to 312n in the cache memory 13, the read processing is completed at high speed. Each is executed in the same way as read from the memory 12.

[0045]

According to the present invention, the instruction code of the program that needs to be operated periodically can be reliably kept in the high-speed cache memory.
It is possible to reduce the processing time of the cyclic program after the first time. As a result, after the periodic program is once stored in the cache memory, the occupation time of the processor can be reduced as compared with before the present invention is applied, and the time for executing the exchange program can be increased in an electronic exchange or the like. , System performance can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an information processing apparatus of the present invention.

FIG. 2 is an explanatory diagram showing an overall configuration of software for controlling the information processing apparatus of the present invention.

FIG. 3 is an explanatory diagram showing a cache memory control sequence according to the present invention.

FIG. 4 is an explanatory diagram showing a cache memory control sequence according to the present invention.

[Explanation of symbols]

 11: processor, 111: arithmetic circuit, 112: register in processor, 12: memory, 121: data in memory, 121-i: instruction code, 121-d: data required for operation, 122: address of data in memory 13: cache memory, 131: multiple entries, 1311: entry, 132: data field, 1321: data field of entry, 133: status display field, 134: cache memory control circuit, 14: bus, 15: periodic interrupt means.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Junichi Fujiwara 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref.

Claims (2)

[Claims] A processor having means for reading an instruction code or data from a memory, performing an operation, and storing the operation result in a register or a memory inside the processor, and a memory having a function of storing an instruction code or data of a program. A high-speed cache memory for holding the data in the entry when the entry in which the data is to be entered when the content of the memory is read by the processor is not in use, and a bus having means for connecting these and reading and writing the data The cache memory is composed of a plurality of entries, and when the entry is in use, the processor does not store the data to be read in the entry and is not in use. In this case, the data that the processor is trying to read is stored in the above entry. And a function of setting the valid display means provided to indicate that the entry is in use to a use state, and setting the use state of the entry to an unused state by an instruction from the processor. A cache memory control device, comprising: a processor for changing a single entry or a plurality of entries to an unused state collectively in an information processing apparatus having a means for changing to a non-use state. 2. The software using the cache memory control device, wherein an entry used by the program which needs to operate periodically is set to an unused state before the program first operates, and then the program is executed. At the same time, the instruction code and data of the program are stored in the high-speed cache memory, and the entry is stored in a stage preceding the start of the second or later execution after the processing of the program that needs to operate periodically ends. 2. The cache memory control method according to claim 1, wherein the cache memory is not changed to an unused state.