JP3388518B2 - Program control unit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program control device, and more particularly to a program control device for efficiently performing data driven parallel processing in a stored program type information processing device.

[0002]

2. Description of the Related Art In a conventional stored program method (Neumann type) information processing apparatus, basically only one control flow can be executed except for some interrupt processing by some input / output devices. When it is attempted to perform a plurality of processes (processes) by changing the state of each data used in the program, first, as shown in FIG. 3 and FIG. The groups (processes A, B, C, D) are divided, and the individual data contents (F
LG1, 2) is checked, and the corresponding processing A, B, C,
The technique of branching to D was taken.

Further, as shown in FIG. 5, each process A,
In B, ... X, the execution time of the CPU is assigned by the process control routine by the timer interrupt and the flag sense, and in each process in the process, the execution time of the CPU is assigned by the control routine by the loop of the flag sense.

[0004]

However, in such a conventional stored program type information processing apparatus, the CPU execution time is assigned to each process by the process control routine based on the timer interrupt and the flag sense. In each process in the process, the execution time of the CPU is assigned by the control routine by the flag sense loop. Therefore, if it is a simple program, the time required for these controls and the labor for creating the control flow are not so much. However, when writing a program with high parallelism, such a method is slow in execution. For example, when trying to perform artificial intelligence processing, practical speed cannot be obtained, and program development is not possible. There was a problem that the efficiency of was not good.

Therefore, in the case of performing the above-mentioned artificial intelligence processing in which the load of software for controlling multiple CPUs is large, a dedicated programming language is used on expensive dedicated hardware. It was necessary to do so, and it was very difficult to realize with a conventional stored program type personal computer or workstation.

An object of the present invention is to provide a program control device for realizing hardware for executing a program having a high parallelism at low cost while maintaining compatibility with a conventional program. .

[0007]

The means of the present invention are as follows.

According to the present invention, each data processing means reads the content of predetermined read target data, performs predetermined data processing on the read target data, and based on the data processing result, the predetermined write target data content. A plurality of data processing means for rewriting, and a correspondence relationship storage means for preliminarily storing a correspondence relationship between each of the plurality of data and any one of the data processing means whose data is to be read, A detection unit that detects that the data has been rewritten by the data processing unit and a data processing unit that reads the data whose rewriting has been detected by the detection unit are searched from the correspondence relationship storage unit, and Execution control means for instructing the retrieved data processing means to execute each data processing. Characterized in that was.

[0009]

[0010]

[0011]

[0012]

[0013]

EXAMPLES Examples will be described below with reference to FIGS. 1 and 2.

1 and 2 are views showing an embodiment of a computer system to which the program control device according to the present invention is applied.

First, the structure will be described. FIG. 1 is a block diagram of a computer system 1. In FIG. 1, a computer system 1 includes a main memory group 2 and C.
PU group 3, tag memory 4, address counters 5 and 6, tag writing control unit 7, scanning control circuit 8, correspondence designation memory 9,
Interrupt arbitration circuit 10, access arbitration circuit 11, multi-CP
The U control circuit 12, the access control units 13 to 15, the address switching units 16 and 17, and the data switching unit 18,
Each unit is connected to the address bus 19, the data bus 20, and the control signal bus 22.

In FIG. 1, the tag memory 4, the address counters 5 and 6, the tag writing control unit 7, the scanning control circuit 8, the correspondence designation memory 9, the interrupt arbitration circuit 10, the access arbitration circuit 11, the multi-CPU control. The circuit 12, the access control units 13 to 15, the address switching units 16 and 17, and the data switching unit 18 constitute the program control device of the present invention.

The main memory group 2 includes a plurality of ROMs (Read
Only Memory), etc.
As shown in, a data area for storing data and a code area for storing a code are formed, and address designation is input from the CPU group 3 via the address bus 19, and
Data is transferred to and from the CPU group 3 via the data bus 20, and an access request from the CPU group 3 is converted into an access request signal by the access control unit 13 and input via the control signal bus 21. It

The CPU group 3 includes a plurality of CPUs (Central Pr
It is a multi-CPU configuration in which various processing units are connected, and the code stored in the code area of the main memory group 2 is read and various information processing (processes) are sequentially executed, and necessary when executing various information processing. Data
The data stored in the data area of the main memory group 2 is read and processed by the address designation output via the address bus 19, and the write signal (WRITE) is issued to the main memory by designating the address of the data area according to the processing result. Output to group 2 and rewrite data contents. This write signal is also output to the tag write control unit 7.

In this embodiment, as shown in FIG.
256 CPU1 to CPU256 are connected,
The configuration is also compatible with multiple CPUs in which a plurality of CPUs are connected on the same bus.

The tag memory 4 is a RAM (Random Accesses).
Memory) and the like, and stores a plurality of flag data (FLG1, FLG2, ...) Indicating that rewriting has been performed in the address unit of the data area in the main memory group 2. Therefore, as shown in FIG. And a tag-in signal (TAGI
N), flag data is set for each memory area, and the stored flag data is read from the tag out (TAG OUT) by the scanning of the scanning control circuit 8.

The address counter 5 counts up for each boundary address when the scan control circuit 8 scans the inside of the tag memory 4, and the address counter 6 has a flag when the scan control circuit 8 scans the inside of the tag memory 4. When in the set state, the scan control circuit 8 further scans the address (corresponding to 1 to 1) in the correspondence designation memory 9 corresponding to the flag.
Count up 8).

The tag write controller 7 outputs a tag-in signal to the tag memory 4 in response to the write signal input from the CPU group 3 and sets flag data corresponding to the write data area in the main memory group 2. . Further, in the tag writing control unit 7, the scanning control circuit 8 to the scanning control circuit 8 are
The tag memory 4 is scanned through the tag out (TAG OUT) to check the flag data, and the corresponding one direction (vertical direction in FIG. 2) in the corresponding designated memory 9 is scanned by the address count of the address counter 5 and stored. When the data is checked and the flag data is set, the correspondence 2 to correspondence 8 directions (horizontal direction in FIG. 2) are addressed from the corresponding data storage area of correspondence 1 in the correspondence designation memory 9 corresponding to the flag data. The stored data is checked by scanning with the address count of the counter 6, the interrupt valid signal IRQ is output to the interrupt arbitration circuit 10 according to the description content of the stored data, and the interrupt arbitration circuit 10 and the access arbitration circuit 11 are supplied. It outputs an interrupt request signal, outputs CPU designation data to the multi-CPU control circuit 13, and reads it from the corresponding designation memory 9. The output address data is output to the designated CPU of the CPU group 2 via the data bus 20 switched by the data switch 18. Further, the scanning control circuit 8 outputs an address switching request signal to the access control unit 14 when scanning the tag memory 4, and outputs an address switching request signal to the access control unit 15 when scanning the corresponding designated memory 9. Output.

The correspondence designation memory 9 is composed of a RAM or the like, and as shown in FIG. 2, forms memory areas of correspondence 1 to correspondence 8, and the correspondence designation data is stored in each of the correspondence memory areas. The contents of the specified data are
Status data indicating effectiveness / invalidity , CPU designation data, and interrupt address data are stored.

The interrupt arbitration circuit 10 outputs an interrupt request signal to a designated CPU of the CPU group 2 in response to the interrupt valid signal IRQ and the interrupt request signal input from the scan control circuit 8. The access arbitration circuit 11 receives the scan control circuit 8 and the CP in response to the interrupt request signal input from the scan control circuit 8.
Arbitrate access from U group 2.

The multi-CPU control circuit 12 designates the CPU in the CPU group 2 for executing the interrupt processing according to the CPU designation data input from the scanning control circuit 8.

The access control unit 13 accesses the main memory group 2 according to the interrupt request signal input from the CPU group 3 and the interrupt arbitration circuit 10.

When the scanning control circuit 8 scans the tag memory 4, the access control unit 14 outputs a switching signal to the address switching unit 16 and switches the address bus 19 connected to the tag memory 4 to the address counter 5 side. At the same time, the interrupt address data is sent from the correspondence designation memory 9 to the data bus 2
When outputting to 0, a switching signal is output to the data switching device 18, and the data bus 20 is switched to the corresponding designated memory 9 side.

The access control unit 15 is provided with an address switching unit 17 when the scan control circuit 8 scans the correspondence designation memory 9.
A switching signal is output to switch the address bus 19 connected to the corresponding designated memory 9 to the address counter 6 side.

The address switching unit 16 is the access control unit 1
Switching control is performed by a switching signal input from the address bus 4, and the address bus 19 is connected to the tag memory 4 side and the address counter 5.
Switch to the side. The address switching unit 17 is switching-controlled by a switching signal input from the access control unit 15, and switches the address bus 19 between the correspondence designation memory 9 side and the address counter 6 side.

The data switching section 18 includes an access control section 15
Switching is controlled by a switching signal input from the data bus 20, and the data bus 20 is switched between the scanning control circuit 8 side and the correspondence designation memory 9 side.

The operation of this embodiment will be described below.

First, the computer system 1 of this embodiment
In order to explain the operation of, the following case is set as one programming example processed in the computer system 1.

In FIG. 2, the data 1 stored in the data area in the main memory 2 is processed by the code 1 and is processed by the CPU 1 when any of the CPUs rewrites the data 1. To do. The data 2 is processed by the code 2 and the code 3, and when the data 2 is rewritten by any of the CPUs, the CPU 1 processes the code 2 and the CPU 3 processes the code 3.

In order to perform this operation, it is necessary to make initial setting of the tag memory 4 and setting of the correspondence designation memory 9.

The correspondence designation memory 9 is set by one of the CPUs in the CPU group 2 via the address bus 19, the data bus 20, and the control signal bus 21. At this time, the address switch 17 and the data switch. The device 18 is switched by the access control unit 15 so that the corresponding designated memory can be accessed from the CPU.

As shown in FIG. 2, the content of the setting is, for example, "0" in the area indicated by (1) in the memory area of the correspondence 1.
1019057 "," 0101BF2D "in the area indicated by (2) in the corresponding 1 memory area, and" 0103 "in the area indicated by (3) in the corresponding 2 memory area.
It shall be set as D302 ″ and stored.

At this time, as shown in FIG. 2, addresses "0045 to 004C"("0040 to 004C" on the main memory 2 are stored.
Data 1 of 004F ”is assigned to Code 1 of address“ 9057 ”and addresses“ 327A to 3289 ”(“ 327
0-327F ") data 2 is address" BF2D- "
It is associated with the code 2 of No. 2 and the code 3 of "D302-". In the example shown in FIG. 2, the main memory 2
Since the data area of is divided by a 16-byte boundary, the address bits A14 to A4 of the CPU are used for data identification, and A15 and A3 to A2 are used for identification of the corresponding code number when accessing the corresponding designated memory 9. Since the designated data has 4 bytes of the 2-byte address 7, the 1-byte CPU designated data 8 and the 1-byte status register 9, A1 to A0 are assigned for this designation. (Note that the address space of the CPU is represented by 2 bytes A15 to A0.)
Explaining "01019057", the left end "0"
The 1-byte 1-byte data indicates status data indicating the validity / invalidity of the interrupt , the next 1-byte data “01” indicates the CPU-designating data that designates the CPU number in the CPU group 3, and the next “1-” The 2-byte data of 9057 ″ represents the interrupt address data in the main memory 2.

When the status data is "00", this correspondence is invalid, and when the status data is "01", it is valid. The data stored in the storage areas (1) and (2) indicates that the interrupt by the CPU 1 is valid, and (3) indicates that the interrupt by the CPU 3 is valid. The above is the necessary setting contents of the correspondence designation memory, and the status is set to "00" for all other unnecessary portions.

Next, regarding the initial setting of the tag memory 4, this is automatically null-cleared (zero-clear "0") as described later.

The operation in the computer system 1 when the CPU 1 rewrites the data 2 in the setting contents will be described below.

First, in FIG. 2, the CP in the CPU group 2
When U1 writes the data 1 in the data area "327A" in the main memory 2, the tag write controller 7 outputs "1" as the TAGIN signal to the corresponding area in the tag memory 4 by the WRITE signal. Thereby, "1" is set in the FLG 2 in the tag memory 4 shown in FIG. 2 (however, 1-bit data is stored in the tag memory).

In parallel with this, the tag memory 4 is scanned by the scanning control circuit 8, and the data boundary is counted up by the address counter 5. When the count becomes "327" due to this count-up, the address switching request signal is sent from the scanning control circuit 8 to the access control unit 1.
4 and a switching signal is output from the access control unit 14 to the address switching unit 16, and the address switching unit 16 switches the address bus 19 connected to the tag memory 4 from the CPU 3 side to the address counter 5 side. The contents of FLG2 in the above are read out from TAGOUT.

At this time, since FLG2 is set to "1", in response to this, the scan control circuit 8 outputs an address switching request signal to the access control unit 15, and the access control unit 15 outputs the address switching unit 17. A switching signal is output to the address designation circuit 9 by the address switching unit 17, the address bus 19 connected to the correspondence designation memory 9 is switched from the CPU 3 side to the address counter 6 side, the address counter 6 is counted up, and the correspondence designation memory 9 shown in FIG. Correspondence 1 to
8 are scanned.

First, in FIG. 2, the scan control circuit 8 checks the memory area (2) "0101BF2D" of the corresponding 1 and the data of the status portion "01" is sent to the scan control circuit 8 via the data bus 20. Since the interrupt is enabled, the IRQ is sent to the interrupt arbitration circuit 10 and the CPU-designated data “01” (designating the CPU 1) is sent to the data bus 20.
Is output to the multi-CPU control circuit 12 via.

When the interrupt of the designated CPU 1 is permitted in this way, a data switching signal is output from the scanning control circuit 8 to the data switching unit 18, and the corresponding designated memory 9 interrupts the data bus 20 via the data switching unit 18. The address data "BF2D" is output. Then, the interrupt processing for the main interrupt address of the main memory 2 of the CPU 1, that is, the code 2 in the code area is performed. At this time, C
The scanning of the scanning control circuit 8 is performed even while the interrupt processing to the code 2 is executed by the PU 1, and the correspondence designation memory 9 is generated by the count up of the address counter 6.
Correspondence 2 in the correspondence designated memory 9 is scanned, and the memory area (3) “0103D302” of correspondence 2 in the designated correspondence memory 9 is checked, and this data similarly requests the CPU 3 to perform interrupt processing to the interrupt address “D302”. , C
The PU3 executes an interrupt process for the code 3.

Next, when the address counter 6 counts up, the correspondence 3 in the correspondence designation memory 9 is scanned, and when the memory area (4) "00065010" is checked, the status is "00", so the scan control circuit. At 8, the scan for data 2 (FLG2) is stopped. Then, by setting the output TAGIN of the tag writing control unit 7 to "0", the contents of FLG2 are automatically cleared to "0". After that, the address counter 5 is counted up again to repeat the same scanning.

Further, in the above embodiment, the I / O device is designated by associating it with the memory address 2.
When the specified data is input from / O or when the specified data is output to the specified I / O, the corresponding process can be performed.
It is possible to quickly deal with more detailed processing conditions than the / O interrupt control.

In the above embodiment, the data boundary in the main memory 2 is 16 bytes, the number of codes corresponding to one data is 8, the maximum number of multi-CPUs is 256, and the address space of the CPU is Although 64 Kbytes is used, by configuring these circuits by changing these values, it is possible to freely select cost (required memory number) or performance (efficiency, speed).

For example, by enlarging the data boundary, dividing the code area by the boundary, reducing the number of multiple CPUs, and assigning "00" of the CPU designation to the status interrupt disable, the necessary tag memory and corresponding designation memory are allocated. Can be reduced and vice versa for more flexible and efficient programming.

Therefore, by mounting the program control apparatus of the present invention on an information processing apparatus such as a conventional stored program type computer system, parallel programming and conventional sequential execution format programming are executed on one piece of hardware. Moreover, since these intermediate programming can be executed, it is possible to realize at low cost an intermediate-stage information processing device for moving to parallel programming and hardware that will become mainstream in the future. It is also possible, for example, to execute parallel programming on a personal computer owned by the individual. Further, since it is compatible with multiple CPUs, it is possible to easily improve the processing efficiency of the information processing apparatus even when it is difficult to program conventionally and the effect of increasing the number of CPUs cannot be obtained. .

[0051]

According to the present invention, even in the case where a plurality of data and a plurality of data processing means carry out cooperative data processing while having a complicated dependency relationship, any data processing purpose can be used. It is possible to memorize the correspondence relation of, and perform automatic control based on this correspondence relation, and each data processing means itself always checks whether or not the data related to its processing is rewritten from a plurality of data. It is not necessary to check, and it is possible to efficiently execute only necessary processing when necessary, and in particular, it is possible to significantly improve programming efficiency in parallel programming and data processing efficiency in a multiprocessor system.

Also, since it can be applied to multiple CPUs,
Conventionally, it is possible to easily improve the processing efficiency of the information processing apparatus even when the programming is very difficult and the effect of increasing the number of CPUs cannot be obtained.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a computer system to which a program control device of the present invention is applied.

FIG. 2 is a diagram showing a configuration of a main memory, a tag memory, a correspondence designation memory, and a CPU group in FIG.

FIG. 3 is a diagram showing an example of a process flow processed by a conventional information processing apparatus of a stored programming system.

FIG. 4 is a diagram showing an example of another process flow processed by a conventional information processing apparatus of a stored programming system.

FIG. 5 is a diagram showing an example of a process flow in which parallel processing is performed by a conventional stored programming type information processing apparatus.

[Explanation of symbols]

1 computer system 2 main memory group 3 CPU group 4 tag memory 5 address counter 6 address counter 7 Tag writing control unit 8 Scan control circuit 9 Corresponding designated memory 10 interrupt arbitration circuit 11 Access arbitration circuit 12 Multi CPU control circuit 13, 14, 15 Access control unit 16, 17 Address changer 18 Data switch 19 address bus 20 data buses 21 Control signal bus

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 9/46-9/54 G06F 15/16-15/177 G06F 15/82 G06F 13/38-13/42 G06F 13 / 24-13/34

Claims (5)

(57) [Claims] 1. Each data processing means reads read target data from a storage area of predetermined read target data, performs predetermined data processing on the read target data, and writes a predetermined write target based on the data processing result. Correspondence between a plurality of data processing means for rewriting write target data in the data storage area and one of the data processing means for reading each data for each of the plurality of data storage areas Correspondence storage means that is stored in advance, detection means that detects that the data has been rewritten by any of the data processing means, and the data that is the target of reading the data for which rewriting has been detected by the detection means The processing means is searched from the correspondence storage means, and the searched data processing means A program control device comprising: execution control means for instructing execution of each data process. 2. The execution control means searches the correspondence relation storage means and gives an execution instruction independently of the execution of each data processing means, and the correspondence relation is stored in the correspondence relation storage means. 2. The program control device according to claim 1, wherein a plurality of data processing means are caused to perform data processing in parallel. 3. The detection means holds rewriting information for a plurality of data for which data has been rewritten, and searches the held rewriting information independently of the execution of each data processing means. TURMERIC line the detection operation
The program control device according to claim 1 or 2, characterized in that . 4. Each of the data processing means has a predetermined storage area.
By executing the program stored in the area
Predetermined data processing, and the correspondence storage means stores a program for each data processing.
Storage area where is stored and C that executes the program
A PU is stored in association with each data storage area, and the execution control means stores a data processing program.
Storage area and CPU for executing the program
Is searched, and the searched CPU is searched.
Instructs This <br/> a program control device according to claim 1, wherein the execution of the program stored in the storage area. 5. A CPU capable of executing each data processing
There are a plurality of the execution control means , and the execution control means divides the retrieved CPU.
By generating a load signal, the plurality of CPUs
Of the retrieved CPU for the retrieved CPU of
The program control device according to claim 4 , wherein the program control device instructs execution of a program stored in the area .