JPH10215290A - Digital demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the digital demodulation circuit that detects a carrier frequency error with high accuracy even when a carrier frequency error is large and compensates the error. SOLUTION: A plurality of paths are provided through which a different fixed value ϕoff is added to a phase rotation signal a9 denoting a carrier frequency error in a delay detection signal and averaging is conducted in each path after a modulo arithmetic operation. Then the fixed value ϕoff is subtracted from the mean value of each path to obtain carrier frequency errors a21-1, a21-2, a21-3. Then the carrier frequency errors for each path are selected or combined to detect a carrier frequency error a10 with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a demodulation circuit used in a digital radio communication system. In particular, the present invention relates to a digital demodulation circuit including an automatic frequency control circuit for correcting a carrier frequency error of a signal received from a partner station.

[0002]

2. Description of the Related Art FIG. 6 shows a configuration example of a conventional digital demodulation circuit. Here, a circuit configuration corresponding to a π / 4 shift DQPSK modulation signal is shown (reference: Yamamoto et al., “3.
Configuration and characteristics of 84kbps π / 4QPSK burst demodulator ",
RCS92-100, IEICE technical report).

In the figure, a received signal a1 in an intermediate frequency band is shown.
Is orthogonally detected by the output signal of the local oscillation circuit 32 in the orthogonal detection circuit 31 to become a complex baseband signal a2,
Further, the signal is converted into a phase signal a3 by the phase detection circuit 33.
The clock recovery circuit 34 detects the clock phase of the received signal from the phase signal a3, and outputs a recovered clock a4 synchronized with the symbol identification point. The latch 35 samples the phase signal a3 at the symbol identification point given by the reproduced clock a4, and outputs a clock-synchronized phase signal a5. The delay circuit 36 outputs a delay signal a6 obtained by delaying the phase signal a5 by one symbol section. Subtraction circuit 37
Subtracts the delayed signal a6 from the phase signal a5 and outputs a delayed detection signal a7 for one symbol period.

Here, when there is no carrier frequency error, the phase angle θ of the j-th sample of the delayed detection signal a7 is
_j is represented by θ _j = iπ / 2 + π / 4 (i = 0, 1, 2, 3) (1) as indicated by a circle in FIG. On the other hand, when there is a carrier frequency error Δf, the signal point rotates from a normal position as indicated by a cross in FIG. 7, and a code error due to noise is likely to occur. Δf
And the phase rotation Δθ has the following relationship: Δθ = 2πΔfT (2) Here, T is a symbol period.

The phase error detection circuit 38 detects the magnitude of the phase rotation. The phase error detection circuit 38 calculates Δθ _j = φ _j −θ _j (3) with respect to the delayed detection signal a7 to generate the phase rotation signal a9. Output. here,
φ _j is a delay detection signal of the j-th sample, and θ _j is a phase angle determination signal when i is selected so as to take a value closest to φ _j in equation (1). The phase rotation signal a9 is integrated by N symbols (N is a positive integer) in an integration circuit 39, is further divided by a symbol number N in a division circuit 40, is averaged, and calculates the phase rotation amount Δθ added to the differential detection signal a7. A carrier frequency error signal a10 shown in FIG. This phase rotation amount Δθ is

[0006]

(Equation 1)

[0007] Note that N is the number of symbols used for averaging, and the detection error decreases as N increases. The integration circuit 41 is used as a variable frequency oscillating means, and continuously integrates the carrier frequency error signal a10 to output a frequency conversion reference signal a11. The delay circuit 42 outputs a delayed phase signal a12 obtained by delaying the phase signal a5 by N symbols required by the integration circuit 39. The subtraction circuit 43 performs frequency conversion by subtracting the frequency conversion reference signal a11 from the delayed phase signal a12, and outputs a carrier frequency error correction signal a13. The carrier reproduction circuit 44 performs carrier reproduction from the carrier frequency error correction signal a13 and outputs a carrier phase signal a14. The subtraction circuit 45 outputs the carrier frequency error correction signal a1
3, the synchronous detection is performed by subtracting the carrier phase signal a14. The sign judgment circuit 46 judges the sign of the synchronous detection signal a15 output from the subtraction circuit 45, and outputs the data signal a1
6 is output.

[0008]

In the conventional configuration, FIG.
When the noise is extremely small, as shown in (1), the phase rotation due to the carrier frequency error can be correctly detected. However, when a large noise is added, a correct phase angle θ _j cannot be selected due to the noise as shown in FIG. The portion indicated by a circle in FIG. 8 is a portion where the phase rotation is increased by noise.
In the hatched portions, the phase angle θ _{j of the differential} detection signal is not the correct phase angle π / 4, but the phase angle 3π / 4 to which the phase angle π / 2 is added, so that an erroneous phase rotation is detected. Will be. That is, the hatched portion in FIG. 8 is erroneously detected as if it is a hatched portion (return). In this case the phase rotation [Delta] [theta] _f that is detected, the correct phase rotation as _{Δθ r, Δθ f = Δθ r} -kπ / 2 (k = ± 1, + 2) ... is represented as (5).

Therefore, as in the conventional configuration, when the integrating circuit 39 and the dividing circuit 40 add and average according to the equation (4), the average value converges not to the correct value Δθ but to Δθ ′ including an error. . Further, as Δf increases, the probability of occurrence of a decision error increases, so that the carrier frequency detection accuracy further deteriorates. In particular, if a conventional configuration is used for a synchronous detection circuit that requires high-accuracy carrier frequency error detection, the code error rate is significantly degraded.

It is an object of the present invention to provide a digital demodulation circuit capable of detecting and compensating for a carrier frequency error with high accuracy even when the carrier frequency error is large.

[0011]

In the conventional configuration, there has been a problem that, due to an erroneous determination of θ _j , it does not converge to a correct phase rotation estimated value during averaging. In the present invention, a plurality of paths for adding different fixed values φ _off to the phase rotation signal Δθ _j obtained by the equation (3) are prepared. Then, for each path, averaging is performed after the modulo operation represented by u (θ) in equation (6), and an average value S _path is obtained.

[0012]

(Equation 2)

Next, the average value S _path for each _path is

[0014]

(Equation 3)

After subtracting the fixed value φ _off as shown in FIG. 3, the value is converted into a carrier frequency error Δf. FIG. 4 shows the relationship between the input carrier frequency error and the detected carrier frequency error when the fixed value φ _off is used as a parameter. As shown here, it can be seen that there is a region where the detection accuracy is high for each fixed value φ _off . For example, when φ _off = −π / 8, the detection accuracy is high when the carrier frequency error is in the range of −16 kHz to −8 kHz, and when φ _off = + π / 8, the detection accuracy is high when the carrier frequency error is in the range from 8 kHz to 16 kHz. You can see that.
Therefore, by selecting or synthesizing the carrier frequency error of each path in accordance with the detected phase rotation signal, it is possible to detect the carrier frequency error with high accuracy, and because of the open loop type, high-speed pull-in is also possible. Can be realized at the same time.

The digital demodulation circuit according to claim 1 is
An open-loop carrier frequency error correction unit is provided. As the frequency error detecting means, an adding means, a correcting means, a smoothing means for realizing the above function for each path,
Subtracting means and selection combining means for selecting or combining carrier frequency errors detected for each path are provided. Thereby, even when the noise and the carrier frequency error are large, the carrier frequency error can be detected with high accuracy.

A digital demodulation circuit according to claim 2 is
In addition to the carrier frequency error correction means of the open loop configuration, the carrier frequency error correction means of the closed loop configuration is provided and a dual loop configuration is provided for switching between them. The frequency error detecting means has the same configuration as the frequency error detecting means of the first aspect. As a result, since the operation is performed so as to suppress the jitter in the closed loop after the pull-in in the open loop, the carrier frequency error correction can be performed with higher accuracy than the digital demodulation circuit of the first aspect.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows an embodiment of the digital demodulation circuit according to the present invention. In the present embodiment, synchronous detection is applied to the carrier recovery method. In the figure, a received signal a1 in the intermediate frequency band is subjected to quadrature detection by a quadrature detection circuit 31 by an output signal of a local oscillation circuit 32 to become a complex baseband signal a2, and further converted to a phase signal a3 by a phase detection circuit 33. . The clock recovery circuit 34 detects the clock phase of the received signal from the phase signal a3, and outputs a recovered clock a4 synchronized with the symbol identification point. The latch 35 samples the phase signal a3 at the symbol identification point given by the reproduced clock a4, and outputs a clock-synchronized phase signal a5. The delay circuit 36 outputs a delay signal a6 obtained by delaying the phase signal a5 by one symbol section. The subtraction circuit 37 subtracts the delayed signal a6 from the phase signal a5 and outputs a delayed detection signal a7 for one symbol section.

The symbol determination circuit 11 determines a symbol so as to minimize the phase rotation error of the differential detection signal a7 synchronized with the reproduced clock, and outputs a phase angle determination signal a8 indicating a normal signal point phase. The subtraction circuit 12
The phase detection signal a8 is subtracted from the differential detection signal a7, and a phase rotation signal a9 indicating the phase difference is output. here,
The differential detection signal a7 corresponds to φ _j in equation (3), the phase angle determination signal a8 corresponds to θ _j in equation (3), and the phase rotation signal a9 corresponds to Δθ _j in equation (3). That is, the symbol determination circuit 11 and the subtraction circuit 12 correspond to the phase error detection circuit 38 having the conventional configuration shown in FIG.

The phase rotation signal a9 output from the subtraction circuit 12 is branched into three paths here. The phase rotation signal a9 branched to the first path is smoothed via an integration circuit 39-1 for integrating the number N of symbols and a division circuit 40-1 for dividing the output of the integration circuit by the number N of symbols. It is output as a first phase error signal a21-1. The phase rotation signal a9 branched to the second path is added to the addition circuit 13-
Fixed value φ output from fixed value output circuit 14-1 at 1
_off = −π / 8 and added as a first fixed-value corrected phase signal a22-1. The correction circuit 15-1 performs a modulo operation shown in Expression (6) on the first fixed value correction phase signal a22-1. The output of the correction circuit 15-1 is smoothed via an integration circuit 39-2 for integrating the number N of symbols and a division circuit 40-2 for dividing the output of the integration circuit by the number N of symbols. The output of the division circuit 40-2 is subtracted by the fixed value φ _off = −π / 8 output from the fixed value output circuit 14-1 by the subtraction circuit 16-1, and the second phase error signal a
Output as 21-2.

The phase rotation signal a9 branched to the third path
Is added to the fixed value φ _off = + π / 8 output from the fixed value output circuit 14-2 by the adder circuit 13-2, and is output as a second fixed value correction phase signal a22-2. The correction circuit 15-2 performs a modulo operation shown in Expression (6) on the second fixed value correction phase signal a22-2. Correction circuit 15
The output of -2 is an integration circuit 39 for integrating the number of symbols N.
-3 and a division circuit 40-3 for dividing the output of the integration circuit by the number N of symbols. The output of the division circuit 40-3 is subtracted by the subtraction circuit 16-2 from the fixed value φ _off = + π / 8 output from the fixed value output circuit 14-2 to obtain a third value.
Is output as the phase error signal a21-3.

The selection / synthesizing circuit 17 inputs the phase error signals a21-1 to a21-3 for each path, performs selective synthesis, and outputs a carrier frequency error signal a10. In the selection / combination circuit 17, when the value of the phase error signal a21-1 of the path not subjected to the fixed value correction is less than ± π / 8, the phase error signal a21- of the other two paths subjected to the fixed value correction.
2, the average value of a21-3 is used as the carrier frequency error signal a1.
Output as 0. When the value of the phase error signal a21-1 of the path not subjected to the fixed value correction is equal to or more than + π / 8, the phase error signal a21 of the path subjected to the correction of the fixed value −π / 8 is used.
-2 is output as the carrier frequency error signal a10.
Further, the phase error signal a21−
When the value of 1 is equal to or smaller than -π / 8, the phase error signal a21-3 of the path corrected by the fixed value + π / 8 is output as the carrier frequency error signal a10.

The configuration from the adding circuit 13 to the selecting / synthesizing circuit 19 is a characteristic part of the frequency error detecting means in the digital demodulating circuit according to the first aspect. The adding means, the correcting means, the smoothing means, and the subtracting means are respectively provided. And a selective combining means. The integration circuit 41 is used as a variable frequency oscillating means, and continuously integrates the carrier frequency error signal a10 to output a frequency conversion reference signal a11.

The delay circuit 42 has a function of N
A delayed phase signal a12 obtained by delaying the phase signal a5 by a symbol is output. The subtraction circuit 43 outputs the delayed phase signal a1
2 to perform frequency conversion by subtracting the frequency conversion reference signal a11, and outputs a carrier frequency error correction signal a13. The carrier reproduction circuit 44 performs carrier reproduction from the carrier frequency error correction signal a13 and outputs a carrier phase signal a14. The subtraction circuit 45 performs synchronous detection by subtracting the carrier phase signal a14 from the carrier frequency error correction signal a13. The sign determination circuit 46 includes a subtraction circuit 45
Performs a code determination on the synchronous detection signal a15 output from, and outputs a data signal a16.

(Embodiment Corresponding to Claim 2) FIG.
An embodiment of the digital demodulation circuit according to the present invention will be described. In the present embodiment, synchronous detection is applied to the carrier recovery method. In the figure, a quadrature detection circuit 31, a local oscillation circuit 32, a phase detection circuit 33, a clock recovery circuit 34, and a latch 35 have the same configurations as those shown in FIG.
Is output. The phase signal a5 is frequency-converted by a subtraction circuit 21, which is a first carrier frequency error correction unit.
The delay circuit 36 outputs a delay signal a6 obtained by delaying the phase signal a23 frequency-converted by the subtraction circuit 21 by one symbol period. The subtraction circuit 37 subtracts the delay signal a6 from the phase signal a23, and outputs a delayed detection signal a7 for one symbol section.

The symbol detection circuit 11 outputs the differential detection signal a
7 is determined so as to minimize the phase rotation error of the signal 7 and the phase angle determination signal a8 indicating the normal signal point phase.
Is output. The subtraction circuit 12 subtracts the phase angle determination signal a8 from the differential detection signal a7, and outputs a phase rotation signal a9 indicating the phase difference. The phase rotation signal a9 output from the subtraction circuit 12 is branched into three paths here. Integrator 39-1 and divider 40 provided in the first path
-1, an addition circuit 13-1, a fixed value output circuit 14-1, a correction circuit 15-1, and an integration circuit 39 provided in the second path
−2, division circuit 40-2, subtraction circuit 16-1, addition circuit 13-2 provided in the third path, fixed value output circuit 14
−2, correction circuit 15-2, integration circuit 39-3, division circuit 40-3, subtraction circuit 16-2, and selection synthesis circuit 17
Has the same configuration as each unit shown in FIG.
7 outputs a carrier frequency error signal a10.

The configuration from the adding circuit 13 to the selecting / synthesizing circuit 19 is a characteristic part of the frequency error detecting means in the digital demodulating circuit according to the second aspect. The adding means, the correcting means, the smoothing means, and the subtracting means are respectively provided. And a selective combining means. The phase rotation signal a9 output from the subtraction circuit 12 is input to the multiplication circuit 22, and is multiplied by the gain output from the gain output circuit 23, and
Is input to The initial value setting circuit 25 includes an addition circuit 24
And the carrier frequency error signal a10 output from the selection / combination circuit 17 are input. The delay circuit 26 delays the output signal a24 of the initial value setting circuit 25 and inputs the output signal a24 to the addition circuit 24. The addition circuit 24 and the delay circuit 26 constitute a complete integration type loop filter.

The integrating circuit 41 is used as a variable frequency oscillating means, and continuously integrates the output signal a24 of the initial value setting circuit 25 and outputs a frequency conversion reference signal a11. The subtraction circuit 21 performs frequency conversion by subtracting the frequency conversion reference signal a11 from the phase signal a5. On the other hand, the delay circuit 42 outputs a delayed phase signal a12 obtained by delaying the phase signal a5 by N symbols required by the integration circuit 39. The subtraction circuit 43 performs frequency conversion by subtracting the frequency conversion reference signal a11 from the delayed phase signal a12, and outputs a carrier frequency error correction signal a13. The carrier reproduction circuit 44, the subtraction circuit 45, and the sign determination circuit 46 have the same configuration as each unit shown in FIG. 1, and the sign determination circuit 46 outputs a data signal a16.

FIG. 3 shows an example of the configuration of the selective combining circuit 17 in the digital demodulation circuit of the present invention. In this configuration example, signal processing is performed using digital phase information. In the figure, the first
Is input to the adders 51 and 52 and the bit shift circuit 63. The second phase error signal a21-2 is input to the addition circuit 53 and the delay circuit 65. The third phase error signal a21-3 is input to the adding circuit 53 and the delay circuit 67.

The adding circuit 51 outputs the phase error signal a21-1.
And fixed value θ = π / 64 output from fixed value output circuit 54
And outputs a fixed value correction signal a31. The bit shift circuit 56 detects a bit of the same digit as the most significant bit of the fixed value from the fixed value correction signal a31 and outputs a bit signal a3
2 is output. Similarly, the addition circuit 52 adds the phase error signal a21-1 and the negative fixed value θ = −π / 64 output from the fixed value output circuit 55, and outputs a fixed value correction signal a33. The bit shift circuit 57 outputs the fixed value correction signal a33
, A bit of the same digit as the most significant bit of the negative fixed value is detected, and a bit signal a34 is output. The inversion circuit 58 outputs an inverted bit signal a35 obtained by inverting the bit signal a34. The logical sum circuit 59 performs a logical sum operation of the bit signal a32 and the inverted bit signal a35, and outputs a logical sum bit signal a
36 is output.

The adder circuit 53 outputs the phase error signal a21-2.
And the phase error signal a21-3 are added to output the added phase error signal a37. The division circuit 60 divides the added phase error signal a37 by 2 and averages the result, and outputs a composite signal a38. The delay circuit 61 latches the composite signal a38 according to the OR bit signal a36, and outputs a carrier frequency error signal a10 which is an output of the selection / combination circuit 17. With the above configuration, when the value of the phase error signal a21-1 of the path without fixed value correction is less than ± π / 8, the phase error signals a21-2 and a21 of the other two paths with fixed value correction performed
The average value of -3 is output as the carrier frequency error signal a10.

The inverting circuit 62 outputs a logical sum bit signal a36.
Is output as an inverted OR bit signal a39.
The bit shift circuit 63 detects the most significant bit of the phase error signal a21-1 and outputs a bit signal a40. The logical product circuit 64 performs a logical product operation of the inverted logical sum bit signal a39 and the bit signal a40, and outputs a logical product bit signal a4.
Outputs 1. The delay circuit 65 outputs the AND bit signal a4
1 to latch the phase error signal a21-2 and output the carrier frequency error signal a10 output from the selection / combination circuit 17.
Is output. With this configuration, when the value of the phase error signal a21-1 of the path for which the fixed value correction is not performed is + π / 8 or more,
The phase error signal a2 of the path corrected by the fixed value -π / 8
1-2 is output as the carrier frequency error signal a10.

The inverting circuit 66 outputs a logical product bit signal a41.
Is output as an inverted AND bit signal a42.
The delay circuit 67 latches the phase error signal a21-3 according to the inverted AND bit signal a42, and
And outputs a carrier frequency error signal a10 which is the output of With this configuration, when the value of the phase error signal a21-1 of the path for which the fixed value correction is not performed is −π / 8 or less, the fixed value +
The phase error signal a21-3 of the path corrected by π / 8 is output as the carrier frequency error signal a10.

FIG. 5 shows the bit error rate characteristics of the digital demodulation circuit of the present invention by simulation. In the simulation, π / 4 shift DQPSK is used as a modulation method, and synchronous detection is used as a detection method. In the AWGN environment, E _b / N ₀ = 8 dB, the symbol rate is 192 kHz, 32 symbols are used for integration, and the results are obtained when the number of paths is 5. This indicates that in the demodulation circuit without carrier frequency correction, the code error rate is greatly degraded as the carrier frequency error increases. Further, in the demodulation circuit using the carrier frequency correction of the conventional configuration, although the improvement is seen, the characteristics are deteriorated due to the influence when the carrier frequency error is large.

On the other hand, in the digital demodulation circuit (FIG. 1) according to the first aspect, even when the carrier frequency error is large, the influence is suppressed and the code error rate characteristic is improved.
In the digital demodulation circuit (FIG. 2) according to the second aspect, the bit error rate characteristic is further improved as compared with the configuration of the first aspect. This is because the detection error is gradually reduced in the closed loop section.

[0036]

As described above, the digital demodulation circuit according to the first aspect of the present invention has a simple circuit configuration using a phase signal, and has a high speed and high accuracy even when the carrier frequency error is large. Corrections can be made. Therefore, the code error rate can be improved even when applied to synchronous detection.

The digital demodulation circuit according to claim 2 is
In addition to the correction of the carrier frequency error according to the first aspect of the present invention, the correction accuracy can be improved by the closed loop, so that the correction of the carrier frequency error can be performed with higher accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a digital demodulation circuit according to the present invention described in claim 1;

FIG. 2 is a block diagram showing an embodiment of a digital demodulation circuit according to the present invention described in claim 2;

FIG. 3 is a block diagram showing a configuration example of a selection / synthesis circuit 17 in the digital demodulation circuit of the present invention.

FIG. 4 is a diagram for explaining the reason for improving characteristics by the configuration of the present invention.

FIG. 5 is a diagram showing a simulation result of a bit error rate characteristic.

FIG. 6 is a block diagram showing a configuration example of a conventional digital demodulation circuit.

FIG. 7 is a view for explaining phase rotation due to a carrier frequency error after differential detection.

FIG. 8 is a view for explaining the reason for the problem that occurs in the conventional configuration.

[Explanation of symbols]

 Reference Signs List 11 symbol determination circuit 12, 16, 21, 37, 43, 45 subtraction circuit 13, 24 addition circuit 14 fixed value output circuit 15 correction circuit 17 selection synthesis circuit 22 multiplication circuit 23 gain output circuit 25 initial value setting circuit 26, 36, Reference Signs List 42 delay circuit 31 quadrature detection circuit 32 local oscillation circuit 33 phase detection circuit 34 clock recovery circuit 35 latch 38 phase error detection circuit 39, 41 integration circuit 40 division circuit 44 carrier recovery circuit 46 sign determination circuit

Claims (2)

[Claims] 1. A delay detection means for delay-detecting a received signal, a phase error detection means for obtaining an amount of phase rotation of an output signal of the delay detection means, and a carrier frequency of the reception signal from an output signal of the phase error detection means Frequency error detecting means for detecting an error, variable frequency oscillating means for outputting a signal having a frequency corresponding to the carrier frequency error detected by the frequency error detecting means, delay means for delaying the received signal, and the variable frequency A carrier frequency error correcting means for frequency-converting the received signal delayed by the delay means using an output signal of the oscillating means, wherein the frequency error detecting means comprises an output of the phase error detecting means. A plurality of adding means for adding different fixed values to the signal, and modulo-executing outputs of the plurality of adding means, respectively. A plurality of correction means, a plurality of smoothing means for respectively smoothing the outputs of the plurality of correction means, and subtracting the fixed values added by the corresponding addition means from the outputs of the plurality of smoothing means, respectively. A digital demodulation circuit, comprising: a plurality of subtraction means; and a selection / combination means for selecting or combining outputs of the plurality of subtraction means and outputting the result. 2. A first carrier frequency error correcting means for frequency-converting a received signal; a delay detecting means for delay detecting an output signal of the first carrier frequency error correcting means; Phase error detecting means for determining the amount of phase rotation; frequency error detecting means for detecting a carrier frequency error of the received signal from an output signal of the phase error detecting means; multiplying an output signal of the phase error detecting means by a predetermined gain Multiplying means, loop filter means for smoothing an output signal of the multiplying means, initial value setting means for initializing the loop filter means with an output signal of the frequency error detecting means, and an output signal of the loop filter means Variable frequency oscillating means for providing a signal having a frequency according to the following to the first carrier frequency error correcting means; A second carrier frequency error correcting means for frequency-converting the received signal delayed by the delay means using the output signal of the variable frequency oscillating means. Detecting means, a plurality of adding means for adding different fixed values to the output signal of the phase error detecting means, a plurality of correcting means for modulo-calculating the outputs of the plurality of adding means, and a plurality of correcting means. A plurality of smoothing means for respectively smoothing the outputs; a plurality of subtraction means for respectively subtracting the fixed values added by the corresponding adding means from the outputs of the plurality of smoothing means; outputs of the plurality of subtraction means And a selecting / synthesizing unit for selecting or synthesizing and outputting.